JPH04237228A - Spread spectrum signal receiver - Google Patents

Abstract

PURPOSE:To constitute the receiver of a spread spectrum modulation signal with digital high circuit integration and software processing and to reduce the cost, to make the size small, to reduce the power consumption and to make the quality high. CONSTITUTION:A satellite signal received by an antenna 31 is fed to a high frequency processing circuit 32 and an output of a reference oscillator 33 is fed to a local oscillation circuit 34 and a local oscillation output whose frequency ratio is fixed and an output frequency of a reference oscillator are obtained. Then the local oscillation output is fed to the high frequency processing circuit 32, a satellite signal is subject to low frequency conversion into an intermediate frequency and subject to low frequency conversion into an intermediate frequency by the oscillation output from the reference oscillator 33. The intermediate frequency signal is fed to a binarizing circuit 35, in which the signal is binarized and a post stage feedback loop 50 for inverse spread and a feedback loop 60 for data bit demodulation are formed as digital circuits. Then a control signal for each of the feedback loops 50,60 is generated by the software processing of a computer 100.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving apparatus for a spread spectrum signal such as a satellite signal used, for example, in a position measuring system for a mobile object.

0002

[Prior Art] A system has been proposed that uses multiple artificial satellites orbiting the earth to measure the position of a moving object, but in this type of system, the satellite signal is subjected to spread spectrum modulation. ing. For example, GPS (Glo
In a positioning system called bal Positioning System, satellite signals are
0bps orbit parameter data (orbital data indicating satellite time, position, etc.) has a chip speed of 1.023 MHz
, spread spectrum modulation with a pseudo noise code (for example, GOLD code) with a period of 1 msec,
Two carrier waves of 2 MHz and 1227.6 MHz are orthogonally phase modulated (two-phase PSK modulated) and transmitted.

[0003] A GPS receiver receives signals from at least three satellites, performs tracking and spectrum despreading on each of the carrier waves, demodulates the orbit parameter data of each satellite, and calculates the arrival time of each signal. Data (the distance between the satellite and the user is obtained from the arrival time of this satellite signal) and the satellite position are obtained. The user's position can be determined three-dimensionally by drawing a sphere centered on each satellite with each measured satellite position as the origin and the measured distance as the radius, and from the intersection of the spheres.

FIG. 9 shows an example of the configuration of a conventional GPS receiver. The signal received by antenna 1 is sent to high frequency processing circuit 2
The carrier wave is 10.7MHz (signal band is 10
．． 7±1.023 MHz).

[0005] This intermediate frequency signal is supplied to a reception demodulation section as described below. This reception demodulation section is composed of a feedback loop for despreading that demodulates spread spectrum modulation, and a feedback loop that demodulates two-phase modulation using orbit parameter data bits.

In this example, a so-called tau dither tracking method is used in the feedback loop of the despread demodulation. That is, 20 is a code generator that generates a pseudo-noise code on the receiver side, which is a code generator with a phase difference of one chip time (
An early) code Me and a late (rate) code Md are generated. The early code Me and the rate code Md from the code generator 20 are supplied to the lead/lag code selector 21, and the code selector 21 is switched by the early/rate switch 22 every 1 msec. A synthesized pseudo-noise code is obtained from the selector 21 and is supplied to the balanced modulator 3. Then, the intermediate frequency signal from the high frequency processing circuit 2 is supplied to this balanced modulator 3,
Balanced modulation is performed by this synthetic pseudo-noise code.

The code generator 20 generates the phase and frequency (chip speed) is controlled so as to match the phase and frequency (chip speed) of the pseudo noise code included in the intermediate frequency signal from the high frequency processing circuit 2. As a result of this closed-loop control, a despread signal Si is obtained from the balanced modulator 3.

The feedback loop for demodulating the data bits is a Costas loop in this example. This Costas loop includes a carrier generator 4 consisting of a voltage-controlled variable frequency oscillator (hereinafter referred to as VCO) and a 90° phase shifter, first and second analog multipliers 5 and 6, and a low-pass filter 7. and 8, a third analog multiplier 9, and a loop filter 10.

The carrier generator 4 outputs first and second carrier signals (cos ωt and si
nωt) are obtained, which are fed to the first and second multipliers 5 and 6, respectively, and multiplied by the despread intermediate frequency signal (±Acos(ωt+φ)) from the balanced modulator 3, respectively. The outputs of the first and second multipliers 5 and 6 are passed through low-pass filters 7 and 8, respectively, to a third multiplier.
is supplied to multiplier 9 and multiplied. The output level of this third multiplier 9 reflects the phase difference between the carrier component of the received signal and the carrier from the carrier generator 4. The output of this multiplier 9 is supplied to the carrier generator 4 via the loop filter 10, which controls the VCO of the carrier generator 4, so that the phase of the output carrier signal of the carrier generator 4 is adjusted to the signal Si. is made to follow the carrier wave component of.

[0010] Also, the outputs of the first and second low-pass filters 7 and 8 of the Costas loop (±1/2Acosφ
and ±1/2 sinφ) are supplied to square law detectors 11 and 12, respectively, and subjected to square law detection. Then, each square law detection output is supplied to an adder 13 and added. The addition output of the adder 13 indicates the correlation level between the received pseudo-noise code and the pseudo-noise code from the code generator 20.

The added output of the adder 13 is supplied via an analog switch 14 to an early data holder 15 and a rate data holder 16, each consisting of an integrator. The analog switch 14 is an early rate switch 22
It is switched in synchronization with the switching of the lead/lag code selector 21 by a switching signal from the lead/lag code selector 21. Therefore, the early data holder 15 stores the correlation level output when the pseudo-noise code from the code generator 20 advances to the code Me, and the rate data holder 16 stores the correlation level output when the pseudo-noise code from the code generator 20 advances. The correlation level output when is the delay code Md is accumulated.

The correlation level outputs of the early data holder 15 and the rate data holder 16 are supplied to a subtracter 17 composed of, for example, a differential amplifier, and the difference between their correlation level outputs is obtained. This difference output reflects the phase error between the received pseudo-noise code and the pseudo-noise code from code generator 20. The output of this difference is the loop filter 1
8 to the VCO of the clock generator 23 as a code driving device, and as described above, the output pseudo-noise code of the code generator 20 is controlled so as to follow the received pseudo-noise code.

Further, the correlation level output from the adder 13 is supplied to a search/synchronization detector 19, and the search/synchronization detector 19 distinguishes between the received pseudo-noise code and the pseudo-noise code in the phase pulling process of the pseudo-noise code. Until a predetermined correlation is obtained, the frequency of the output clock from the clock generator 23 is greatly changed, and the frequency and phase of the pseudo-noise code from the code generator 20 are largely moved to perform the search. And once the correlation is obtained,
The search is stopped and thereafter the clock generator 23 is controlled by the output of the loop filter 18.

As described above, the spread spectrum modulated received signal is demodulated by the despreading feedback loop, and
The data bits are also demodulated by the Costas loop. A demodulated output of data bits is obtained from the low-pass filter 7, and the data bits are supplied to a data demodulation circuit (not shown) to demodulate trajectory parameter data.

[0015]

However, the above-mentioned conventional spread spectrum signal receiving apparatus requires the balanced modulator 3 in order to obtain correlation with the pseudo noise code on the receiver side. There was a problem that required analog circuit technology to maintain the balance of the device 3.

Furthermore, since the carrier generator 4 and the clock generator are provided with VCOs, circuit technology and circuit elements are required to maintain the linearity of each VCO. For this reason, the configuration of the receiving device is complicated and expensive, and
The device had become large.

Furthermore, the despreading feedback loop and the data
The feedback loop for demodulating bits has a problem in that parameters are fixed depending on circuit elements or parts, and it is not easy to change the parameters for control.

In view of the above points, the present invention aims to improve the above points through high digital integration and software.

[0019]

[Means for Solving the Problems] In order to achieve the above object, the spread spectrum signal receiving apparatus according to the present invention, when adapted to the embodiment of FIG. A high frequency processing circuit 32 that converts a spread signal into an intermediate frequency signal, a binarization circuit 35 that binarizes the intermediate frequency signal from this high frequency processing circuit 32, a pseudo noise code generator 51, and this pseudo noise code. A code driver 54 for controlling the phase and chip speed of the output pseudo-noise code of the generator 51, a binary signal from the binarization circuit 35, and the pseudo-noise code generator 51.
A first multiplication circuit 36 that performs multiplication with the output pseudo-noise code of
and a numerically controlled variable frequency oscillator 61 for outputting first and second carrier signals that follow the low frequency converted carrier wave included in the intermediate frequency signal and have mutually different phases by π/2. , the output signal of the first multiplier circuit 36,
First and third multiplication circuits 62 and 63 that multiply the first and second carrier signals, respectively, and counters to which output signals of the second and third multiplication circuits are supplied. second low-pass filters 64 and 65;
Upon receiving the counting result outputs which are the outputs of the second and third low-pass filters 64 and 65, from this counting result output,
The numerically controlled variable frequency oscillator 61 is configured such that the frequency and phase of the output carrier signal of the numerically controlled variable frequency oscillator 61 follow the carrier wave component included in the intermediate frequency signal.
means for generating a control signal for controlling the spread spectrum signal; and means for generating a control signal for controlling the spread spectrum signal so that the phase of the pseudo noise code output from the pseudo noise code generator 51 matches the phase of the pseudo noise code included in the spread spectrum signal based on the counting result output. code drive device 54
and a control device consisting of a microcomputer 100 having means for generating control signals for controlling.

[0020]

[Operation] According to the configuration of the present invention, a received spread spectrum signal is converted into an intermediate frequency signal, then binarized, and a feedback loop for subsequent despreading and data processing are performed.
The feedback loop for demodulating the bits is constructed digitally. The control signals for each feedback loop are then formed by software.

Therefore, there is no need for a balanced modulator like in the past, and since a numerically controlled variable frequency oscillator is used, there is no need to use a VCO like in the past, and the spread spectrum is simple and inexpensive. It becomes possible to realize a signal receiving device.

[0022]

[Embodiment] Fig. 1 is a block diagram of an embodiment of a spread spectrum signal receiving apparatus according to the present invention.
This is an example of the case of a receiving device of S.

A satellite signal (spread spectrum signal) received by the antenna 31 is supplied to a high frequency processing circuit 32 . Further, the output of a reference oscillator 33 consisting of a 18.414 MHz crystal oscillator is supplied to a local oscillation circuit 34,
This provides a local oscillation output whose frequency ratio is fixed to the output frequency of the reference oscillator.

This local oscillation output is then supplied to the high frequency processing circuit 32, and the satellite signal is converted to the first intermediate frequency 19.
The second intermediate frequency is 1.023 MHz by the oscillation output from the reference oscillator 33.
is converted into a second intermediate frequency signal Sif.

The second intermediate frequency signal Sif from the high frequency processing circuit 32 is supplied to a binarization circuit 35, where it is compared in level with a predetermined threshold value and binarized.

The binarized output Sd of this binarization circuit 35 is sent to a signal multiplier 3 composed of an exclusive OR circuit.
6.

In this example, as in the previous example, the feedback loop 50 for despread demodulation uses the so-called tau dither tracking method, and the feedback loop 60 for demodulating the data bits uses , Costas loops are used, but these have a digital configuration, and their respective control signals are formed by software processing in the microcomputer 100.

That is, in the feedback loop 50 for despreading demodulation, 51 is a code generator that generates a pseudo-noise code on the receiver side. The data is spread spectrum modulated by a pseudo-noise code with a chip rate of 1.023 MHz and a period of 1 msec) to generate an early code Me and a late code Md with a phase difference.

Early code Me from this code generator 51
and rate code Md are supplied to an early/lag code selector 52, and this code selector 52 is connected to an early/rate switch 5.
By switching every 1 msec by the switching signal from 3, a synthetic pseudo-noise code is obtained from the code selector 52, and this is supplied to the multiplier 36. and,
This synthetic pseudo-noise code and the binarized intermediate frequency signal Sd from the binarization circuit 35 are multiplied by the multiplier 36.

In this case, the clock generator 54, which generates a drive clock for controlling the phase and frequency (chip speed) of the output code of the code generator 51, is composed of a numerically controlled variable frequency oscillator (hereinafter referred to as NCO). be done. This clock generator 54 is supplied with a reference clock from the reference oscillator 33, and the clock generator 54 forms a drive clock for the code generator 51 from this reference clock under the control of the microcomputer 100.

In the code generator 51, the phase and frequency of the early and late pseudo-noise codes are controlled by the clock whose phase and frequency are controlled from the clock generator 54. As a result, the pseudo-noise code output from the code generator 51 is controlled to match the phase and frequency of the pseudo-noise code included in the intermediate frequency signal Sd from the binarization circuit 35, and despreading is thereby performed. Ru.

The Costas loop of the feedback loop 60 for demodulating data bits includes a carrier generator 61 consisting of an NCO and a 90° phase shifter, and first and second multipliers consisting of exclusive OR gates. vessels 62 and 63;
It consists of low-pass filters 64 and 65 consisting of counters, and a microcomputer 100 that forms a control signal to the carrier generator 61. A reference clock from the reference oscillator 33 is supplied to the carrier generator 61, and the carrier generator 61 generates a carrier according to the control of the microcomputer 100 from this reference clock.

The microcomputer 100 executes various functions shown as functional blocks in FIG. 1 using program software. That is, to explain the processing functions of the microcomputer 100 in terms of the functional blocks in FIG. An output corresponding to the phase difference between the carrier wave component and the carrier from the carrier generator 61 is obtained. The loop filter means 102 forms a signal for controlling the carrier generator 61 from the multiplication output from the multiplication means 101, and supplies the signal to the carrier generator 61. The above constitutes a part of the Costas loop 60.

Next, the absolute value detection means 103 and 104 perform absolute value detection on the count value outputs from the low-pass filters 64 and 65, respectively, and add the detected outputs to the addition means 1.
Add with 05. This addition means 105 obtains a signal indicating the correlation level between the pseudo-noise code from the code generator 51 and the pseudo-noise code of the received signal. Here, the reason why the outputs of the low-pass filters 64 and 65 are subjected to absolute value detection instead of square law detection is as follows.

That is, in the conventional analog configuration shown in FIG. 9, the correlation outputs of the low-pass filters 7 and 8 are
If the above correlation is established, the broken lines (a) and (b) in Figure 2A
As shown, the relationship is that of a cosine wave and a sine wave. Therefore, if these are square-detected and added together, a signal of a constant level will be obtained. However, in this example, the outputs of the low-pass filters 64 and 65 are binary signals. The correlation outputs of the low-pass filters 64 and 65 are
When the correlation is established, the solid line (C) in FIG. 2A,
As shown in (d), it becomes a triangular wave shape. For this reason, when the outputs of the low-pass filters 64 and 65 are square-detected and summed as in the conventional method, the summed output does not have a constant output level even though the correlation is established, as shown in FIG. 2B. First, it becomes difficult to determine whether or not there is a correlation.

On the other hand, after absolute value detection as in this example, the added output has a constant output level as shown in FIG. 2C, and it is possible to reliably determine whether or not there is a correlation.

The output of the adding means 105 is switched to the switching means 106 in synchronization with the selector 52 by a switching signal from the early rate switching device 53, and is stored in the early data holding means 107 and the rate data holding means 108. be done. Substantially, the switching means 106 is unnecessary, and the early data memory area and the rate data memory area are selected according to the switching signal from the early/rate switch 53, and these early data and rate data are transferred to each area. Accumulate in. The output of the early data holding means 107 and the output of the rate data holding means 108 are calculated by the subtracting means 10.
9 and is subtracted. The result of the subtraction is then supplied to the loop filter means 110 to form a numerical control signal for controlling the phase of the drive clock of the code generator 51, which is the output of the clock generator 54.

Further, the output of the adding means 105 is supplied to the search signal generating means 111 and also to the synchronizing signal detecting means 112. The search signal generating means 111 is
A search signal for performing a search is generated by sliding the output code of the code generator 51 by one period until a predetermined correlation is obtained. The synchronization detection means 112 monitors the addition output and performs a search, or the loop filter means 11
It is determined whether phase control is to be performed based on the output of 0, and a switching signal is generated to switching means 113 for switching between the output of search signal generating means 111 and the output of loop filter means 110. The output of switching means 113 is supplied to clock generator 54 .

Next, the actual processing flow of the microcomputer 100 will be explained with reference to the flowcharts of FIGS. 3 to 7, in which the reference numerals of each functional means in FIG. 1 are compared. The operations shown in FIGS. 3 to 7 are repeated every 1 msec, which is the chip speed of the pseudo noise code. Therefore, the low-pass filters 64 and 65 having a counter configuration are reset every 1 msec.

First, to explain FIG. 3, I data from the low-pass filter 64 having a counter configuration is taken in (step 201), and its absolute value is determined (step 2).
02). Similarly, a low-pass filter 65 with a counter configuration
The Q data from is taken in (step 203) and its absolute value is determined (step 204).

Next, the absolute value of the I data obtained in step 202 and the absolute value of the Q data obtained in step 204 are added to obtain the addition result A (step 205). and,
With reference to the switching signal from the early rate switch 53,
It is determined whether the current mode is an early mode in which the code generator 51 outputs the early code Me (step 20
6). As a result of the determination, if it is the early mode, the addition result A is written into the early data storage area of the RAM, for example (step 207). Further, if the rate mode is in which the rate code Md is output from the code generator 51, the addition result A is written into the rate data storage area of the RAM, for example (step 208).

Next, the flowchart shown in FIG. 4 will be described. The portion in FIG. 4 corresponds to the operation of the synchronization detection means 112 in FIG. That is, first, it is determined whether the addition result A obtained in step 205 exceeds a predetermined threshold value (step 211). This is to determine whether the pseudo noise code of the received signal and the pseudo noise code from the code generator 51 are correlated with each other regarding the feedback loop 50.

As a result of the determination, if it is determined that there is a correlation, the first timer S is set to, for example, "10" (10 msec) (step 212), and the second timer P is set to "10" (10 msec), for example. 30,000'' (30 seconds) (step 213), and the process moves to a flowchart for forming a control signal for the Costas loop 60 in FIG. 6, which will be described later.

Further, as a result of the determination in step 211, when it is determined that there is no correlation, the first timer S
is decremented by "1" (step 214), and it is determined whether the value of this timer S is "0" (step 215). As a result of the determination, if the timer S is not "0", the process moves to the flowchart of FIG. 6.

[0045] Also, as a result of the determination, the value of timer S is "0".
If not, set the value of the first timer S to "1" (
Step 216), it is determined whether the value of the second timer P is "0" (step 217). If the value of the timer P is "0", the flowchart of the operation of the search signal generation means 111 and the loop filter means 102 during the search shown in FIG. 5 is shown. Further, if the value of the timer P is not "0", the value of the timer P is decreased by "1" (step 218), and the loop filter means 110 of the feedback loop 50 of FIG.
Moving on to the flowchart for the operation.

In this case, once it is detected in the feedback loop 50 that the correlation is established (correlation lock), the first timer S executes the flowchart of FIG. This is to prevent non-correlation from being detected unless it is determined in step 211 that there is no correlation.

Further, once the feedback loop 50 detects correlation lock, the timer P locks the correlation even if non-correlation is detected (determined that no correlation has been obtained continuously for 10 msec). This state is maintained for a time set by the timer P, for example, 30 seconds (in the feedback loop 60, the loop filter 102 controls the output of the carrier generator 61, and in the feedback loop 50, the loop filter 110 controls the output of the clock generator 54). (The phase and frequency control is performed.), and when it is detected that no correlation can be obtained even after 30 seconds have passed, the process moves to the correlation search flowchart of FIG.

That is, once a correlation lock is detected in the feedback loop 50, the correlation is not immediately unlocked even if it is determined in step 211 that the correlation is not locked; Does not move to correlation search. For this reason, in reality, the correlation may be unlocked for an instant for some reason, such as when the correlation is not broken, such as when an obstacle such as an airplane temporarily enters the space between the satellite and the receiving device. Even if detected, the process is prevented from proceeding to a correlation search operation, which will be described later, which takes a relatively long time. This ensures that even if there is a momentary reception failure, the feedback loop 5
0 is hardly affected by this, and stable reception is possible.

Next, a flowchart of the portion corresponding to the search signal generating means 110 and the loop filter means 102 at the time of search in FIG. 5 will be explained.

The search in this example is performed as follows. That is, the received signal exists within the range of 1.023 MHz±15 kHz when viewed in terms of its intermediate frequency signal Sif. Therefore, if you search within this range, you can find a correlation. However, the bandwidth of the loop filter means 102 is generally within a frequency range smaller than this search range, in this example only ±350 Hz, and the correlation search can only be performed within this loop filter bandwidth range.

Therefore, in this example, the carrier generator 6
At the center frequency fc where an output of 1 is given, the early and rate codes from the code generator 51 are slid by one cycle. If the correlation cannot be obtained by the one cycle of slide control, the oscillation center frequency fc of the carrier generator 61 is shifted by 700 Hz, and the slide control of the code generator 51 is performed again. This is performed sequentially within the range of ±15 kHz. Note that the frequency fc, which differs by 700 Hz, is changed alternately in the plus direction and in the minus direction.

That is, in FIG. 5, first, since no correlation is established in the feedback loop 50, the correlation unlocked state is initialized (step 221). next,
Determine whether sliding (phase control) for one period of the early and rate codes from the code generator 51 has been completed (
Step 222). For example, it takes a predetermined time, for example 4 seconds in this example, to output one period of the pseudo-noise code from the code generator 51 and perform a correlation search, so it is difficult to determine whether one period of sliding has been completed or not. The determination is made by monitoring this 4 second timer.

As a result of the determination in step 222, if 4 seconds have elapsed, this means that the correlation could not be found even though the output of the code generator 51 was searched for one period.・Loop carrier generator (NC
O) A numerical control signal is generated to change the oscillation center frequency fc of 61 by a predetermined step width frequency Δf=700 Hz (step 223). Then, the numerical control signal is supplied to the carrier generator 61 (step 224
). Thereafter, a numerical control signal is again generated to slide the output of the code generator 51 by one period, and the control signal is supplied to the clock generator 54 (step 225).

As a result of the determination in step 222, if 4 seconds have not elapsed, this means that one cycle of sliding of the output of the code generator 51 has not yet been completed, so the carrier generator of the Costas loop The oscillation center frequency fc of 61 remains unchanged, and the process jumps to step 225, where a numerical control signal for sliding the output of the code generator 51 by one cycle is continued to be supplied to the clock generator 54. After this step 225, the process returns to step 201 in FIG. 3 (see FIG. 7).

As a result of the above correlation search, a correlation lock is always detected somewhere.

When it is detected in step 211 of FIG. 4 that a correlation has been established, the process moves to the flowchart of the loop filter means 102 of FIG. 6 for finely controlling the carrier generator 61, as described above. . The operation of this flowchart, that is, the control of the carrier generator 61 in the correlation lock state is performed as follows.

That is, first, the carrier generator 61 is set to the correlated oscillation center frequency fc. Then, referring to the output of the multiplication means 101, which is an error signal that is a reference signal for controlling the carrier generator 61, the multiplication output is positive (indicating that the oscillation frequency is shifted to a higher side).
In this case, the oscillation frequency of the carrier generator 61 is set to a predetermined frequency width, for example, 30H, with respect to the center frequency fc at that time.
Lower by z. Conversely, when the multiplication output is negative (indicating that the oscillation frequency is shifted to a lower side), the oscillation frequency of the carrier generator 61 is lowered by a predetermined frequency width, for example, 30 Hz, with respect to the center frequency fc at that time. This frequency shift is performed every time the operation of this flowchart is performed, that is, every 1 msec. Then, this frequency shift is
For example, it is performed for 50 m seconds, and the number of positive and negative multiplication outputs during that 50 m seconds are counted and compared. If this is done with one counter, it is sufficient to count up when the multiplication output is positive and to count down when the multiplication output is negative.

If the oscillation center frequency fc of the carrier generator 61 at that time is locked to the carrier of the received signal, the count value for 50 m seconds will be "0", and on the other hand, the oscillation center frequency fc of the carrier generator 61 is locked to the carrier of the received signal. When the frequency fc is higher than the lock frequency, the count value is positive, and when the oscillation center frequency fc is lower than the lock frequency, the count value is negative. Therefore, when the count value for 50 m seconds is positive, the oscillation center frequency fc of the carrier generator 61 is shifted lower by a predetermined step width, for example, 1 Hz, and the same operation is performed at the shifted oscillation center frequency fc. When the count value for 50 m seconds is negative, the oscillation center frequency fc is shifted higher by a predetermined step width, for example, 1 Hz, and the same operation is performed at the shifted oscillation center frequency fc. With the above control operation, the carrier generator 6
Fine tracking control is performed for the carrier of the received signal having the oscillation center frequency fc of 1.

That is, in FIG. 6, the count value outputs from the low-pass filters 64 and 65 are multiplied together, and it is determined whether or not the multiplication output is a negative value (step 231). As a result of the determination, if it is determined to be positive, the count value COS for the Costas loop
CNT is counted up by "1" (step 232
), a numerical control signal is formed to lower the oscillation frequency of the carrier generator 61 by a predetermined frequency width, for example, 30 Hz, with respect to the center frequency fc at that time (step 233), and this is supplied to the carrier generator 61 (step 234). ). Further, if the result of the determination in step 231 is negative, the count value COSCNT is decremented by "1" (step 235), and the oscillation frequency of the carrier generator 61 is set to the center frequency fc at that time. In contrast, a numerical control signal is generated to lower the frequency by the predetermined frequency width, that is, 30 Hz (step 236), and is supplied to the carrier generator 61 (step 234).

Next, the value of the third timer C (initial value is 50) is decreased by "1" (step 237). and,
It is determined whether the value of timer C is "0" (step 238). As a result of this determination, the value of timer C is "0"
If not, that is, if 50 milliseconds have not passed since the oscillation center frequency fc was set or changed, the process moves to the next flowchart of FIG.

Further, as a result of the determination in step 238, when it is determined that the value of timer C is "0", that is, 50 seconds have passed since the oscillation center frequency fc was set or changed.
When m seconds have passed, the count value COSCNT becomes "0".
” (step 239). If the count value COSCNT is "0", the oscillation center frequency fc is left unchanged and the process jumps to step 244, where the timer C
Set the value to the initial value = 50.

On the other hand, if the count value COSCNT is not "0", it is determined whether or not the count value COSCNT is positive (step 240). If the result of the determination is positive, a control signal is generated to lower the oscillation center frequency fc of the carrier generator 61 by 1 Hz (step 241), and this is output to the carrier generator 61 (step 243). Further, if it is determined that it is negative as a result of the determination in step 240, a control signal is generated to increase the oscillation center frequency fc of the carrier generator 61 by 1 Hz (
Step 242), and outputs this to the carrier generator 61 (Step 243).

Thereafter, the process proceeds to step 244, where the initial value of timer C is set, and then, the process proceeds to step 245, where the value of the count value COSCNT is set to "0" for counting for the next 50 msec. Then, the process moves to the next flowchart shown in FIG.

The flowchart in FIG. 7 shows that the subtraction means 109
and the operation of the loop filter means 110. In this example, the code generator 51 is controlled as follows.

In other words, the addition means 105 which is the correlation output
Difference DI between early data EA and rate data LA from
=EA-LA, and when the value of the difference DI is positive and exceeds a predetermined value, that is, when the Early code Me has a stronger correlation, the output phase of the code generator 51 is advanced. When the value of the difference DI is negative and exceeds a predetermined value, that is, when the rate code Md has a stronger correlation, the output of the code generator 51 is controlled to be delayed. Then, the value of the difference DI is “
When the value is within a predetermined range around 0, the state is maintained as it is.

In the practical operation of FIG. 7, in this example, the count value PNCNT of the counter related to the control of the code generator 51 is considered as the difference DI. Then, the predetermined values are set to count values +PN and -PN, and FIG.
As shown in the figure, the count value PNCNT is set so that it always becomes +PN when it becomes larger than the count value +PN, and always becomes -PN when it becomes smaller than the count value -PN.

In addition to the above phase control, the code generator 51
The chip speed (frequency) of the output code is checked based on the output frequency of the carrier generator 61 of the Costas loop 60. This utilizes the fact that a predetermined relationship is established between the output frequency of the clock generator 54, which is a drive circuit for the code generator 51, and the frequency of the carrier generator 61. That is, if the feedback loop 50 is locked, the frequency at which the carrier generator 61 of the Costas loop 60 should oscillate can be calculated. Conversely, if the Costas loop 60 is locked, the set frequency of the code generator 51 can be determined by the resolution of the carrier generator 61 of the Costas loop 60. In other words, the frequency ratio between the two is 1:1500, so approximately 150
This means that the frequency of the feedback loop 50 can be controlled with zero times precision.

That is, in the flowchart of FIG. 7, first, the early data E which is the output of the adding means 105 is
Find the difference between A and rate data LA, and calculate the difference EA-LA
It is determined whether or not is negative (step 251). As a result of the determination, if the difference is positive, the correlation level for the early code Me is greater, so the count value PNCNT is incremented by "1" (step 252). Then, the count value PNCNT is the predetermined value +P
It is determined whether it is equal to N (step 253). Then, three types of control output values, X, Y, and Z, to be outputted to the clock generator 54 are prepared according to the result of the determination.

[0069] As a result of the determination in step 253,
When the count value PNCNT=+PN, the control output value X is the control value Nowf that keeps the output phase of the code generator 51 unchanged, and the control output values Y and Z advance the output phase of the code generator 51. The control value of the clock generator 54 is set to Fast (step 254).

Further, as a result of the determination in step 253, if the count value PNCNT ≠PN, -PN<
Since PNCNT <+PN, the control output value X is the control value Slow of the clock generator 54 that delays the output phase of the code generator 51, and the control output value Y is the control value Nowf that leaves the output phase unchanged. , control output value Z
is the control value Fast of the clock generator 54 that advances the output phase of the code generator 51 (step 25).
5).

Further, as a result of the determination in step 251, when it is determined that the difference DI is negative, the correlation level at the rate code Md is greater, so the count value PNC
NT is counted down by "1" (step 25)
6). Then, the count value PNCNT becomes the predetermined value -
It is determined whether it is equal to PN (step 257). As a result of the determination in step 257, the count value PNC
When NT = -PN, the control output values X, Y are
The control value Slow of the clock generator 54 is set to delay the output phase of the code generator 51, and the control output value Z is as follows.
The control value Nowf is set to keep the output phase of the code generator 51 as it is (step 258). Furthermore, as a result of the determination in step 257, the count value PNCNT ≠-P
When it is N, since -PN<PNCNT<+PN, the process proceeds to step 255.

Next, the output frequency of the code generator 51 of the loop 50 is calculated using the output frequency of the carrier generator 61 of the Costas loop 60, and the control value of the clock generator 54 is set for the output frequency value. (step 258). Then, the control value is compared with the current control value of the clock generator 54 for the code generator 51,
Determine whether the difference is within a predetermined range (step 2
60). As a result of the determination, if the difference is within a predetermined range, the control value for the clock generator 54 is changed to the control value Y.
(Step 261). In other words, -PN<PNCN
When T<+PN, the state is maintained and P
When NCNT = +PN, the control value Fast is set to advance the output phase of the code generator 51, and when the count value PNCNT = -PN, the control value Slo is set to delay the output phase of the code generator 51.
Let it be w.

Furthermore, if the result of the determination in step 260 is that the difference is outside the range, it is determined whether the frequency has shifted to a higher side depending on whether the difference is positive or negative (
step 262). As a result of the determination, if the difference is higher, the control value for the clock generator 54 is set to the control value X (step 263). That is, −PN<P
When NCNT <+PN, also PNCNT =
-PN, the control value Slow is set to delay the output phase of the code generator 51. Also, PNC
When NT = +PN, the output phase of the code generator 51 is left unchanged.

Further, as a result of the determination in step 262, if it is determined that the frequency has shifted to the lower side, the control value for the clock generator 54 is set to the control value Z (step 264). In other words, -PN<PNCNT
When <+PN and when PNCNT=+PN, the control value Fast is set to advance the output phase of the code generator 51. Also, PNCNT = -PN
When this is the case, the output phase of the code generator 51 is left unchanged.

[0075] The flowcharts in FIGS. 3 to 7 above are 1 m
It is repeated every second.

The present invention is applicable not only to position measuring systems such as GPS, but also to all spread spectrum signal receiving devices.

Further, the carrier wave modulation method is not limited to the quadrature phase modulation as in the above example, and it goes without saying that various modulation methods can be used. Furthermore, it is not necessary to superimpose data such as the orbit parameter data in this example on the carrier wave, and only the carrier wave may be transmitted.

[0078]

[Effects of the Invention] As explained above, according to the present invention, a receiving device for a spread spectrum modulated signal can be configured by high digital integration and software, resulting in lower cost, smaller size, and lower power consumption. , high quality can be achieved.

Further, according to the present invention, the feedback loop for correlating the pseudo noise code of the received signal with the output of the pseudo noise code generator of the receiving device binarizes the intermediate frequency signal and converts it into pseudo noise. Since the output of the code generator is multiplied, there is no need for a conventional balanced modulator, and therefore no circuit technology is required to maintain the balance of the balanced modulator.

Furthermore, since the configuration is digital, an NCO can be used as the variable frequency oscillator, and a conventional VC can be used.
There is an advantage that there is no need to use O, and there is no need for circuit technology to maintain the linearity of the VCO.

Furthermore, since it has a digital configuration as described above, it does not require the analog circuit technology described above.
Stable reception is possible, and when applied to a multi-channel receiver, there is no interference or variation between channels. Furthermore, by implementing software, various parameters determined by the loop filter can be easily changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a spread spectrum signal receiving device according to the present invention.

FIG. 2 is a diagram for explaining level output according to the correlation between a pseudo-noise code in a received signal and a pseudo-noise code on the receiving device side.

FIG. 3 is a flowchart of a part of the operation of the microcomputer 100 in the embodiment of FIG. 1;

FIG. 4 is a flowchart of a part of the operation of the microcomputer 100 in the embodiment of FIG. 1;

5 is a flowchart of a part of the operation of the microcomputer 100 of the embodiment of FIG. 1. FIG.

6 is a flowchart of a part of the operation of the microcomputer 100 of the embodiment of FIG. 1. FIG.

7 is a flowchart of a part of the operation of the microcomputer 100 of the embodiment of FIG. 1. FIG.

FIG. 8 is a diagram for explaining the operating principle of the flowchart in FIG. 7;

FIG. 9 is a block diagram of an example of a conventional spread spectrum signal receiving device.

[Explanation of symbols]

32 RF processing circuit 33 Reference oscillator 35 Binarization circuit 36 Signal multiplication circuit 50 Feedback loop 51 for despreading Code generator 54 that generates a pseudo-noise code on the receiving device side Clock generation for driving the code generator 51 (NCO) 60 Costas loop 61 Carrier generator (NCO) 62, 63 Signal multiplier circuit 64, 65 Low-pass filter 100 Microcomputer

Claims (1)

[Claims] 1. A high frequency processing circuit that converts a spread spectrum signal whose carrier wave is spread spectrum modulated by a pseudo noise code into an intermediate frequency signal, and a binarization circuit that binarizes the intermediate frequency signal from the high frequency processing circuit. , a pseudo-noise code generator, a code drive device for controlling the phase and chip speed of the output pseudo-noise code of the pseudo-noise code generator, and a binary signal from the binarization circuit and the pseudo-noise code. The first one performs multiplication with the output pseudo-noise code of the noise code generator.
a multiplier circuit, and a numerically controlled variable frequency for outputting first and second carrier signals that follow the low frequency converted carrier wave included in the intermediate frequency signal and have mutually different phases by π/2. an oscillator, an output signal of the first multiplier circuit, and the first and second multipliers having phases different from each other by π/2.
first and second low-pass filters comprising second and third multiplier circuits that respectively multiply the carrier signal of the second and third multiplier circuits; The count result outputs which are the outputs of the second and third low-pass filters are received, and from this count result output, the frequency and phase of the output carrier signal of the numerically controlled variable frequency oscillator are determined to be the carrier wave component included in the intermediate frequency signal. A function for generating a control signal for controlling the numerically controlled variable frequency oscillator so as to follow the signal, and a function for controlling the phase of the output pseudo-noise code from the pseudo-noise code generator to match the spread spectrum signal based on the counting result output. A control device comprising a microcomputer having a function of generating a control signal for controlling the code driving device so as to match the phase of the included pseudo-noise code.