KR100230005B1 - Thin film actuated mirror arrays having a stress-adjustible membrane therein and manufacturing method thereof - Google Patents

Abstract

There is disclosed a thin film type optical path adjusting device capable of easily controlling stress in a membrane after forming a membrane at a low temperature and then heat-treating the membrane, and preventing the membrane from being etched. The apparatus includes an actuator having a membrane, a lower electrode, a deformation portion, an upper electrode, and a via contact composed of an active matrix with transistors embedded therein and a silicon carbide stacked on top of the active matrix. Accordingly, the membrane is formed at a low temperature of about 200 to 300 DEG C, and heat treatment is performed at 600 DEG C or less to prevent damage to the active matrix, and stress in the membrane can be easily controlled. Also, it is possible to form a membrane having excellent resistance to etching using hydrogen fluoride vapor as a main component.

Description

Thin film type optical path control device capable of controlling stress of a membrane and manufacturing method thereof

The present invention relates to AMA (Actuated Mirror Arrays) which is a thin film type optical path adjusting device having a membrane capable of easily controlling stress and a method of manufacturing the same. More particularly, the present invention relates to an AMA The present invention relates to a thin film type optical path adjusting device having a membrane that can easily control stress by annealing the thin film and has excellent resistance to etching, and a manufacturing method thereof.

2. Description of the Related Art Generally, a spatial light modulator, which is an apparatus for projecting optical energy onto a screen, can be variously applied to optical communication, image processing, and information display devices. These devices are classified into a direct view type image display device and a projection type image display device according to a method of projecting a light beam incident from a light source on a screen. Examples of the direct view type image display device include a CRT (Cathode Ray Tube), and the projection type image display device includes a liquid crystal display (LCD), a DMD (Deformable Mirror Device), and AMA. The CRT device has a disadvantage in that it is difficult to enlarge the screen, although the image quality is excellent. That is, as the size of the screen increases, the weight and volume of the apparatus increase, resulting in an increase in manufacturing cost. Accordingly, a liquid crystal display (LCD) capable of forming a thin optical structure and having a light weight has been developed. However, the efficiency of the liquid crystal display device is low enough to have a light efficiency of 1 to 2% due to the polarization of the light beam, the response speed of the liquid crystal material therein is low, and the device is likely to be overheated. Accordingly, in order to solve the above problems, a device such as a DMD or AMA has been developed. At present, the DMD device has a light efficiency of about 5%, whereas the AMA has a light efficiency of 10% or more. In addition, the AMA improves the contrast to form a brighter and clearer image, and is not affected by the polarity of the incident light beam, and does not affect the polarity of the light beam.

AMA, which is an optical path control device, is divided into a bulk type and a thin film type. The bulk optical path adjusting device is disclosed in U.S. Patent No. 5,085,497 issued to Gregory Um et al. A bulk-type optical path adjusting device comprises a ceramic wafer cut into a thin layer of a multilayer ceramic and forming a metal electrode therein, mounted on an active matrix with a built-in transistor, processed by a sawing method, And a mirror is installed on the surface. However, the bulk optical path adjusting apparatus requires very high precision in design and manufacture, and has a problem that the response speed of the deformed portion is slow.

Accordingly, a thin film type optical path adjusting device that can be manufactured using a semiconductor process has been developed. The thin-film type optical path adjusting device is disclosed in Japanese Patent Application No. 96-25325 filed on June 28, 1996 by the present applicant (entitled "Optical path adjusting device with uniform stress distribution and method of manufacturing the same").

FIG. 1 is a cross-sectional view of the thin-film type optical path adjusting device described in the above-mentioned prior application, and FIGS. 2A to 2C are a manufacturing process diagram of the device shown in FIG.

1, the device includes an active matrix 10 in which M × N (M, N is an integer) transistors (not shown) are embedded and a drain 18 is formed on one surface of the active matrix 10, And an actuator 19 formed on an upper portion of the housing 10. A protective layer 12 is formed on the active matrix 10 and an etch stop layer 14 is formed on the protective layer 12. The actuator 19 is formed such that one side of the actuator 19 is in contact with a portion where the drain 18 is formed under the etching prevention layer 14 and the other side of the actuator 19 is parallel to the etching prevention layer 14 with an air gap 16 therebetween A laminated membrane 20, a lower electrode 22 stacked on top of the membrane 20, a deformation section 24 stacked on top of the lower electrode 22, An upper electrode 26 and a via contact 28 formed vertically from the other side of the deformation portion 24 to the drain 18. A stripe 30 is formed at the center of the upper electrode 26.

Hereinafter, a method of manufacturing the thin film type optical path adjusting apparatus will be described with reference to FIGS. 2A to 2C. In Figs. 2A to 2C, the same reference numerals are used for the same members as those in Fig.

Referring to FIG. 2A, a protective layer 12 is stacked on an active matrix 10 in which M × N transistors (not shown) are built in and a drain 18 is formed on one surface. The passivation layer 12 is formed to have a thickness of about 1 mu m by using a phosphorus-silicate glass (PSG) by spin coating or chemical vapor deposition (CVD) . An etch stop layer 14 is deposited on the protective layer 12. The etch stop layer 14 is formed to have a thickness of about 2000 Å by using a low pressure chemical vapor deposition (LPCVD) method. After the etch stop layer 14 is formed, a sacrificial layer 15 composed of phosphorus silicate glass (PSG) having a high phosphorus (P) concentration is deposited on the etch stop layer 14. The sacrificial layer 15 is formed to have a thickness of about 1 mu m using Atmospheric Pressure Chemical Vapor Deposition (APCVD). At this time, since the sacrifice layer 15 covers the surface of the active matrix 10 in which the transistors are embedded, the flatness of the surface is very poor. Therefore, the surface of the sacrifice layer 15 is planarized by using a spin-on-glass (SOG) method or a CMP (Chemical Mechanical Polishing) process. Preferably, the surface of the sacrificial layer 15 is planarized using a CMP process and then subjected to a scrubbing treatment. Subsequently, a portion where the drain 18 is formed in the lower part of the sacrificial layer 15 is etched to form a place where the support part is formed. Accordingly, a portion of the etch stopper layer 14 below the drain 18 is exposed.

A membrane 20 made of silicon nitride (Si _x N _y ) is deposited on the exposed etch stop layer 14 and the sacrificial layer 15. The membrane 20 is formed to have a thickness of about 0.1 to 1.0 占 퐉 at a temperature of about 700 占 폚 to 800 占 폚 by a low pressure chemical vapor deposition (LPCVD) method. At this time, the membrane 20 deposits a multi-layer film having different compositions of silicon (Si) and nitrogen (N) to control the stress inside the membrane 20.

Referring to FIG. 2B, a lower electrode 22 made of platinum (Pt) or platinum-tantalum (Pt-Ta) is formed on the membrane 20. The lower electrode 22 is formed to have a thickness of 500 to 2000 ANGSTROM using a sputtering method. The deformed portion 24 is formed by using a piezoelectric material such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) Laminated so as to have a thickness of about 1 to 1.0 mu m. The deformed portion 24 is formed using a sol-gel method, and then the deformed portion 24 is phase-transformed using a rapid thermal annealing (RTA) method.

Referring to FIG. 2C, an upper electrode 26 is stacked on the upper portion of the deformation portion 24. As shown in FIG. The upper electrode 26 is formed to have a thickness of about 500 to 2000 ANGSTROM using aluminum (Al) or platinum by a sputtering method. Subsequently, the upper electrode 26, the deformed portion 24, the lower electrode 22, and the membrane 20 are sequentially patterned in a pixel shape. At this time, the upper electrode 26 is patterned so that a stripe 30 is formed at the center of the upper electrode 26. In addition, a via contact 28 is formed to electrically connect the drain 18 and the lower electrode 22. The via contact 28 is formed by successively etching the deformation portion 24, the lower electrode 22, the membrane 20, the etching prevention layer 14 and the protection layer 12 and then depositing tungsten (W) or titanium (Ti ) Is formed using a lift-off method. Then, the sacrificial layer 15 is etched by using hydrogen fluoride (HF) vapor, and then the device is cleaned and dried to complete.

However, in the thin-film type optical path adjusting device described in the above-mentioned prior application, since the membrane made of silicon nitride is formed at a high temperature of 700 to 800 ° C, there is a problem that the active matrix having the MOS transistor has thermal damage such as spiking there was. In addition, since the membrane is formed of a multi-layered film having a different composition of silicon and nitrogen in order to control the stress in the membrane, the process becomes complicated and the reproducibility of the process is lowered, and the influence of the etching process subsequent to the membrane composed of silicon nitride There is a problem that is easy to receive and etch.

Accordingly, it is an object of the present invention to provide a thin film type optical path controller having a membrane capable of forming a membrane at a low temperature and thermally treating the membrane to easily control stress, and a method of manufacturing the same. It is another object of the present invention to provide a thin film type optical path adjusting apparatus having a membrane excellent in resistance to etching and a method of manufacturing the same.

1 is a cross-sectional view of a thin-film type optical path adjusting apparatus previously filed by the present applicant.

2A to 2C are a manufacturing process diagram of the apparatus shown in Fig.

3 is a plan view of the thin-film type optical path adjusting apparatus according to the present invention.

FIG. 4 is a cross-sectional view of the device shown in FIG. 3 taken along line AA '.

5A to 5D are process diagrams of the apparatus shown in Fig.

Description of the Related Art

41: active matrix 43: actuator

49: drain 51: protective layer

53: etching preventing layer 55: air gap

56: sacrificial layer 57: membrane

61: lower electrode 63:

65: upper electrode 67: stripe

68: via hole 69: via contact

In order to achieve the above objects,

An active matrix in which M × N (M, N is an integer) transistors are built in, and a drain is formed in one side of the active matrix; And

A membrane made of silicon carbide (SiC), which is formed on the active matrix, i) one side is in contact with the upper side of the active matrix and the other side is laminated in parallel with the active matrix via an air gap, ii) A lower electrode stacked on top of the lower electrode, iii) a deformation portion laminated on the upper electrode, iv) an upper electrode stacked on one side of the deformation portion, and v) And an actuator having a via hole formed vertically through the membrane to the upper portion of the drain.

The active matrix further includes a protective layer stacked on the active matrix and an etch stop layer stacked on the protective layer. The actuator further includes a via contact formed in the via hole from the lower electrode to the drain to electrically connect the lower electrode and the drain.

Preferably, the membrane composed of silicon carbide has a thickness of 0.1 to 1.0 탆.

According to another aspect of the present invention,

Forming a drain on one side of an active matrix having M x N (M, N is an integer) transistors; And

I) forming a membrane composed of silicon carbide on top of the active matrix, ii) forming a lower electrode on top of the membrane, iii) forming a deformation on top of the lower electrode, iv) (V) forming a via hole vertically from an upper portion of the other side of the deformation portion to an upper portion of the drain; and (vi) electrically connecting the lower electrode and the drain to the via hole Forming an active matrix on the active matrix substrate, and forming a via contact on the active matrix substrate.

Forming a protective layer on top of the actuator and the drain, forming an etch stop layer on the protective layer, forming a sacrificial layer on the etch stop layer, A portion of the etching stopper layer is exposed to expose a portion of the etching stopper layer.

Preferably, the membrane made of silicon carbide is formed at a temperature of 200 to 300 DEG C by PECVD (Plasma Enhanced Chemical Vapor Deposition) method and is formed by heat treatment at a temperature of 600 DEG C or less.

Preferably, the membrane composed of silicon carbide is formed of silicon carbide made from liquid C ₆ H ₁₈ O ₁₂ , or formed of silicon carbide made by mixing SiH ₄ and CH ₄ .

The forming of the upper electrode may further include patterning the upper electrode to form a stripe at a central portion of the upper electrode. The forming of the via contact may include forming a via contact (Pt) or a platinum-tantalum (Pt- Ta.

In the thin film type optical path adjusting apparatus according to the present invention, an image signal generated from a transistor embedded in an active matrix is applied to a lower electrode which is a signal electrode through a drain and a via contact. A bias voltage is applied to the upper electrode, which is a common electrode, to generate an electric field between the upper electrode and the lower electrode. The deformation part which is laminated between the upper electrode and the lower electrode causes deformation due to this electric field. The deformed portion contracts in the direction perpendicular to the electric field, and the actuator including the deformed portion is bent in the direction opposite to the direction in which the membrane is formed. Therefore, the upper electrode on the upper part of the actuator also tilts in the same direction. A light beam incident from a light source is reflected by an upper electrode inclined at a predetermined angle, and then projected on a screen to form an image. Therefore, in the thin-film-type optical path adjusting device and the manufacturing method thereof according to the present invention, damage to the active matrix can be prevented by forming the membrane at a low temperature by using silicon carbide, and stress in the membrane can be easily controlled by heat- . In addition, the membrane composed of silicon carbide has excellent resistance to etching using hydrogen fluoride (HF) vapor as a main component. Thus, it is possible to prevent the membrane from being etched from a subsequent etching process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a plan view of the thin film type optical path adjusting apparatus according to the present invention, and FIG. 4 is a sectional view taken along line AA 'of the apparatus shown in FIG. 3 and 4, the thin film type optical path adjusting apparatus according to the present invention includes an active matrix 41 having a drain 49 formed on one side thereof and an actuator 43 formed on the active matrix 41.

The active matrix 41 includes a protective layer 51 stacked on the active matrix 41 and the drain 49 and an etching prevention layer 53 stacked on the protective layer 51. M × N MOS transistors (not shown) are built in the active matrix 41.

The actuator 43 includes a membrane (not shown) stacked in parallel with the etching prevention layer 53 via the air gap 55, one side of which is in contact with a portion where the drain 49 is formed under the etching prevention layer 53 A lower electrode 61 laminated on the upper portion of the membrane 57, a deformation portion 63 laminated on the upper portion of the lower electrode 61, an upper electrode 65 stacked on one side of the deformation portion 63, A via hole 68 formed from the other side of the deformation part 63 to the drain 49 through the lower electrode 61, the membrane 57, the etching prevention layer 53 and the protection layer 51, And a via contact 69 formed to electrically connect the lower electrode 61 and the drain 49 to each other.

Referring to FIG. 3, one side of the membrane 57 has a rectangular concave portion at its central portion, and the concave portion is formed into a shape that widens stepwise toward both edges. The other side of the membrane 57 has a rectangular protruding portion corresponding to the concave portion and narrowing stepwise toward the center portion. Therefore, the concave portion of the membrane of the actuator adjacent to the concave portion of the membrane 57 is fitted, and the rectangular protrusion is fitted in the concave portion of the adjacent membrane.

Hereinafter, a manufacturing method of the thin film type optical path adjusting apparatus will be described in detail with reference to the drawings.

5A to 5D are process diagrams of the apparatus shown in Fig. In Figs. 5A to 5D, the same reference numerals are used for the same members as those in Fig.

5A, a protection layer 51 made of phosphorus silicate glass (PSG) is formed on an active matrix 41 having M × N transistors (not shown) and a drain 49 formed on one side Laminated. The protective layer 51 is formed to have a thickness of about 1.0 to 2.0 占 퐉 by using a chemical vapor deposition (CVD) method. The protective layer 51 protects the active matrix 41 from subsequent processes.

An etch stop layer 53 made of nitride is stacked on the protective layer 51. The etch stop layer 53 is formed to have a thickness of about 2000 Å by using a low pressure chemical vapor deposition (LPCVD) method. The etching prevention layer 53 prevents the protective layer 51 and the active matrix 41 and the like from being etched during the subsequent etching process. A sacrificial layer 56 is stacked on the etching preventing layer 53. The sacrificial layer 56 is formed to have a thickness of about 1.0 to 3.0 mu m by using atmospheric pressure chemical vapor deposition (APCVD) method using phosphorous silicate glass (PSG) having a high phosphorus (P) concentration. In this case, since the sacrifice layer 56 covers the upper portion of the active matrix 41 in which the transistors are embedded, the flatness of the surface is very poor. Therefore, the surface of the sacrifice layer 56 is planarized by using a spin-on-glass (SOG) method or a CMP method. Subsequently, a part of the sacrificial layer 56 under the drain 49 is etched to expose a part of the etch stop layer 53. [

Referring to FIG. 5B, a membrane 57 is stacked on the top of the exposed etch stop layer 53 and the sacrificial layer 56 to a thickness of about 0.1 to 1.0 .mu.m. The membrane 57 is formed at a temperature of 200 to 300 DEG C using PECVD (Plasma Enhanced CVD). At this time, the silicon carbide is produced by depositing silicon (Si) and carbon (C) generated from liquid C ₆ H ₁₈ Si ₂ . Alternatively, the silicon carbide can be produced by depositing Si and C generated from a mixture of SiH ₄ and CH ₄ . Subsequently, the membrane 57 composed of silicon carbide is heat-treated at a temperature of 600 ° C or less to control the stress in the membrane 57. Generally, when the membrane is made of nitride, a process of laminating a multi-layered film in which the composition of silicon and nitrogen is changed in order to form a membrane at a high temperature of 700 to 800 ° C and to control stress in the membrane is required. However, when the formation temperature of the membrane is 700 ° C or more, the active matrix may be damaged due to high temperature. In the process of laminating the multilayered film in which the composition of silicon and nitrogen is changed, the difficulty is very high and the reproducibility of the process is low. In the present invention, the above problems are solved by forming the membrane 57 by PECVD using silicon carbide and then heat-treating it. That is, it is possible to prevent the active matrix 41 from being damaged by depositing silicon carbide at a temperature of 200 to 300 ° C. and then performing a heat treatment at a temperature of 600 ° C. or less. In order to control the stress in the membrane, It is not necessary to deposit a multi-layer film of Furthermore, the membrane 57 made of silicon carbide has an advantage that it is very resistant to etching with hydrogen fluoride vapor as a main component, and thus is not etched due to a subsequent etching process.

A lower electrode 61 made of a metal such as platinum or tantalum is stacked on the membrane 57. The lower electrode 61 is formed to have a thickness of about 500 to 2000 ANGSTROM using a sputtering method. An image signal generated from the transistor built in the active matrix 41 is applied to the lower electrode 61 which is a signal electrode through the drain 49 and the via contact 69. Then, the lower electrode 61 is etched and patterned to separate each pixel.

Referring to FIG. 5C, a deformed portion 63 composed of PZT or PLZT is formed on the lower electrode 61. The deformed portion 63 is formed to have a thickness of about 0.1 to 1.0 탆, preferably about 0.4 탆, by a sol-gel method, and is then thermally treated by a rapid thermal annealing (RTA) . The deformed portion 63 is deformed by an electric field generated between the upper electrode 65 and the lower electrode 61. The upper electrode 67 is stacked on one side of the deformation portion 63. The upper electrode 67 is formed to have a thickness of about 500 to 2000 ANGSTROM using a sputtering method, such as aluminum, platinum or the like, which is excellent in electrical conductivity and reflectivity. A bias voltage is applied to the upper electrode 57, which is a common electrode, so that an electric field is generated between the lower electrode 61 and the upper electrode 57. The upper electrode 57 also functions as a mirror for reflecting the light flux incident from the light source. Subsequently, the upper electrode 65 is patterned to form a stripe 67 at the center. The stripe 67 operates the upper electrode 65 uniformly to prevent irregular reflection of the incident light beam.

5D, after the upper electrode 65 is patterned into a predetermined shape, the deformed portion 63, the lower electrode 61, and the membrane (not shown) are sequentially removed from the upper portion of the deformation portion 63 to the upper portion of the drain 49 The etch stop layer 53 and the passivation layer 51 are sequentially etched to form a via hole 68 from the deformation portion 63 to the drain 49. [ Next, a via contact 69 is formed by sputtering a metal such as tungsten, platinum, or titanium to electrically connect the drain 49 and the lower electrode 61. Accordingly, the via contact 69 is vertically formed in the via hole 68 from the lower electrode 61 to the upper portion of the drain 49. An image signal generated from the transistor incorporated in the active matrix 41 is applied to the lower electrode 61 through the drain 49 and the via contact 69. [ Subsequently, the deformed portion 63, the lower electrode 61, and the membrane 57 are sequentially patterned, and then the sacrificial layer 56 is etched with hydrogen fluoride vapor, washed and dried to complete the AMA device.

An image signal generated from the MOS transistor built in the active matrix 41 is applied to the lower electrode 61 which is the signal electrode through the drain 49 and the via contact 69. In this case, A bias voltage is applied to the upper electrode 65, which is a common electrode, to generate an electric field between the upper electrode 65 and the lower electrode 61. The deformed portion 63 laminated between the upper electrode 65 and the lower electrode 61 is deformed by this electric field. The deformed portion 63 contracts in the direction perpendicular to the electric field and the actuator 43 including the deformed portion 63 is bent in the direction opposite to the direction in which the membrane 57 is formed. Therefore, the upper electrode 65 on the upper portion of the actuator 43 also tilts in the same direction. The light beam incident from the light source is reflected by the upper electrode 65 inclined at a predetermined angle, and then projected on the screen to form an image.

In the thin film type optical path adjusting device and the method of manufacturing the same according to the present invention, damage to the active matrix can be prevented by forming the membrane at a low temperature by using silicon carbide, and the stress formed inside the film formed at a low temperature can be easily Can be adjusted. Also, the membrane composed of silicon carbide has excellent resistance to etching based on hydrogen fluoride vapor. Thus, it is possible to prevent the membrane from being etched from a subsequent etching process.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. There will be.

Claims (12)

An active matrix 41 in which M × N (M, N is an integer) transistors are built in, and a drain 49 is formed on one side of the active matrix 41; And The active matrix 41 is formed on the upper part of the active matrix 41. The active matrix 41 has one side contacted with the upper part of the active matrix 41 and the other side parallel to the active matrix 41 via the air gap 55, Ii) a lower electrode 61 laminated on top of the membrane 57; iii) a deformed portion 63 stacked on top of the lower electrode 61. The lower electrode 61 is made of silicon carbide (SiC) An upper electrode 67 stacked on one side of the deformed portion 63 and v) a deformed portion 63 extending from the other side of the deformed portion 63 to the lower electrode 61, And an actuator (43) having a via hole (68) vertically formed to the upper portion of the drain (49) through the through hole (57). The active matrix according to claim 1, wherein the active matrix (41) further comprises a protective layer (51) stacked on the active matrix (41) and an etch stop layer (53) stacked on the protective layer Wherein the thin film type optical path adjusting device is a thin film type optical path adjusting device. The thin film type optical path adjusting apparatus according to claim 1, wherein the membrane (57) composed of silicon carbide has a thickness of 0.1 to 1.0 m. The actuator according to claim 1, wherein the actuator (43) is formed in the via hole (68) from the lower electrode (61) to the drain (49) to electrically connect the lower electrode Further comprising a via contact (69) formed on the substrate (10). Forming a drain on one side of an active matrix having M x N (M, N is an integer) transistors; And I) forming a membrane composed of silicon carbide on top of the active matrix, ii) forming a lower electrode on top of the membrane, iii) forming a deformation on top of the lower electrode, iv) (V) forming a via hole vertically from an upper portion of the other side of the deformation portion to an upper portion of the drain; and (vi) electrically connecting the lower electrode and the drain to the via hole Forming an active matrix on the active matrix, wherein the step of forming an active matrix comprises forming an active matrix. 6. The method of claim 5, wherein the membrane made of silicon carbide is formed by forming a protective layer on the actuator, forming an etch stop layer on the protective layer, forming a sacrificial layer on the etch stop layer And etching a portion of the sacrificial layer under the drain to expose a part of the etch stop layer. [6] The method of claim 5, wherein the silicon carbide membrane is formed at a temperature of 200 to 300 [deg.] C using a PECVD (Plasma Enhanced Chemical Vapor Deposition) method. The method according to claim 7, wherein the membrane made of silicon carbide is formed by heat treatment at a temperature of 600 ° C or less. 6. The method of claim 5, wherein the membrane comprised of silicon carbide is formed of silicon carbide produced from liquid C ₆ H ₁₈ O ₁₂ . The method of claim 5, wherein the method for manufacturing a thin-film optical path control device characterized in that the membrane consisting of the silicon carbide is formed of a silicon carbide prepared by mixing SiH ₄ and CH _4. [6] The method of claim 5, wherein forming the upper electrode further comprises patterning the upper electrode to form a stripe at the center of the upper electrode. The method according to claim 5, wherein the via contact is formed by sputtering platinum (Pt) or platinum-tantalum (Pt-Ta).