KR100228462B1 - Semiconductor device and the manufacturing method thereof - Google Patents

Abstract

Provided are a semiconductor device having a high capacitance ratio, a low resistance polysilicon gate electrode and a resistor suitable for an analog circuit, and a high mass productive semiconductor device and a manufacturing method thereof.

According to the present invention, a transistor having a gate having a laminated structure of a polycrystalline silicon layer and a silicide layer and a thermal oxide film of polycrystalline silicon are formed as an interlayer insulating film, and a capacitor having polycrystalline silicon as a positive electrode is formed, and the voltage coefficient is A highly reliable semiconductor device is formed by forming an excellent capacitor, a resistive element requiring a high low refractive index, a gate portion and a wiring portion requiring high speed on the same substrate. The first mask body covers the upper and side surfaces of the upper electrode, thereby preventing unnecessary etching of the upper electrode, and the gate electrode and the resistor formed of the first polycrystalline silicon when doping the second polycrystalline silicon layer also have low resistance. By controlling the sheet resistance of the lower electrode of the unit capacitor in the range of 30 to 1000 Ω / ?, it is possible to improve the performance of the switching capacitor filter without lowering the capacity ratio of the unit capacitor while keeping the gate electrode low. .

Description

Semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device suitable for an analog circuit using a capacitor formed of a polycrystalline silicon layer, in particular a switching capacitor circuit, and the like, and a method for manufacturing the same.

In recent years, semiconductor integrated circuits have become very fine. According to such a miniaturization aspect, the line width of the gate and wiring used for an element becomes small. In order to reduce the short channel effect caused by decreasing the line width of the gate, Japanese Unexamined Patent Publication No. 62-31506 discloses an insulating film formed by CVD (Chemical Vapor Deposition) by thermal decomposition of TEOS (tetra ethoxy silane), and anisotropic dry etching. A so-called LDD (Lightly Doped Drain) structure is described in which sidewalls are formed to form a double structure of a source and a drain.

In addition, as the miniaturization reduces the line width of the gate and the wiring, the resistance increases, which causes a problem of slowing down the signal transmission characteristics. In order to solve this problem, U.S. Patent No. 4,392,299 describes the deposition of metal silicide on polycrystalline silicon to form a low resistance gate or wiring.

However, in an analog circuit, a resistive element or a capacitor is used a lot, and when a resistive element having a high resistance is formed by wiring using the adaptive structure of low-resistance polycrystalline silicon and silicide as described above, the wiring needs to be lengthened, resulting in an increase in chip area. There was a problem. 2 is a circuit diagram showing the configuration of a general switching capacitor filter (hereinafter referred to as SCF). In FIG. 2, C1 and C2 are each composed of a plurality of unit capacitors. An example of a method of manufacturing a semiconductor device having such a unit capacitor will be described with reference to FIG.

First, as shown in FIG. 4 (a), after forming the field oxide film 2 on the semiconductor substrate 1, the first polysilicon layer 3 is formed on the field oxide film 2, for example. And thermal decomposition of SiH ₄ gas. Next, the first poly-crystalline silica goncheung (3) (重) doped layer (H ₁₎ by diffusion of a high concentration of an impurity diffusion method, such as POCl ₃ for to maintain a low resistance. The resist 8 is provided in the transistor formation region A and the capacitor formation region B, respectively, as shown in FIG. 4 (b) on the first polycrystalline silicon layer 3 of the dope layer H ₁ . After that, the first polysilicon layer 3 is patterned by, for example, photolithography and etching to form gate electrodes 3A (H ₁ ) and capacitor lower electrodes 3B (H ₁ ) (fourth). See also (c)]. In Fig. 4, reference numeral 10 denotes a gate oxide film.

Next, an interlayer insulating film 4 is deposited on the dope layer H ₁ as shown in FIG. 4 (d) by, for example, thermal oxidation or CVD. The second polysilicon layer 5 is deposited thereon (see also fourth (e)). Next, phosphorus is diffused in high concentration to the second polysilicon layer 5 in the same manner as the doping to the first polysilicon layer 3, so that the middle dope layer H ₂ is also made low. See also 4 (f)]. Then, as shown in FIG. 4 (g), after the resist 9 is provided on the second polycrystalline silicon layer 5 made of the heavy dope layer H ₂ , the second polycrystalline silicon layer 5 is formed. For example, patterning is performed by photolithography (see also fourth (h)).

3 shows an example in which the second polysilicon layer 5 is patterned first and then the first polysilicon layer 3 is patterned. In the above-described manufacturing method, the impurity concentration of the first polycrystalline silicon layer is increased in order to lower the gate electrode and the poly resistance (not shown). Therefore, in the lower electrode of the capacitor formed of the first polycrystalline silicon layer, crystal grains grow in the inside of the film 3 during the doping or after the doping, thereby causing irregularities on the surface of the film. The unit capacitor formed on such a polysilicon layer on the uneven surface has a low melt ratio. This capacity ratio is the ratio of the capacitors C1 and C2 in FIG. 2, for example, to determine the characteristics of the integrator and also to determine the characteristics of the SCF. Therefore, there is a problem that the characteristics of the SCF composed of a capacitor having a low melt ratio is also uneven.

In addition, since the interlayer insulating film of the gate oxide film or the capacitor causes a breakdown voltage due to the incorporation of impurities in the metal silicide or the like, there is a problem that the reliability of the interlayer insulating film of the gate oxide film or the capacitor is formed after the metal silicide is formed. In addition, since the gate oxide film and the interlayer insulating film of the capacitor are formed independently, there has been a demand to use an oxidation method suitable for each film.

In view of the above, this invention makes it a subject to provide the semiconductor future suitable for an analog circuit, and its manufacturing method. In particular, it is an object of the present invention to provide a semiconductor device having a high capacitance ratio, a low-resistance polysilicon gate electrode and a resistor, and also having high mass productivity.

In order to solve the above problems, claim 1 of the present invention is a MOS transistor having a gate electrode formed on a semiconductor substrate and consisting of a polysilicon layer and a metal silicide layer, and a first polycrystalline silicon layer and interlayer insulation forming a lower electrode layer. A semiconductor device comprising a capacitor comprising a second polycrystalline silicon layer forming a layer and an upper electrode layer.

Claim 2 of the present invention is the semiconductor device according to claim 1, wherein the capacitor is covered with the upper electrode layer and its side surface by an insulating layer.

Claim 3 of the present invention is the semiconductor device according to claim 1, wherein the metal silicide comprises at least one layer selected from WSi, MoSi ₂ , TiSi ₂ , TaSi ₂ , and CoSi ₂ .

Claim 4 of the present invention is a semiconductor device according to claim 1, characterized in that the insulating layer is SiO _2.

Claim 5 of the present invention is a semiconductor device according to claim 1, characterized in that the insulating layer covering the first polycrystalline silicon layer is SiO _2.

Claim 6 of the present invention is the semiconductor device according to claim 1, wherein the insulating layer covering the second polycrystalline silicon layer is SiN.

Claim 7 of this invention is a semiconductor device of Claim 1 whose sheet resistance of the said 1st polycrystal silicon layer is 30-1000 ohms / ?.

Claim 8 of the present invention is the semiconductor device according to claim 1, wherein the capacitor is a unit capacitor.

Claim 9 of the present invention is the semiconductor device according to claim 1, wherein the resistance of the lower electrode layer portion is higher than that of the other polycrystalline silicon layer.

Claim 10 of the present invention provides a MOS transistor having a gate electrode composed of a polycrystalline silicon layer and a metal silicide layer, a first polycrystalline silicon layer forming a lower electrode layer, an interlayer insulating film, and an upper electrode layer formed on a semiconductor substrate. A semiconductor device comprising a capacitor made of a polycrystalline silicon layer and a resistor made of a single layer of a polycrystalline silicon layer.

Claim 11 of the present invention is that the impurity concentration of the lower electrode of the capacitor composed of polycrystalline silicon is relatively lower than the impurity concentration of the surrounding, the sheet resistance value is 30 ~ 1000Ω /? It is a semiconductor device characterized by the above-mentioned.

For example, a field oxide film for separation between elements is formed on a semiconductor substrate of silicon substrate capability. Subsequently, a gate oxide film is formed in a portion where the field oxide film of the semiconductor substrate is not formed, and a first polycrystalline silicon layer is deposited on the gate oxide film and the field oxide film to form phosphorus as an impurity. The surface of the first polycrystalline silicon layer is oxidized, for example, by thermal oxidation in an oxidizing atmosphere, or an insulating layer of SiN or SiO ₂ is formed by CVD to form a second polycrystalline silicon layer on the insulating layer. For example, a resist is used to etch the second polycrystalline silicon layer, leaving a portion of the capacitor as the upper electrode layer, and selectively deposit the first mask body covering the upper electrode layer and its side surface. As the first mask body, an insulating layer of SiN or SiO ₂ formed by CVD can be used.

Subsequently, after forming the metal silicide layer, a second mask body such as a resist is formed on the portion of the MOS transistor to serve as a gate electrode, and the first polycrystalline silicon layer and the metal silicide layer are etched. As the metal silicide, at least one selected from high melting point metal silicide, for example, tungsten silicide (WSi), molybdenum silicide (MoSi ₂ ), titanium silicide (TiSi ₂ ), tantalum silicide (TaSi ₂ ), and cobalt silicide (CoSi ₂ ) Layers consisting of one or more layers can be used.

In this manner, a capacitor including a gate electrode having a laminated structure of polycrystalline silicon and a metal silicide, an electrode of a polycrystalline silicon layer, and an interlayer insulating film of a silicon oxide film can be obtained on the same semiconductor substrate. Therefore, the wiring portion and the gate electrode portion become low resistance, the capacitor portion has high breakdown voltage and high melt ratio.

If the impurity is diffused into the first polycrystalline silicon layer so as to have a sheet resistance of 30 to 1000 Ω / Ω, growth of silicon crystal grains in the electrode portion can be suppressed and the occurrence of irregularities on the electrode surface can be reduced. Therefore, the precision ratio of the unit capacitors is not lowered.

In addition, the upper electrode layer and its side surface are covered with a first mask, and a portion of the polycrystalline silicon layer monolayer, which becomes a resistor, is formed of a laminated structure of a polycrystalline silicon layer and a metal silicide layer, and an electrode and a silicon oxide film of the polycrystalline silicon layer. A capacitor composed of an interlayer insulating film and a resistor composed of a single layer of a polycrystalline silicon layer can be formed. Therefore, a high resistance resistor can be formed in addition to the above-described capacitor and gate electrode, so that the chip size can be reduced.

In addition, the second polycrystalline silicon layer is etched and the insulating layer on the first polycrystalline silicon layer is etched, and then the first polycrystalline silicon layer is not covered with the second polycrystalline silicon layer and the second polycrystalline silicon layer by diffusing impurities. When the second polycrystalline silicon layer is doped by lowering the resistance of the gate electrode and the resistor formed of the first polycrystalline silicon layer, the resistance is also reduced. Therefore, according to the present invention, the performance of the SCF can be improved without lowering the precision ratio of the unit capacitor while keeping the gate electrode or the like at low resistance.

In addition, the present invention can be carried out while maintaining the mass productivity if the doping to the first and second polycrystalline silicon layer is treated by thermal diffusion method.

1 is a process diagram for explaining a first embodiment of a method of manufacturing a semiconductor device of the present invention, and FIGS. 1 (a) to 1 (f) are schematic cross-sectional views showing the structure of a semiconductor device after each process.

2 is a circuit diagram showing the configuration of a typical SCF.

3 is a process diagram for explaining an example of a conventional semiconductor device manufacturing method, and FIGS. 3 (a) to 3 (i) are cross-sectional views showing an excavation of the semiconductor device after each step.

4 is a process diagram for explaining another example of a conventional method for manufacturing a semiconductor device, and FIGS. 4A to 4H are schematic sectional views showing the structure of the semiconductor device after each process.

* Explanation of symbols for main parts of the drawings

50 semiconductor substrate 51 filter oxide film

52: first polycrystalline silicon layer 53: interlayer insulating film

54 second polycrystalline silicon layer 55 gate oxide film

56,58: Resist 57: First Mask Body (Insulation Layer)

59 metal silicide layer 60 second mask body (resist)

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same reference numerals are assigned to the same numbers, and repetitive descriptions are omitted.

[First Embodiment]

1 is an example of forming an important capacitor in a CMOS analog circuit with a process diagram showing a process of the semiconductor device of the present invention and a manufacturing method thereof. In a CMOS analog circuit, it is preferable to use a capacitor having polysilicon excellent in voltage characteristics and temperature characteristics as a positive electrode and a silicon oxide film as an interlayer insulating film. Therefore, the present embodiment provides a method of realizing the interlayer insulating film on the same substrate as the MOS transistor using the high melting point silicide film having high speed as the wiring and gate material. In addition, wiring, a passivation film, etc., such as aluminum, are abbreviate | omitted and shown.

In FIG. 1, reference numeral 50 is a semiconductor substrate, 51 is a field oxide film, 55 is a gate oxide film, 56 is a first polycrystalline silicon layer, 53 is an interlayer insulating film, and 54 is a second film. Polycrystalline silicon layer, 56 is a resist, 57 is an insulating layer to be a first mask body, 58 is a resist for forming a first mask body, 59 is a metal silicide layer, and 60 is a second layer It is a mask body.

두께로 형성한다. 또 다결정 실리콘층(52)을 LPCVD(Low Pressure Chemical Vapor Deposition) 등으로 예를 들면, 3000

두께로 형성한다. 다결정 실리콘층(52)은 커패시터의 하부 전극이 됨과 동시에 게이트나 배선에 사용되는 고융점 금속 실리사이드막과 다결정 실리콘막의 적층 구조의 하부측이 된다. 이어서, 다결정 실리콘층(53)에 불순물로서 인을 기상 확산 방법에 의해 도핑한다.The field oxide film 51 is formed on the surface of the silicon substrate 50 by the method known in FIG. 1 (a), and the gate oxide film 55 is formed as the first insulating film in the active region, for example, 250.

Form to thickness. Further, the polycrystalline silicon layer 52 may be, for example, 3000 by low pressure chemical vapor deposition (LPCVD) or the like.

Form to thickness. The polycrystalline silicon layer 52 serves as the lower electrode of the capacitor and at the lower side of the laminated structure of the high melting point metal silicide film and the polycrystalline silicon film used for the gate and wiring. Subsequently, the polycrystalline silicon layer 53 is doped with phosphorus as an impurity by a vapor phase diffusion method.

이다. 또, 층간 절연막(53)상에 제2다결정 실리콘막(54)을 형성해서 인을 도핑한다. 다결정 실리콘층(54)은 커패시터의 상부 전극으로 되는 부분이다. 형성 조건은 다결정 실리콘층(52)의 형성 조건과 동일하면 된다.Next, in the oxidizing atmosphere, the surface of the polycrystalline silicon layer 52 is thermally oxidized to form an interlayer insulating film 53 which is an insulating layer. The thickness of the interlayer insulating film 53 is 450, for example.

to be. Further, a second polycrystalline silicon film 54 is formed on the interlayer insulating film 53 to dope phosphorus. The polycrystalline silicon layer 54 is a portion that becomes the upper electrode of the capacitor. The formation conditions may be the same as those of the polycrystalline silicon layer 52.

Next, as shown in FIG. 1 (b), a resist 56 is formed on the portion of the capacitor that is to be the upper electrode, and the polycrystalline silicon layer 54 is etched. The insulating layer 53 may also be etched.

두께로 형성해서 절연층으로 한다. 실리콘 산화층(57)은 다결정 실리콘층(52)과 에칭 선택비가 충분히 큰 것이면 되고 실리콘 산화층(57) 대신 예를 들면, 질화실리콘(SiN)이라도 좋다.Next, after removing the resist 56, as shown in FIG. 1 (c), the silicon oxide layer 57 by thermal decomposition of TEOS (tetra ethoxy silane) is, for example, 1000

It is formed in thickness and it is set as an insulating layer. The silicon oxide layer 57 may have a sufficiently large etching selectivity with the polycrystalline silicon layer 52, and may be silicon nitride (SiN) instead of the silicon oxide layer 57, for example.

Further, a resist 58 is formed on a portion of the polycrystalline silicon layer 52 to be the lower electrode of the capacitor on the silicon oxide layer 57, the silicon oxide layer 57 and the interlayer insulating film 53 are etched, and then the resist ( 58) is removed and the 1st mask body 57 is formed as shown to FIG. 1 (d). The first mask body 57 is deposited to cover the upper surface and side surfaces of the second polycrystalline silicon layer serving as the upper electrode layer. As described later, the second mask body 60 serves as a mask for etching the metal silicide and prevents contamination by the metal particles that fly when etching the metal silicon layer. In addition, it serves to prevent a short circuit between the upper electrode and the lower electrode. Although not shown in the drawing, the first mask body 57, that is, the silicon oxide layer 57 is selectively left on the portion of the second polycrystalline silicon layer 54 that becomes a resistive element, thereby forming the portion as a high resistance resistive element. can do.

두께로 형성한다. 다결정 실리콘층과 실리사이드층과의 적층 구조로되어야 할 부분에 제2마스크체인 레지스트(60)를 형성하고, 플라즈마 에칭법을 이용해서 텅스텐 실리사이드와 다결정 실리콘을 에칭한다. 이때, 레지스트(60)부분은 에칭되지 않고 다결정 실리콘층과 실리사이드층의 적층 구조로 된다. 이러한 적층 구조는 MOS 트랜지스터의 게이트 전극이 된다.Next, as shown in FIG. 1 (e), the tungsten silicide 59 is, for example, 2000

Form to thickness. A resist 60, which is a second mask body, is formed in a portion of the polycrystalline silicon layer and the silicide layer to be laminated, and tungsten silicide and polycrystalline silicon are etched using a plasma etching method. At this time, the portion of the resist 60 is not etched into a laminated structure of the polycrystalline silicon layer and the silicide layer. This stacked structure becomes a gate electrode of a MOS transistor.

The portion of the silicon oxide layer 57 is etched with tungsten silicide thereon, but the polycrystalline silicon layer 52, the interlayer insulating film 53, and the polycrystalline silicon layer 54 under the silicon oxide layer 57 are formed of the silicon oxide layer 57. It functions as a mask to form a capacitor composed of the polycrystalline silicon layers 52 and 54 and the interlayer insulating film 53. In addition, the portion formed by the mask body formed on the first polycrystalline silicon layer 52 becomes a high resistance region where tungsten silicide is not deposited and can be used as a resistance element.

Subsequently, impurities are diffused into the active region using the gate electrode as a mask to form a source drain diffusion layer (see also first (f)).

The capacitor according to the present embodiment thus obtained can be formed under conditions suitable for oxidizing polycrystalline silicon because its interlayer insulating film can be formed separately from other films, for example, gate oxide films. Therefore, silicide contamination can be prevented, resulting in a highly reliable interlayer insulating film.

In addition, the transistor has a laminated structure in which the gate portion is composed of a tungsten silicide and a polycrystalline silicide film, so that the transistor can operate at high speed at low resistance, and the gate oxide film can be formed independently before the polycrystalline silicon layer or the silicide layer is formed, thereby providing high reliability. It can be a gate oxide film.

As described above, according to the present embodiment, the interlayer insulating film of the gate oxide film and the capacitor can be formed before forming the polycrystalline silicon layer or the silicide layer, and the interlayer insulating film of the gate oxide film and the capacitor can be formed under separate conditions. In addition, since the first mask body covers the upper and side surfaces of the upper electrode, contamination during the etching of the metal silicide can be prevented, and unnecessary etching of the upper electrode can be prevented.

In this embodiment, the interlayer insulating film is formed by thermal oxidation, but may be formed by CVD.

Second Embodiment

This embodiment corresponds almost to the manufacturing method of the semiconductor device shown in FIG. However, in the present embodiment, the sheet resistance value is controlled in the range of 30 to 1000 Ω / ?, preferably 35 to 1000 Ω /? As a result of controlling the amount of indoping into the first polycrystalline silicon layer 3 to a specific value. It differs in that it performs the process which makes the 1st polycrystalline silicon layer 52 into a hardness dope layer, and is performed after patterning the doping with respect to the 2nd polycrystalline silicon layer 54. FIG.

의 제1다결정 실리콘층(52)을 형성한 후, 제1다결정 실리콘층(52)에 대해 특정 조건에서 도핑한다. 이러한 도핑은 예를 들면, N₂가스(5ℓ/분), O₂가스(0.5ℓ/분) 및 POCl₃가스(120mg/분)로 이루어지는 혼합 가스를 온도 1000℃ 정도로 가열한 반응실 내로 유입하여 4분간 행한다. 이러한 조건에 따름으로써, 제1다결정 실리콘층(52)의 시트 저항값을 상술한 특정 범위 내로 제어할 수 있다. 이러한 특정 범위의 시트 저항값을 나타내는 다결정 실리콘층에서는 도핑 중의 열 또는 도핑 후의 열공정에서의 열에 노출되어도 막 내부에서 결정립이 발생하지 않기 때문에 막 표면에 요철이 생기지 않는다.Referring to the sheet resistance value control process, the film thickness 3500

After the first polycrystalline silicon layer 52 is formed, the first polycrystalline silicon layer 52 is doped under specific conditions. Such doping is introduced into a reaction chamber in which, for example, a mixed gas consisting of N ₂ gas (5 L / min), O ₂ gas (0.5 L / min) and POCl ₃ gas (120 mg / min) is heated to a temperature of about 1000 ° C. 4 minutes. By following these conditions, the sheet resistance value of the first polycrystalline silicon layer 52 can be controlled within the above-mentioned specific range. In the polycrystalline silicon layer exhibiting such a specific range of sheet resistance values, no grains occur in the film surface because no grains are generated inside the film even when exposed to heat during doping or heat during thermal processing after doping.

After the sheet resistance value control process for the first polycrystalline silicon layer 52, as shown in FIG. 1 (b), a resist (2) is deposited on the second polycrystalline silicon layer 54 where dopants are not diffused. 56 is provided to pattern the second polycrystalline silicon layer 54. At this time, you may pattern with respect to the lower interlayer insulation film 53. Next, the sheet resistance as described above except that the doping time for the surface of the first polycrystalline silicon film 51 not covered with the second polycrystalline silicon layer 54 and the second polycrystalline silicon layer 54 is 9 minutes. Doping is carried out under the same conditions as doping in the value control process. According to this process, the dopant (phosphorus) concentration becomes high about the 2nd polycrystalline silicon layer 54 already patterned, and it becomes a middle dope layer. In addition, the exposed portion of the first polycrystalline silicon layer 52 not covered with the second polycrystalline silicon layer 54 has a high concentration exceeding the dopant (phosphorus) concentration before doping, and this also becomes a middle dope layer. The portion of the first polycrystalline silicon layer 52 covered with the second polycrystalline silicon layer 54 is a lightly doped layer with the dopant (phosphorus) concentration before doping. Subsequently, similarly to FIGS. 1C to 1F, a semiconductor device having a desired unit capacitor structure, a semiconductor having a gate electrode and a resistance element is obtained.

In such a semiconductor device, the portion of the first polycrystalline silicon layer 52 surrounded by the intermediate dope layer has a dopant concentration maintained in a predetermined range and remains a hard dope layer. The lightly-doped layer can be used as the lower electrode of the capacitor, the middle-doped layer above the lightly-doped layer can be used as the upper electrode of the capacitor, and both of the dope layers constitute a unit capacitor via the interlayer insulating film 53. A plurality of unit capacitors are assembled to form C1 or C2 of the SCF in FIG. In this embodiment, the sheet resistance of the hardness dope layer as the lower electrode of the capacitor is controlled within a specific range so that unevenness does not occur on the surface thereof, so that the hardness dope layer does not lower the accuracy ratio of the unit capacitor. By using the light-hardened layer with unevenness on the surface as a single electrode for the unit capacitor, the accuracy ratio can be easily increased, and the performance of the SCF can also be improved.

In the above embodiment, the doping time for setting the patterned second polycrystalline silicon layer 54 as the intermediate dope layer was set to 9 minutes. However, the doping amount may be arbitrarily changed to 4 to 9 minutes. In this case, the patterned second polycrystalline silicon layer 54 does not become a middle dope layer, but becomes a hardness dope layer like the first polycrystalline silicon layer 52 in the lower portion thereof. However, even in this case, the portion adjacent to the first polycrystalline silicon layer 52 which is the hard dope layer becomes a middle dope layer because of its high impurity concentration. Also in this case, the portion of the first polycrystalline silicon layer 52, which is a hard-doped layer, functions as the lower electrode of the capacitor is the same as that of the above embodiment.

In addition, in the present embodiment, not only the first polycrystalline silicon layer 52 but also the second polycrystalline silicon layer 54 can be doped to be a hardness dope layer. In each of the above embodiments, since all of them can be manufactured using conventional thin film deposition techniques, impurity diffusion techniques, etc., there is an effect that is excellent in mass productivity. In each of the above examples, phosphorus was used as an impurity, but is not limited thereto.

As described above, according to the present invention, a transistor having a high speed operation having a stacked structure of a polysilicon layer and a silicide layer and a thermal oxide film of a polycrystalline silicon are used as an interlayer insulating film, and the voltage characteristics using polycrystalline silicon as a positive electrode are excellent. Capacitors can be formed. In addition, the gate oxide film of the transistor is formed before the injection of high concentration impurities into the polycrystalline silicon, and the interlayer insulating film of the capacitor is formed before the silicide layer is formed, thereby protecting each insulating film from contamination of impurities or silicides, Since oxidation and oxidation of an interlayer insulation film can be performed separately, it can form on the oxidation conditions suitable for each, and can provide a highly reliable semiconductor device.

In addition, since the first mask body covers the upper and side surfaces of the upper electrode, contamination during metal silicide etching can be prevented and unnecessary etching of the upper electrode can be prevented.

In addition to the transistor and the capacitor, a single layer structure of high resistance polycrystalline silicon can be formed on the same substrate. Therefore, a capacitor having excellent voltage coefficient, a resistance element requiring high resistivity, a gate portion and a wiring portion requiring high speed can be formed on the same substrate.

In addition, by controlling the sheet resistance of the lower electrode of the unit capacitor in the range of 30 to 1000 Ω /? It is possible to improve the performance of the SCF to which the present invention is applied without lowering the precision ratio of the unit capacitor. In addition, when the second polycrystalline silicon layer is doped, the gate electrode and the resistor formed of the first polycrystalline silicon are also reduced in resistance. Therefore, according to the present invention, the performance of the SCF can be improved without lowering the precision ratio of the unit capacitor while keeping the gate electrode or the like at low resistance.

In addition, the present invention can be implemented while maintaining mass productivity by treating the doping of the first and second polycrystalline silicon layers by thermal diffusion method.

Claims (10)

A MOS transistor having a gate electrode formed of a polycrystalline silicon layer and a metal silicide layer, and a first polycrystalline silicon layer forming a lower electrode layer, an interlayer insulating layer, and an upper electrode layer provided on the semiconductor substrate. A semiconductor device comprising a capacitor made of a polycrystalline silicon layer. The semiconductor device according to claim 1, wherein said capacitor is covered with said upper electrode layer and its side surfaces by an insulating layer. The semiconductor device of claim 1, wherein the metal silicide comprises at least one layer selected from WSi, MoSi ₂ , TiSi ₂ , TaSi ₂ , and CoSi ₂ . The method of claim 1, wherein the semiconductor device is characterized in that the insulating layer is SiO _2. The method of claim 1, wherein said semiconductor device characterized in that the insulating layer covering the second polysilicon layer is SiO _2. The semiconductor device according to claim 1, wherein the insulating layer covering said second polycrystalline silicon layer is SiN. The semiconductor device according to claim 1, wherein the sheet resistance value of said first polycrystalline silicon layer is 30 to 1000? / ?. The semiconductor device of claim 1, wherein the capacitor is a unit capacitor. The semiconductor device according to claim 1, wherein the resistance of the lower electrode layer portion is larger than that of the other polycrystalline silicon layer. A MOS transistor having a gate electrode composed of a polycrystalline silicon layer and a metal silicide layer, formed on a semiconductor substrate, a first polycrystalline silicon layer forming a lower electrode layer, an interlayer insulating film, and a second polycrystalline silicon layer forming an upper electrode layer. A semiconductor device comprising a capacitor comprising a resistor and a resistor made of a single layer of a polycrystalline silicon layer.

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