JP3290506B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device suitable for an analog circuit such as a capacitor electrode or a MISFET gate formed of a polycrystalline silicon layer (film). The present invention relates to an apparatus and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated devices have been extremely miniaturized. With such miniaturization, the line width of gates and wirings used in devices has been reduced. Japanese Patent Publication No. Sho 62-31506 discloses a method of reducing the short channel effect caused by a reduction in the line width of a gate by CVD (Chemical Vapor Depo) by thermal decomposition of TEOS (tetraethoxysilane).
a so-called LDD (Light), in which an insulating layer is formed by the formation of an insulating layer, sidewalls are formed by anisotropic dry etching, and the source and the drain have a double structure.
ly Doped Drain) structure is described.

Further, since the line width of gates and wirings is reduced with miniaturization, there is a problem that the resistance is increased and the signal transmission characteristics are reduced. In order to solve such a problem, U.S. Pat. No. 4,392,299 discloses that a low-resistance gate or wiring is formed by laminating silicide on polycrystalline silicon.

[0004]

However, in an analog circuit, a resistance element and a capacitor are frequently used, and a high-resistance resistance element is formed by wiring having a laminated structure of a low-resistance polycrystalline silicon layer and a silicide layer as described above. If it is formed, it is necessary to lengthen the wiring, and there is a problem that the chip area is increased.

FIG. 2 is a circuit diagram showing a configuration of a general switched capacitor filter (hereinafter abbreviated as SCF). In FIG. 2, C1 and C2 are each configured as an aggregate of a plurality of unit capacitors. An example of a method for manufacturing a semiconductor device having this unit capacitor will be described with reference to FIG.

First, as shown in FIG. 3A, after a field oxide layer 2 is formed on a semiconductor substrate 1, a first polysilicon layer (polysilicon layer) is formed on the field oxide layer 2. 3 is deposited by, for example, thermal decomposition of SiH4 gas. Next, in order to reduce the resistance, phosphorus as an impurity is diffused into the first polycrystalline silicon layer 3 at a high concentration by a diffusion method such as POCl3 to form a heavy doped layer H1.
And As shown in FIG. 3B, a resist 8 is provided on each of the transistor formation region A and the capacitor formation region B on the first polycrystalline silicon layer 3 which has been made into the heavy doped layer H1. The crystalline silicon layer 3 is patterned by, for example, photolithography and etching to form a gate electrode 3A (H1) and a capacitor lower electrode 3B (H2) (FIG. 3).
(C)). In FIG. 3, reference numeral 10 denotes a gate oxide layer.

Next, on this heavy dope layer H1,
As shown in FIG. 3D, an interlayer insulating layer 4 is deposited by, for example, thermal oxidation or CVD. A second polycrystalline silicon layer 5 is deposited thereon (see FIG. 3E). next,
Phosphorus is diffused into the second polycrystalline silicon layer 5 at a high concentration by the same method as the doping of the first polycrystalline silicon layer 3, and this is also made into a heavy doped layer H2 for lowering the resistance (FIG. 3 (F)). Next, FIG.
As shown in (G), the second doped heavy layer H2
After the resist 9 is provided on the polycrystalline silicon layer 5, the second polycrystalline silicon layer 5 is patterned by, for example, photolithography (see FIG. 3H).

FIG. 4 shows a second polycrystalline silicon layer 5.
After first patterning the first polycrystalline silicon layer 3
This is an example of patterning. In the manufacturing method described above,
In order to reduce the resistance of the gate electrode and the poly resistor (not shown in the figure), the impurity concentration of the first polysilicon layer increases. Therefore, in the capacitor lower electrode formed of the first polycrystalline silicon layer, crystal grains grow inside the layer 3 during the doping or in a subsequent heat step, and irregularities are generated on the layer surface. The unit capacitor formed on the polycrystalline silicon layer having such an uneven surface has a reduced specific accuracy. This ratio accuracy is determined by the capacitor C in FIG.
The ratio of 1 to C2, for example, determines the characteristics of the integrator and also determines the characteristics of the SCF. Therefore, there is an inconvenience that the characteristics of the SCF composed of capacitors having low specific accuracy vary.

In addition, since the gate oxide layer and the interlayer insulating layer of the capacitor are reduced in the breakdown voltage and the like by mixing impurities from silicide or the like, the formation of the gate oxide layer and the interlayer insulating layer of the capacitor must be performed by the metal silicide layer. If performed after formation, there is a problem that reliability is impaired. There is also a demand that the gate oxide layer and the interlayer insulating layer of the capacitor are formed independently, so that an oxidation method suitable for each layer is used.

[0010]

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a method of manufacturing a semiconductor device suitable for an analog circuit. In particular, it is an object of the present invention to provide a method for manufacturing a semiconductor device having a capacitor with high specific accuracy, a polycrystalline silicon gate electrode and a resistor with low resistance, and high productivity.

[0011]

According to a first aspect of the present invention , there is provided a method of manufacturing a semiconductor device, comprising: forming a field oxide layer and a gate oxide layer on a semiconductor substrate; Depositing a layer, forming an insulating layer on the first polycrystalline silicon layer, forming a second polycrystalline silicon layer on the insulating layer, and leaving a portion to be an upper electrode layer of the capacitor. Etching a second polycrystalline silicon layer and the insulating layer, selectively depositing a first mask body covering the upper electrode layer and side surfaces thereof ,
A metal silicide layer is formed over the entire surface of the obtained laminate.
Forming a second mask on a portion to be a gate electrode of a MOS transistor, etching the first polycrystalline silicon layer and the metal silicide layer, and forming a laminated structure of a polycrystalline silicon layer and a metal silicide layer. And a capacitor comprising a gate electrode comprising a polycrystalline silicon layer electrode and an interlayer insulating layer comprising a silicon oxide layer.

In the method of manufacturing a semiconductor device described above,
The first mask body may be an insulating layer.

In the above-described method of manufacturing a semiconductor device,
The first mask body is made of SiO ₂ formed by CVD.
It may be.

In the method of manufacturing a semiconductor device described above,
The first mask body may be SiN formed by CVD.

In the above-described semiconductor manufacturing method, the metal silicide layer is formed of WSi, MoSi ₂ , TiSi ₂ ,
It may be composed of at least one or more layers selected from TaSi ₂ and CoSi ₂ .

In the method of manufacturing a semiconductor device described above,
The first polycrystalline silicon layer has a sheet resistance of 30 to 1
The impurities may be diffused so as to be 000Ω / □.

In the method of manufacturing a semiconductor device according to the second invention, a field oxide layer and a gate oxide layer are formed on a semiconductor substrate, a first polysilicon layer is deposited, and the first polysilicon layer is formed. Forming an insulating layer thereon, forming a second polycrystalline silicon layer on the insulating layer, etching the second polycrystalline silicon layer and the insulating layer except for a portion serving as an upper electrode layer of the capacitor, A first mask body covering the upper electrode layer and its side surface and a portion serving as a resistor of the single-layer polysilicon layer is selectively applied, and then the first mask body obtained above is obtained.
A metal silicide layer over the entire surface of the
Form, the second mask member is formed in a portion serving as a gate electrode of the MOS transistor, wherein the first polycrystalline silicon layer said metal silicide layer is etched, laminated structure of a polysilicon layer and a metal silicide layer And a capacitor comprising a gate electrode comprising a polycrystalline silicon layer electrode and an interlayer insulating layer comprising a silicon oxide layer.

In the method of manufacturing a semiconductor according to the second aspect of the present invention , the second polycrystalline silicon layer is etched, the insulating layer on the first polycrystalline silicon layer is etched, and impurities are diffused. The resistance between the second polycrystalline silicon layer and the first polycrystalline silicon layer that is not covered by the second polycrystalline silicon layer may be reduced.

According to a third aspect of the invention , there is provided a method of manufacturing a semiconductor device, comprising: forming a first polycrystalline silicon layer on an oxide layer formed on a semiconductor substrate; A step of diffusing impurities to control a sheet resistance value of the first polycrystalline silicon layer within a range of 30 to 1000 Ω / □, and an insulating layer on the first polycrystalline silicon layer after the step of controlling the sheet resistance. Forming a second polycrystalline silicon layer to be an upper electrode of the capacitor through the step of forming a second capacitor; patterning the second polycrystalline silicon layer to form an upper electrode of the unit capacitor; By further diffusing impurities into the first polycrystalline silicon layer using the formed second polycrystalline silicon layer as a mask, the first polycrystalline silicon layer below the second polycrystalline silicon layer is diffused. Increasing the impurity concentration of the other portion except the first polycrystalline silicon layer having a controlled sheet resistance value, and patterning the first polycrystalline silicon layer to form a gate and a unit capacitor. Forming a lower electrode.

According to a fourth aspect of the present invention , there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a first polysilicon layer on an oxide layer formed on a semiconductor substrate; Diffusing impurities to control the sheet resistance value of the first polycrystalline silicon layer within a range of 30 to 1000 Ω / □; patterning the first polycrystalline silicon layer to form a gate and a capacitor; Forming an interlayer insulating layer on the first polycrystalline silicon layer patterned by the patterning step, and then forming a second polysilicon layer serving as an upper electrode of a capacitor on the interlayer insulating layer. Forming a crystalline silicon layer;
Patterning the polycrystalline silicon layer of
Diffusing impurities into the polycrystalline silicon layer of
Increasing the impurity concentration of the other portion of the first polycrystalline silicon layer below the polycrystalline silicon layer except for the first polycrystalline silicon layer having a controlled sheet resistance value. Features.

[0021]

A field oxide layer for element isolation is formed on a semiconductor substrate such as a silicon substrate. A gate oxide layer is formed on a portion of the semiconductor substrate where the field oxide layer is not formed, a first polysilicon layer is formed on the gate oxide layer and the field oxide layer, and, for example, phosphorus is diffused as an impurity. The surface of the first polycrystalline silicon layer is oxidized by, for example, thermal oxidation in an oxidizing atmosphere, or an insulating layer of SiN or SiO2 is formed by CVD, and a second insulating layer is formed on the insulating layer in the same manner. A polycrystalline silicon layer is formed. For example, phosphorus is diffused as an impurity. For example, the above-mentioned second polycrystalline silicon layer is etched by using a resist while leaving a portion to be the upper electrode of the capacitor, and the above-mentioned upper electrode layer and the first mask body covering the side surface thereof are selectively deposited. I do. As the first mask body, an insulating layer of SiN or SiO2 formed by CVD can be used.

Next, on the entire surface of the laminate obtained above,
A metal silicide layer is formed , a second mask body such as a resist is formed on a portion to be a gate electrode of the MOS transistor, and the first polycrystalline silicon layer and the metal silicide layer are etched. As the metal silicide layer , a refractory metal silicide such as tungsten silicide (WSi) or molybdenum silicide (MoSi2
), Titanium silicide (TiSi2), tantalum silicide (TaSi2), cobalt silicide (CoS
A layer consisting of at least one layer selected from i2) can be used.

In this manner, a MOS transistor having a gate electrode having a laminated structure (first conductive layer) of a polycrystalline silicon layer and a metal silicide layer on the same substrate, and a single layer structure of a polycrystalline silicon layer (Second conductive layer), a semiconductor device having a resistance element is obtained.

Similarly, it is possible to obtain a gate electrode having a laminated structure of a polycrystalline silicon layer and a metal silicide layer on the same semiconductor substrate, and a capacitor comprising an electrode of a polycrystalline silicon layer and an interlayer insulating layer of a silicon oxide layer. it can. For this reason, the wiring portion and the gate electrode portion have low resistance, and the capacitor portion has high withstand voltage and high specific accuracy.

When an impurity is diffused into the first polycrystalline silicon layer so that the sheet resistance becomes 30 to 1000 Ω / □, the growth of silicon crystal grains at the electrode portion can be suppressed. Can be reduced. Therefore, the specific accuracy of the unit capacitor is not reduced.

Further, the upper electrode layer and its side surfaces are covered with the first mask body, and the portion of the polycrystalline silicon layer serving as a resistor is covered, thereby forming a laminated structure of the polycrystalline silicon layer and the metal silicide layer. A capacitor comprising a gate electrode comprising a polycrystalline silicon layer, an electrode comprising a polycrystalline silicon layer and an interlayer insulating layer comprising a silicon oxide layer, and a resistor comprising a single layer of a polycrystalline silicon layer can be formed. Therefore, in addition to the above-described capacitor and gate electrode, a high-resistance element can be formed, and the chip size can be reduced.

Further, while etching the second polycrystalline silicon layer, etching the insulating layer on the first polycrystalline silicon layer, and then diffusing impurities to form the second polycrystalline silicon layer and the second polycrystalline silicon layer. When the second polycrystalline silicon layer is doped by lowering the resistance with the first polycrystalline silicon layer which is not covered with the crystalline silicon layer, the gate electrode and the resistance formed by the first polycrystalline silicon layer are reduced. The body also has low resistance. Therefore, according to the present invention, it is possible to improve the performance of the SCF without lowering the specific accuracy of the unit capacitor while keeping the gate electrode and the like at low resistance.

Further, the present invention can be carried out while maintaining mass productivity because doping of the first and second polycrystalline silicon layers is performed by a thermal diffusion method.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. Note that the same components are denoted by the same reference numerals throughout the drawings, and repeated description will be omitted. Embodiment 1 FIG. 1 is a process diagram showing a process of a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which an important capacitor is formed in a CMOS analog circuit. Polycrystalline silicon with excellent voltage and temperature coefficients for CMOS analog circuits
It is desirable to use a capacitor in which the layers are both electrodes and the silicon oxide layer is an interlayer insulating layer. Therefore, in the present embodiment, the above-described interlayer insulating layer is formed of a MOS using a refractory metal silicide layer excellent in high speed as a wiring and a gate material.
It is intended to provide a method which can be realized on the same substrate as a transistor. It should be noted that wiring such as aluminum, a passivation layer, and the like are omitted.

In FIG. 1, 50 is a semiconductor substrate, 51 is a field oxide layer, 55 is a gate oxide layer, 52 is a first polycrystalline silicon layer, 53 is an interlayer insulating layer, 54 is a second polycrystalline silicon layer, Reference numeral 56 denotes a resist, 57 denotes an insulating layer serving as a first mask, 58 denotes a resist for forming the first mask, 59 denotes a metal silicide layer, and 60 denotes a second mask.

Referring to FIG. 1A, a field oxide layer 51 is formed on the surface of a silicon substrate 50 by a known method, and a gate oxide layer 55 is formed as a first insulating layer to a thickness of, for example, 250 ° in an active region. . Further, the polycrystalline silicon layer 52 is formed by LPCVD (Low Pressure).
Chemical Vapor Deposition
n) and the like, for example, to a thickness of 3000 °. The polycrystalline silicon layer 52 serves as a lower electrode of the capacitor, and also serves as a lower side of the laminated structure of the refractory metal silicide layer used for the gate and the wiring and the polycrystalline silicon layer. Next, the polycrystalline silicon layer 52 is doped with phosphorus as an impurity by a vapor phase diffusion method.

Next, the surface of the polycrystalline silicon layer 52 is thermally oxidized in an oxidizing atmosphere to form an interlayer insulating layer 53 as a second insulating layer. The thickness of the interlayer insulating layer 53 is, for example, 450
Å.

Further, a polycrystalline silicon layer 54 is formed on the interlayer insulating layer 53, and is doped with phosphorus. This polycrystalline silicon layer 54 is a portion to be the upper electrode of the capacitor. The formation conditions may be the same as the formation conditions of the polycrystalline silicon layer 52.

Next, as shown in FIG. 1B, a resist 56 is formed on a portion to be an upper electrode of the capacitor.
The polycrystalline silicon layer 54 is etched.

Next, after removing the resist 56, FIG.
As shown in FIG. 2C, the silicon oxide layer 57 formed by thermal decomposition of TEOS (tetraethoxysilane)
A third insulating layer is formed to a thickness of 0 °. The silicon oxide layer 57 as the third insulating layer only needs to have a sufficiently high etching selectivity with respect to the polycrystalline silicon layer 52, and may be, for example, silicon nitride instead of the silicon oxide layer 57.

Further, a resist 58 is formed on a portion of the polycrystalline silicon layer 52 which is to be a lower electrode of the capacitor on the silicon oxide layer 57, and the silicon oxide layer 57 and the interlayer insulating layer 53 are etched.
8 is removed, and a first mask body 57 is formed as shown in FIG. The first mask body 57 is attached so as to cover the upper surface and the side surface of the second polycrystalline silicon layer serving as the upper electrode layer. This first mask body 57 is
The metal silicide layer 59 as will be described later in conjunction with a mask for etching, thereby preventing the contamination by metal particles flying in etching the metal silicide layer 59. Further, it plays a role of preventing a short circuit between the upper electrode and the lower electrode. Although not shown, the first mask body 57, that is, the silicon oxide layer 57 is selectively left above the portion of the first polycrystalline silicon layer 52 which will be a resistance element, thereby increasing the resistance of the portion. Resistance element.

Next, as shown in FIG. 1E, a tungsten silicide layer 59 is formed, for example, at 2000.degree.
Further, the polysilicon layer 52 and the tungsten silicon
A resist 60 serving as a second mask body is formed in a portion where a stacked structure with the doped layer 59 is to be formed, and tungsten silicide and polycrystalline silicon are etched using a plasma etching method. At this time, the portion of the resist 60 is not etched, and the polysilicon layer 52 and the metal silicide layer are not etched.
59 and a laminated structure. This laminated structure becomes the gate electrode of the MOS transistor.

In the portion of the silicon oxide layer 57, the tungsten silicide layer 59 thereon is etched, but the polycrystalline silicon layer 5 below the silicon oxide layer 57 is etched.
2. The silicon oxide layer 57 functions as a mask for the interlayer insulating layer 53 and the polycrystalline silicon layer 54, and a capacitor composed of the polycrystalline silicon layers 52 and 54 and the interlayer insulating layer 53 can be formed. Further, the mask body 57 formed on the first polycrystalline silicon layer 52 serves as a high-resistance region where tungsten silicide is not deposited, and can be used as a resistance element.

Next, using the gate electrode as a mask, impurities are diffused into the active region to form source / drain diffusion layers (see FIG. 1F).

In the thus obtained capacitor according to this embodiment, the interlayer insulating layer 53 has another layer, for example, a gate.
Since the gate oxide layer 55 may be formed separately, multi
It is possible to carry out under conditions suitable to oxidize crystalline silicon layer 52, the metal (W) for performing the silicide layer 59 formed previously can prevent contamination of the metal silicide layer 59, reliability of the interlayer insulating layer 53 .

[0041] In addition, the transistor has its gate part data
A laminated structure in which a ring stainless silicide layer 59 made of polycrystalline silicon layer 52 may be high-speed operation with low resistance, and the gate oxide layer 55 is Ya polycrystalline silicon layer 52
Since the metal (W) silicide layer 59 can be formed independently before being formed, a highly reliable gate oxide can be formed.
Layer 55 can be used.

As described above, according to the present embodiment, the gate
A second connection between the oxide layer 55 and the interlayer insulating layer 53 of the capacitor
Can be formed before forming the crystalline silicon layer 54 and the metal silicide layer 59, and since the first mask member 57 covers the upper and side surfaces of the upper electrode, a metal Shirisa
The contamination at the time of etching the id layer 59 can be prevented, and unnecessary etching of the upper electrode can be prevented.

In the present embodiment, the interlayer insulating layer 53 is formed by thermal oxidation, but may be formed by CVD. Embodiment 2 This embodiment corresponds almost directly to the method for manufacturing a semiconductor device of the present invention shown in FIG. However, in this embodiment, as a result of controlling the phosphorus doping amount in the first polycrystalline silicon layer 52 to a specific value, the sheet resistance value thereof is set to 30 to 1000.
Ω / □, preferably in the range of 35 to 1000 Ω / □, and performing the step of using the first polycrystalline silicon layer 52 as a lightly doped layer.
4 is different from the conventional method in that doping is performed after patterning.

The step of controlling the sheet resistance will be described. First, the first polycrystalline silicon layer 52 having a thickness of 3500.degree.
Is formed, the first polycrystalline silicon layer 52 is doped under specific conditions. This doping is performed, for example, by N2 gas (5 l / min), O2 gas (0.5 l / min) and POCl3 gas (120 mg / min).
Is introduced into a reaction chamber heated to a temperature of about 1000 ° C. for 4 minutes. According to this condition, the sheet resistance value of first polycrystalline silicon layer 52 can be controlled within the above-described specific range. In a polycrystalline silicon layer exhibiting a sheet resistance value in this specific range, no crystal grains are generated inside the layer even when it is exposed to heat during doping or heat in a subsequent heat process. Does not occur.

After the step of controlling the sheet resistance of the first polycrystalline silicon layer 52, as shown in FIG. 1B, the non-doped second polycrystalline silicon in which no impurity (dopant) is diffused is formed. A resist 56 is provided on the layer 54, and the second polycrystalline silicon layer 54 is patterned. At this time, the lower interlayer insulating layer 53 may be patterned. Next, except that the doping time is set to 9 minutes for the exposed surface of the first polycrystalline silicon layer 52 not covered by the second polycrystalline silicon layer 54 and the second polycrystalline silicon layer 54. The doping is performed under the same conditions as the doping in the sheet resistance value control step. By this step, the dopant (phosphorus) concentration of the already patterned second polycrystalline silicon layer 54 increases, and the second polycrystalline silicon layer 54 becomes a heavy doped layer. The exposed portion of the first polycrystalline silicon layer 52 that is not covered by the second polycrystalline silicon layer 54 has a high concentration exceeding the dopant (phosphorus) concentration before doping, which is also a heavy doped layer. Become. Subsequently, the portion of the first polycrystalline silicon layer 52 covered by the second polycrystalline silicon layer 54 becomes a lightly doped layer with the dopant (phosphorus) concentration before doping. continue,
1C to 1F, a semiconductor device having a target unit capacitor structure and a semiconductor having a gate electrode and a resistor is obtained.

In such a semiconductor device, the first polycrystalline silicon layer 52 surrounded by the above-mentioned heavy dope layer
In the part, the dopant concentration is maintained in a predetermined range, and the light-doped layer remains. The lightly-doped layer functions as a lower electrode of the capacitor, and the heavyly-doped layer above the lightly-doped layer functions as an upper electrode of the capacitor. Both doped layers form a unit capacitor via the interlayer insulating layer 53. A plurality of unit capacitors are assembled and C1 or C1 of the SCF in FIG.
2 is constituted. In the present embodiment, the sheet resistance of the lightly doped layer as the lower electrode of the capacitor is controlled within a specific range, and the surface thereof has no irregularities. It does not lower. Since the lightly doped layer with few irregularities on the surface is used for the unit capacitor as one electrode, its specific accuracy can be easily raised,
Eventually, the performance of the SCF can also be improved.

In the above embodiment, the patterned second
Although the doping time for making the polycrystalline silicon layer 54 a heavy dope layer was 9 minutes, the doping amount may be arbitrarily changed to 4 to 9 minutes. In this case, the patterned second polysilicon layer 54 does not become a heavy doped layer, but becomes a lightly doped layer similarly to the first polycrystalline silicon layer 52 in a lower portion thereof. However, even in this case, the portion adjacent to the first polycrystalline silicon layer 52 which is a lightly doped layer becomes a heavy doped layer because the impurity concentration becomes high. Also in this case, the first
The portion of the lightly doped layer in the polycrystalline silicon layer 52 functions as the lower electrode of the capacitor as in the case of the above embodiment.

It should be noted that also in this embodiment, not only the first polycrystalline silicon layer 52 but also the second polycrystalline silicon layer 54 can be doped for light doping. Further, in each of the above-described embodiments, since it can be manufactured using a conventional thin layer deposition technique, impurity diffusion technique, or the like, there is an effect that the mass productivity is excellent. Furthermore, in each of the above embodiments, phosphorus was used as the dopant, but the present invention is not limited to this.

[0049]

As described above, according to the present invention,
Excellent transistor with high-speed operation having a gate with a laminated structure of a polycrystalline silicon layer and a metal silicide layer, and excellent voltage coefficient using a polycrystalline silicon thermal oxide layer as an interlayer insulating layer and polycrystalline silicon as both electrodes. Capacitor formed. In addition, by forming a gate oxide layer of a transistor before introducing high-concentration impurities into polycrystalline silicon and forming an interlayer insulating layer of a capacitor before forming a metal silicide layer, contamination of impurities and metal silicide can be prevented. In addition to preventing the insulating layer, the oxidation of the gate oxide layer and the oxidation of the interlayer insulating layer can be performed separately,
The semiconductor device can be formed under oxidation conditions suitable for each of them, and a highly reliable semiconductor device can be provided.

Further, since the first mask body covers the upper surface and side surfaces of the upper electrode, it is possible to prevent contamination at the time of etching the metal silicide layer and to prevent unnecessary etching of the upper electrode. it can.

Further, in addition to the above-described transistor and capacitor, a single-layer structure of high-resistance polycrystalline silicon can be formed over the same substrate. Therefore, a capacitor having an excellent voltage coefficient, a resistance element requiring a high resistivity, and a gate portion and a wiring portion requiring high speed can be formed on the same substrate.

Further, since the sheet resistance of the lower electrode of the unit capacitor is controlled within the range of 30 to 1000 Ω / □, the performance of the SCF to which the present invention is applied is not reduced without lowering the specific accuracy of the unit capacitor. Can be improved. Further, when doping the second polycrystalline silicon layer, the resistance of the gate electrode and the resistor formed of the first polycrystalline silicon is also reduced. Therefore, according to the present invention, it is possible to maintain S
It is possible to improve the performance of CF.

Further, the present invention can be carried out while maintaining mass productivity because the doping of the first and second polycrystalline silicon layers is processed by the thermal diffusion method.

[Brief description of the drawings]

FIGS. 1A to 1F are process diagrams for explaining a first embodiment of a method of manufacturing a semiconductor device according to the present invention, wherein FIGS. 1A to 1F are schematic cross-sectional views showing the configuration of a semiconductor device after each process; It is.

FIG. 2 is a circuit diagram showing a configuration of a general SCF.

FIGS. 3A to 3H are process diagrams for explaining an example of a conventional method for manufacturing a semiconductor device, and FIGS. 3A to 3H are schematic cross-sectional views showing the configuration of the semiconductor device after each process.

FIGS. 4A to 4I are process diagrams illustrating an example of a conventional method for manufacturing a semiconductor device, and FIGS. 4A to 4I are schematic cross-sectional views showing the configuration of the semiconductor device after each process.

[Explanation of symbols]

 Reference Signs List 50 semiconductor substrate 51 field oxide layer 52 first polycrystalline silicon layer 53 interlayer insulating layer 55 gate oxide layer 54 second polycrystalline silicon layer 56 resist 57 first mask body (insulating layer, silicon oxide layer) 58 resist 59 Metal silicide layer 60 Second mask body (resist)

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-301554 (JP, A) JP-A-3-105981 (JP, A) JP-A-59-195859 (JP, A) JP-A-58-1985 159365 (JP, A) JP-A-63-177453 (JP, A) JP-A-59-163855 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/822 H01L 27 / 04

Claims (4)

(57) [Claims] Forming a field oxide layer and a gate oxide layer on a semiconductor substrate; depositing a first polycrystalline silicon layer; forming an insulating layer on the first polycrystalline silicon layer; Forming a second polycrystalline silicon layer on the layer,
Etching the second polycrystalline silicon layer and the insulating layer except for a portion to be an upper electrode layer of the capacitor, selectively applying a first mask body covering the upper electrode layer and side surfaces thereof; A metal sheet is applied over the entire surface of the laminate obtained above.
Forming a re-side layer, forming a second mask body in a portion to be a gate electrode of the MOS transistor, etching the first poly-silicon layer and the metal silicide layer, and forming a poly-silicon layer and a metal silicide layer. A method for manufacturing a semiconductor device, comprising forming a capacitor comprising a gate electrode having a laminated structure of the above, an electrode of a polycrystalline silicon layer, and an interlayer insulating layer of a silicon oxide layer. 2. A field oxide layer and a gate oxide layer are formed on a semiconductor substrate, a first polysilicon layer is deposited, and an insulating layer is formed on the first polysilicon layer. Forming a second polycrystalline silicon layer on the layer,
The second polycrystalline silicon layer and the insulating layer are etched except for the part to be the upper electrode layer of the capacitor, and cover the upper electrode layer and its side surfaces and the part of the single-layer polycrystalline silicon layer that becomes the resistor. A first mask body is selectively applied, and then a metal mask is applied over the entire surface of the laminate obtained above.
Forming a re-side layer, forming a second mask body in a portion to be a gate electrode of the MOS transistor, etching the first poly-silicon layer and the metal silicide layer, and forming a poly-silicon layer and a metal silicide layer. A method of manufacturing a semiconductor device, comprising forming a capacitor comprising a gate electrode having a laminated structure of the above, an electrode comprising a polycrystalline silicon layer and an interlayer insulating layer comprising a silicon oxide layer, and a resistor comprising a single layer of a polycrystalline silicon layer. . Forming a first polycrystalline silicon layer on an oxide layer formed on a semiconductor substrate; and diffusing an impurity into the first polycrystalline silicon layer to form the first polycrystalline silicon layer. The sheet resistance of the crystalline silicon layer is 30 to 10
A step of controlling the resistance within a range of 00Ω / □, and a step of forming a second polycrystalline silicon layer serving as an upper electrode of a capacitor on the first polycrystalline silicon layer after the sheet resistance control step via an insulating layer. Patterning the second polycrystalline silicon layer and the insulating layer to form an upper electrode of a unit capacitor; and forming the first polycrystalline silicon layer left as a mask using the first polycrystalline silicon layer as a mask. Is further diffused into the first polycrystalline silicon layer, thereby forming a first polycrystalline silicon layer below the second polycrystalline silicon layer and having a controlled sheet resistance. Increasing the impurity concentration of the portion other than the silicon layer; and forming a gate and a lower electrode of the unit capacitor by patterning the first polycrystalline silicon layer. The method of manufacturing a semiconductor device, which comprises. 4. A step of forming a first polycrystalline silicon layer on an oxide layer formed on a semiconductor substrate; and diffusing an impurity into the first polycrystalline silicon layer to form the first polycrystalline silicon layer. The sheet resistance of the crystalline silicon layer is 30 to 10
Controlling the first polycrystalline silicon layer to form a lower electrode of a gate and a capacitor; and controlling the first polycrystalline silicon layer to form a lower electrode of a gate and a capacitor.
Forming an interlayer insulating layer on the polycrystalline silicon layer, and then forming a second polycrystalline silicon layer serving as an upper electrode of the capacitor on the interlayer insulating layer; and forming the second polycrystalline silicon layer and the Patterning an interlayer insulating layer; and diffusing impurities into the second polycrystalline silicon layer to form a first polycrystalline silicon layer below the second polycrystalline silicon layer, the sheet resistance value being: Increasing the impurity concentration of the other portion except for the first polycrystalline silicon layer controlled by the above method.