KR100224560B1 - Analog-digital converter - Google Patents

Abstract

[0001] The present invention relates to an analog-to-digital converter (SAR) type analog-to-digital converter capable of performing analog-to-digital conversion at high speed, A digital-to-analog conversion means for outputting a voltage signal corresponding to a count value outputted from the counter means, and a digital-to-analog conversion means for outputting a voltage signal corresponding to the count value outputted from the counter means, And gate means for comparing the voltage value output from the digital-analog conversion means with the voltage value of the analog input signal and applying a clock signal to the counter means when the voltage value of the input signal is higher.

Description

Analog-to-digital converter

FIG. 1 is a circuit diagram showing a configuration of a conventional SAR-type analog-digital converter; FIG.

FIG. 2 is an operation timing diagram for explaining the operation of the analog-digital converter shown in FIG. 1; FIG.

FIG. 3 is a circuit diagram showing a configuration of an analog-digital converter according to an embodiment of the present invention; FIG.

FIG. 4 is a circuit diagram showing a detailed configuration of an initial value generating unit in FIG. 3; FIG.

FIG. 5 is an operation timing diagram for explaining the operation of the analog-digital converter shown in FIG. 4; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

1: Counter 2: Digital-to-Analog Converter

3: latch circuit 4: controller

31: initial value generating unit 32: counter

33: Controller 41: Encoder

42: ROM table CP1, CP4 _{1 to} CP4 ₁₆ : comparator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-digital converter for converting an analog signal into digital data, and more particularly to a successive approximation register (SAR) type analog-digital converter capable of performing data conversion at high speed.

[0002] Recently, with the rapid development of electronic technology, the signal processing method has gradually been digitized in the electronic and communication fields. Accordingly, analog-digital converters for converting analog signals into digital data have been widely used.

FIG. 1 shows the configuration of a SAR-type analog-digital converter as a conventional analog-digital converter.

Referring to FIG. 1, reference numeral CP1 denotes an input / output terminal connected to the non-inverting terminal (+) and an inverting terminal (-) to which the output voltage from the digital- And outputs a high level comparison signal when the level of the input analog signal IN is higher than the voltage level of the inverting terminal (-) side thereof. The AND circuit outputs a high-level comparison signal And outputs an input clock signal CLK to the counter 1 at the subsequent stage.

Reference numeral 1 denotes a counter for counting the number of times the clock signal CLK is input, 2) converts the 8-bit digital data (Q0 to Q7) output from the counter 2 into a voltage level signal corresponding to the data value, - analog converter, 3 is a latch signal ( Latches the output data (Q0 to Q7) of the counter 2 and outputs the same.

Reference numeral 4 denotes a controller for controlling the analog-to-digital conversion operation. When the conversion start signal CS is inputted from the outside, the counter 1 outputs a clear signal ( ), And clears the counter 1 to start the analog-to-digital conversion, and a busy signal (" When a low-level comparison signal is output from the comparator CP1, the latch circuit 3 outputs a latch signal ), Latches the 8-bit data (Q0 to Q7) output from the counter 1, and outputs a conversion completion signal ) To indicate that the analog-to-digital conversion has ended.

Next, the operation of the apparatus having the above-described configuration will be described in detail with reference to a timing chart shown in FIG.

First, a conversion start signal ( , The controller 4 outputs a clear signal (" 1 ") to the counter 1 ) To reset the counter 1.

Therefore, at this time, the output data (Q0 to Q7) of the counter 1 is set to 0000 0000 and the data is outputted to the comparator CP1 through the digital-analog converter 2, And a voltage signal of 0 level is applied to (-).

The comparator CP1 outputs a high-level comparison signal when a predetermined level of the analog signal IN is input as a voltage signal of 0 level is applied to the inverting terminal (-) of the comparator CP1. The clock signal CLK is applied to the counter 1 through the AND gate AND as the clock signal CLK is input to one terminal of the AND gate AND.

When the clock signal CLK is input to the counter 1 as described above, the counter 1 counts the input clock signal CLK and outputs data corresponding to the counted value to the output terminals Q0 through Q7 . At this time, the output of the count value data is converted into a level signal corresponding to the count value through the digital-to-analog converter 2, and is then applied to the inverting terminal (-) side of the comparator CP1. Therefore, in the comparator CP1, the count value of the counter 1, that is, the output of the digital-analog converter 2 corresponding to the count value is equal to or larger than the input signal IN, A signal is output.

Next, when the count value of the counter 1 rises and the voltage level input to the inverting terminal (-) side of the comparator CP1 becomes equal to or larger than the level of the input signal IN, The output signal from the counter circuit CP1 drops to a low level and the clock signal CLK input to the counter 1 through the AND gate is blocked by this low level output, The operation is stopped.

When the output level of the comparator CP1 drops to a low level, the controller 4 outputs a latch signal (" 1 ") to the latch circuit 3 ), Latches the data (Q0 to Q7) output from the counter 1 at this time, and outputs a conversion completion signal ) To complete the analog-to-digital conversion operation for one input signal.

Therefore, according to the above-described conventional analog-digital converter, it is possible to perform digital conversion on the analog input signal with a relatively simple configuration.

However, in the above-described conventional analog-to-digital converter, the counter 1 must perform the counting operation until a count value corresponding to the level of the input signal IN is obtained, so that the analog input signal IN is converted into digital data There is a problem that it takes a lot of time.

Accordingly, it is an object of the present invention to provide an analog-to-digital converter capable of performing analog-to-digital conversion at high speed.

According to an aspect of the present invention, there is provided an analog-to-digital converter comprising: initial value generating means for outputting digital data approximating a level of an analog input signal; Digital-to-analog conversion means for outputting a voltage signal corresponding to the count value outputted from the counter means, and a comparator for comparing the voltage value outputted from the digital-analog conversion means with the voltage value of the analog input signal And gate means for applying a clock signal to the counter means when the voltage value of the embroidery signal is higher.

The initial value generating means may include a plurality of comparison means for comparing the analog input signal with different predetermined reference voltages, encoding means for encoding the comparison signal output from the comparison means, To the initial value data of the counter means.

According to the present invention configured as described above, digital data approximate to the input signal is generated by the initial value generating means, and the counter means stores the digital data generated by the initial value generating means as the initial value, The counted value of the clock signal is counted.

Therefore, since the counting time of the counter means is reduced, the overall analog-digital conversion time is greatly shortened.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram of an analog-digital converter according to an embodiment of the present invention. In FIG. 3, the same reference numerals as in FIG.

In FIG. 3, reference numeral 31 denotes an output enable signal (an output enable signal) from the controller 33 Is an initial value generator for outputting digital data near to the level of an input analog signal IN, (DATA) applied from the initial value generator 32 at the time of input of the clock signal CLK.

Reference numeral 33 denotes a controller for controlling the analog-to-digital conversion, which, in addition to the operation in the above-described FIG. 1, ) Is input to the initial value generation unit 31, the output enable signal ( ) To the counter 32 and outputs the load signal ( To load the 8-bit data output from the initial value generator 31 as the count initial value of the counter 32.

FIG. 4 is a circuit configuration showing a detailed configuration of the initial value generating unit 31. In this case, the analog input voltage IN is compared with a different predetermined reference level, and when the input voltage is higher than the reference level, comparison of the comparator 16 for outputting a signal (CP4 ₁ ~CP4 ₁₆₎ and, a comparator (CP4 ₁ ~CP4 ₁₆₎ receives the output of the encoding and outputting it as a 4-bit data 16: 4 encoder 41, And a ROM table 42 for outputting 8-bit data corresponding to the address of the output data of the encoder 41 as an address.

That is, in the above configuration, the analog input signal is applied to the non-inverting terminal (+) of each of the comparators CP4 _{1 to} CP4 ₁₆ . A plurality of resistors R are connected in series between the reference voltage V _REF and the ground and the inverting terminals (-) of the comparators CP4 _{1 to} CP ₁₆ are connected to the connection nodes of the resistors R , Where the resistors R are all set to the same value. Thus, while going toward the respective comparator (CP4 ₁ ~CP4 ₁₆₎ includes a comparator (CP4 ₁₎ from the comparator (CP4 ₁₆₎ side of the reference voltage is set to be high will have a level difference between a constant value.

And, a 16-bit data output from said comparator (CP4 ₁ ~CP4 ₁₆₎ 16: is output as 4-bit data is encoded by the encoder 4 (41), ROM table 42 in the 4-bit inputs (A0 To A3) and outputs 8-bit data (D0 to D7) corresponding thereto as the coefficient initial value of the counter 32 described above.

Table 1 below shows an example of the data configuration of the ROM table.

[Table 1]

Next, the operation of the apparatus having the above-described configuration will be described with reference to a timing chart shown in FIG.

A conversion start signal ( ) Is input, that is, the conversion start signal The controller 33 outputs a clear signal (" 1 ") to the counter 32 ) To output the output enable signal (" 0 ") to the initial value generator 31 And outputs a load signal (< RTI ID = 0.0 > ).

8, the 8-bit data D0 to D7 approximating the level of the input signal GH (IN) are output at the initial value generator 31 as described in FIG. 4, and the output data D0- D7 are loaded as initial coefficients of the counter 32.

When the output data Q0 to Q7 corresponding to the counted value of the counter 32 are applied to the comparator CP1 through the digital-analog converter 2 and the output of the comparator CP1 becomes high level, The clock signal CLK is applied to the counter 32 through the AND circuit 32 and the counter 32 performs the counting operation from the loaded initial value and outputs the counted value through the digital-analog converter 2 .

If the above operation is continued and the voltage value output from the analog-digital converter 2 becomes larger than the level of the input signal IN, as shown in FIG. 5, the output of the comparator CP1 becomes low level The controller 33 controls the latch circuit 3 in the same manner as the above-described conventional operation, Latches the digital data (Q0 to Q7) corresponding to the level of the input signal IN outputted from the counter 32 and outputs a conversion completion signal ), Thereby ending the analog-digital conversion processing.

Therefore, according to the embodiment, the counting operation of the counter 32 starts from a value approximate to the level of the input signal IN without starting from the 0 level, so that the overall analog-to-digital conversion speed is significantly improved do.

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the technical spirit of the present invention. For example, in the above embodiment, the initial value generator 31 is configured to use ₁₆ comparators (CP4 _{1 to} CP4 ₁₆ ) to calculate an approximate data value of the input signal IN. However, Is not particularly limited and may be arbitrarily set in accordance with the system in which the present invention is employed.

INDUSTRIAL APPLICABILITY As described above, according to the present invention, it is possible to realize an analog-digital converter capable of performing analog-digital conversion at a high speed while reducing manufacturing cost.

Claims (5)

An initial value generating means for outputting digital data approximating the level of an analog input signal, a counter means for counting a clock signal applied with the data output from the initial value generating means as an initial value, Analog conversion means for comparing the voltage value outputted from the digital-analog conversion means with the voltage value of the analog input signal and for outputting a clock signal to the counter means when the voltage value of the input signal is higher than the voltage value outputted from the digital- And an analog-to-digital converter. 2. The apparatus as claimed in claim 1, wherein the initial value generating means comprises at least two comparing means for comparing the analog input signal with different predetermined reference voltages, and a comparing means for comparing the comparison signal outputted from the comparing means with the initial value data And an analog-to-digital converter for converting the analog signal into digital data. 2. The apparatus according to claim 1, wherein the initial value generating means comprises: a plurality of comparing means for comparing the analog input signal with a different predetermined reference voltage; encoding means for encoding a comparison signal output from the comparing means; And data conversion means for converting the output data into initial value data of the counter means. 4. The analog-digital converter according to claim 3, wherein the data conversion means comprises a ROM table. The analog-digital converter according to claim 3 or 4, wherein the output data of the encoding means is address data of the ROM table.