DE19722805A1 - Successive approximation register A=D converter for communication electronics - Google Patents

Abstract

The converter includes input signals (IN) converted into corresponding digital data, transmitted by a start value generator (31). A counter (32) processes applied clock pulse signals with a start value of the transmitted data. A D-A converter (2) transmits a voltage signal, corresponding to a value delivered by the counter. A gate (AND1) compares the level of the analog input signal with a reference value delivered by the D-A converter, and applies a clock pulse signal to the counter when the analog input signal level is higher than the reference value.

Description

The present invention relates to analog / digital converters for Convert analog signals to digital data, and in particular an analog / digital converter of the SAR type (successive approxi mation register), which is able to store data with high To change speed.

With today's quantum leaps in electronic technologies are methods of processing signals digitally, namely especially in the field of electronics or communications technology nik. This results in analog / digital (A / D) converters for converting analog signals into digital data widely for most electronic devices or communication devices used.

Fig. 1 shows the structure of a conventional A / D converter of the SAR type.

In Fig. 1, reference character "CP1" represents a comparator whose non-inverting input (+) is connected to an analog input signal IN from an external device (not shown) and whose inverting input (-) is connected to an output signal from a later to be described Digi tal / analog (D / A) converter 2 is connected.

The comparator CP1 outputs an output signal with an H level when a level of the signal applied to the non-inverting input (+) is higher than that of the signal applied to the inverting input (-). Accordingly, the comparator CP1 outputs the signal with the H level until the level of the signal applied by the D / A converter 2 is greater than that of the analog input signal IN.

In the meantime, an output signal of the comparator CP1 into an input port of an AND gate AND1 with two inputs entered, and a clock signal CLK1 with a predetermined Frequency is in the other input port of the AND gate AND1 entered. Thus, the AND gate AND1 gives the clock signal CLK1 off when a signal with an H level from the comparator CP1 is given.

A counter 1 counts the number of clock pulses which are input to a clock input port CLK and outputs a count as 8-bit data Q0-Q7. When a clear signal CLR is input, the counter 1 is reset to the initial value "0".

The output signal of the AND gate AND1 is connected to the clock input port CLK of the counter 1 . Therefore, the counter 1 counts the number of clock pulses which are input via the AND gate AND1 and accordingly outputs 8-bit count data Q0-Q7.

A digital-to-analog converter 2 converts the 8-bit digital data Q0-Q7 output from the counter 1 into a voltage level signal corresponding to a data value thereof. A latch circuit 3 holds the 8-bit data Q0-Q7 from the counter 1 when a latch signal LA is input and outputs it.

A controller 4 controls the analog / digital conversion. That is, the controller 4 when a conversion start signal CS is input from an external device, a signal CLR outputs it to the counter 1, to clear the counter 1, so as to initiate the A / D conversion and that simultaneously outputs a busy signal BUSY, which indicates that the A / D conversion is currently being carried out. Also, when an output level of the comparator CP1 goes to an L level, the controller 4 outputs the signal LA to the latch circuit 3 to hold the 8-bit data Q0-Q7 output from the counter 1 , and also outputs a conversion completion signal CC to indicate completion of the A / D conversion.

The operation of the conventional A / D converter having the above structure will now be described with reference to FIG. 2.

When the conversion start signal CS is input from the external device, the controller 4 outputs the clear signal CLR to the counter 1 , so that the counter 1 is reset.

Accordingly, the output data Q0-Q7 of the counter 1 is set to "0000 0000", and the data is applied to the comparator CP1 via the digital / analog converter 2 , so that a voltage signal of a "0 level" is applied to the inverting input (-) of the comparator CP1 is created.

In the comparator CP1, where a voltage signal with a "0 level" is applied to the inverting input (-) and an analog input signal IN is not applied with a "0 level" to the non-inverting input (+), a Output signal of the comparator CP1 set to an "H level". The H-level signal is applied to one port of the AND gate AND1, and thus the input clock signal CLK1 is applied to the counter 1 through the AND gate AND1 at the same time.

When the clock signal CLK1 is applied to a clock input port CLK of the counter as shown above, the counter 1 counts the number of clock pulses and outputs the 8-bit data according to the count value via the output port Q0-Q7. Here, the count data, which is output from the counter 1 , applied to the digital / analog converter 2 and converted into a level signal corresponding to the count value. The level signal is also applied to the inverting input (-) of the comparator CP1. Thus, a comparison signal with an H level is output from the comparator CP1 until the count value of the counter 1 , ie an output voltage from the digital / analog converter 2 , corresponding to the count value is equal to or greater than the analog input signal IN.

Next, when the count increases by the counter 1 , when the input voltage level from the inverting input (-) of the comparator CP1 becomes equal to or higher than the level of the analog input signal IN, the equalizing signal from the comparator CP1 becomes an L level- Signal as shown in Fig. 2. Accordingly, the input clock signal CLK1, which is input through the AND gate AND1, is blocked, and the counting of the counter 1 stops.

Also, when the output level of the comparator CP1 becomes an L level, the controller 4 outputs the signal LA to the hold circuit 3 for holding the data Q0-Q7 output from the counter 1 at this point and also ends the A / D conversion on an input signal by outputting the conversion completion signal CC to the outside.

As a result, the usual A / D converter with a relatively simplified structure, as shown above, a change from analog input signals to digital signals.

However, since in the conventional A / D converter, counting by the counter 1 should continue until a count value corresponding to the level of the analog input signal IN is obtained, much time is required to convert the analog input signal IN to digital data.

To solve the above problem, it is the task of the present one Invention to provide an analog to digital converter, which perform an analog / digital conversion at high speed can lead.  

This object is achieved by the claim 1 specified analog / digital converter solved, i.e. by a Analog / digital converter, which input signals in corresponding digital data converts, the analog / digi tal converter has: an initial value generator for output of digital data is approximately equal to a level of the analog Input signal; a counter for counting applied clock signals at an initial value that is output by the initial value generator level data; a digital / analog converter for outputting a Voltage signal corresponding to one output from the counter Count value; and a gate for comparing a level of the ana Lied input signal with one of the digital / analog converter output reference value and application of a clock signal to the Counter if the level of the analog input signal is greater than is the reference value.

Preferred developments are the subject of the dependent claims.

According to a preferred development, the initial value contains generator a variety of comparators to compare the analog input signal with a predetermined reference span tion, which are different from each other, and an encoder for coding a comparison output by the comparator signals and a data converter for converting those from the encoder output data in initial value data of the counter.

According to the present invention having the above structure digital data approximately equal to an input signal through the Initial value generator is generated and the counter counts clock pulses using those generated by the initial value generator digital data as an initial value.

Therefore, for analog / digital conversion as a whole required time due to the reduction of the counting time of the count be drastically reduced.

In the following, the present invention will be explained based on an off management example with reference to the accompanying drawings gene explained in more detail.

Show it:

Fig. 1 is a circuit diagram showing a configuration of a conventional A / D converter of the SAR type;

FIG. 2 is a timing chart for explaining an operation of the A / D converter shown in FIG. 1;

Fig. 3 is a circuit diagram showing a configuration approximate shape of an A / D converter of the SAR type according to an exporting may convert to the present invention, which data at high speed;

Fig. 4 is a circuit diagram showing a detailed configuration of the initial value generator shown in Fig. 3; and

FIG. 5 is a timing chart for explaining an operation of the A / D converter shown in FIG. 4.

In Fig. 3, the elements shown in Fig. 1 have the same reference numerals, and a detailed description thereof is omitted.

With reference to FIG. 3, reference numeral 31 represents an initial value generator for outputting digital data approximately equal to a level of an analog input signal IN when an output activation signal OE is applied by a controller 33 to be described later. The outputted digital data of the initial value generator 31 are connected to a data input port DATA of a counter and load in the counter 32 an initial count value by a load signal LOAD.

In any case, reference numeral 33 designates its own controller for the analog / digital conversion. As described with reference to FIG. 1, the controller 33 , when a conversion start signal CS is input from the external device, outputs an output activation signal OE to the initial value generator 31 and the load signal LOAD to the counter 32 , so that 8 bits Data which is output from the initial value generator 31 is loaded as the initial count value of the counter 32 .

Fig. 4 shows in detail the structure of the initial value generator 31.

The initial value generator 31 contains 16 comparators CP4₁-CP4₁₆ for comparing the analog input signal IN with a respective predetermined reference level, which differ from one another, and for outputting a comparison signal with an "H level" when the analog input signal IN is greater than the reference level , a 16: 4 encoder 41 for encoding and outputting the received output signal of the comparators CP4₁-CP4₁₆ in 4-bit data and a ROM table 42 for outputting 8-bit data corresponding to an address of the output data of the encoder 41st

That is, analog input signals are input to each non-inverting input (+) of the respective comparators CP4₁-CP4₁₆. A plurality of resistors R1-R16 are connected in series between a predetermined reference voltage V _F and Mas se, and each inverting input (-) of the respective comparators CP4₁-CP4₁₆ is connected to a corresponding connection node of the resistors R1-R16. The resistors R1-R16 are set to the same value. Thus, the reference voltage with a level difference having a uniform value becomes higher if one goes from the comparator CP4₁₆ to the comparator CP4₁.

A 16-bit data output signal from the comparators CP4₁-CP4₁₆ is encoded and output in 4-bit data by the 16: 4 encoder 41 . The ROM table 42 uses a 4-bit input signal A0-A3 as an address and outputs 8-bit data D0-D7 for an initial count value of the counter 32 .

Table 1 below shows an example of the data configuration ration of the ROM table.  

Table 1

The operation of the above converter having the structure described above will now be described with reference to FIG. 5.

When the conversion start signal CS is input from the external device, that is, when the conversion start signal CS assumes an "active-L" state, the controller 33 outputs the clear signal CLR to the counter 32 to clear the counter 32 . The controller 33 outputs the output activation signal OE to the initial value generator 31 and also outputs the load signal LOAD to the counter 32 .

Here, as shown in FIG. 4, the initial value generator 31 outputs the 8-bit data D0-D7 approximately equal to the level of the analog input signal IN, and the output data D0-D7 are loaded into the counter 32 as an initial count value.

Next, the output data Q0-Q7 corresponding to the count value of the counter 32 are applied to the comparator CP1 through the D / A converter 2 . The data value of the ROM table 42 is set such that the signal level applied to the comparator CP1 by the D / A converter 2 is not greater than the analog input signal IN.

In the meantime, when the output of CP1 is high, the clock signal CLK1 is applied to the counter 32 through the AND gate AND1, and the counter 32 performs counting with the loaded initial value to increase the count value through the D / A converter 2 output.

When the above operation runs so long that the voltage value output from the D / A converter 2 becomes larger than the level of the analog input signal IN, the output signal of the comparator CP1 assumes an L level as shown in FIG. 5 . Here, the controller 33 outputs the hold signal LA to the hold circuit 3 for holding the digital data (Q0-Q7) output from the comparator 32 according to the level of the analog input signal IN, and at the same time outputs the conversion completion signal CC to the external devices so as to end the analog / digital conversion.

Since in the preferred embodiment the counting operation of the counter 32 does not start from the level "0", but from an initial value approximately equal to the level of the analog input signal IN, the speed of the analog / digital conversion is drastically improved.

Therefore, it should be understood that the present invention is not limited to the particular embodiment disclosed herein which is considered the best mode for carrying out the present invention, the present invention is not limited to the particular embodiments described in this specification, but rather by the attached patent claims. For example, in the above embodiment, the number of comparators in the initial value generator 31 is sixteen (CP4₁-CP4₁₆) to calculate the data approximately equal to the analog input signal IN, but is not limited to this, and can thus be arbitrarily set according to the requirements of a system which uses the present invention.

Also in the above embodiment, after the output of the comparators CP4₁-CP4₁4 is encoded by the encoder 41 in the initial value generator 31 , the encoding data is used as the address data of the ROM table 42 . However, the outputs of the comparators can be used as the address data of the ROM table 42 by appropriately setting the number of comparators.

As described above, the A / D converter can be as shown in FIG the invention an analog / digital conversion at high speed realizing.

Claims (5)

1. Analog / digital converter for converting input signals (IN) into corresponding digital data, which has:
initial value generating means ( 31 ) for outputting digital data approximately equal to a level of the analog input signal (IN);
counter means ( 32 ) for counting applied clock signals with an initial value of the data output from the initial value generating means ( 31 );
a digital / analog conversion device ( 2 ) for outputting a voltage signal corresponding to a count value output by the counter device ( 32 ); and
a gate device (AND1) for comparing a level of the analog input signal (IN) with a reference value output by the digital tal / analog converting device ( 2 ) and for applying a clock signal to the counter device ( 32 ) when the level of the analog Input signals (IN) is greater than the reference value. 2. Analog / digital converter according to claim 1, characterized in that the initial value generating device ( 31 ) has:
at least two comparison devices (CP4₁-CP4₁₆) for comparing the analog input signal (IN) with a respective predetermined reference voltage, which are different from one another; and
a data conversion device ( 41 , 42 ) for converting a comparison signal output by the comparison devices (CP4₁-CP4₁₆) into initial value data of the counter device ( 32 ). 3. Analog / digital converter according to claim 2, characterized in that the data conversion device ( 41 , 42 ) has a ROM table ( 42 ). 4. Analog / digital converter according to claim 1, characterized in that the initial value generating device ( 31 ) has:
a plurality of comparison means (CP4₁-CP4₁₆) for comparing the analog input signal (IN) with a respective predetermined reference voltage which are different from each other;
encoding means ( 41 ) for encoding a comparison signal output from the comparison means (CP4₁-CP4₁₆); and
a data conversion device ( 42 ) for converting the data output by the encoder device ( 41 ) into initial value data of the counter device ( 32 ). 5. Analog / digital converter according to claim 4, characterized in that the data conversion device ( 42 ) has a ROM table ( 42 ).