FR2749456A1 - ANALOGUE-DIGITAL CONVERTER WITH SUCCESSIVE APPROXIMATIONS REGISTER THAT CAN CONVERT DATA AT HIGH SPEED - Google Patents

Abstract

The present invention relates to an analog-to-digital converter of the successive approximation register type. The converter is characterized in that it comprises an initial value generating means (31); counting means (32) for counting clock signals applied with an initial value of data produced by the generating means (31); a digital to analog converter (32) producing a voltage signal corresponding to a count value produced by the counting means (32) and gate means for applying a clock signal to the counting means (32) when the level of the analog signal IN is greater than the reference value. The invention finds application in the field of communications.

Description

The present invention relates to an analog-to-digital converter for

  converting analog signals into digital data and more particularly a RAS (successive approximation register) analog-to-digital converter capable of converting data to

high speed.

  Concurrently with quantum advances in electronic technologies, a process for processing signals allows for digitization especially in the field of electronics or communications engineering. As a result, an analog to digital (A / D) converter for converting analog signals to digital data is widely used in most devices or

  electronic communication devices.

  Figure 1 shows a configuration of a

  A / D converter of the conventional RAS type.

  In FIG. 1, the reference symbol "CP1" represents a comparator whose port or non-inversion input (+) is connected to the analog input signal IN from an external device (not represented) and whose port or inverting input (-) is connected to an output of a converter

  digital-analogue (N / A) 2 to be described later.

  The comparator CP1 produces a high level signal when a signal level applied to the non-inversion port (+) is greater than that of the signal applied to the inverting port (-). As a result, the comparator CP1 continues to produce the high level signal until the level of the signal applied by the D / A converter 2 is greater than

  that of the analog input signal IN.

  At the same time, an output of the comparator CP1 is applied to an input port of a two-input AND gate AND1 and a CLK1 clock signal having a predetermined frequency is applied to the other input port of the AND gate ET1. Thus, the AND gate ET1 produces a clock signal CLK1 when a signal of a high level is produced.

by the comparator CP1.

  A counter 1 counts the number of clock pulses applied to an input port of clock signals CLK and

  produces a count value in 8 bit data Q0 - Q7.

  When an erase signal CLR is applied, the counter 1 is reset to the initial value "0". The output of the AND gate ET1 is coupled to the input port of the clock signal CLK of the counter 1. Thus, the counter 1 counts the number of clock signals applied by the AND gate ET1 and thus produces data. of

counting 8 bits Q0 - Q7.

  A digital-to-analog converter 2 converts the 8-bit digital data Q0-Q7 produced by the counter 1 into a voltage level signal corresponding to a data value thereof. A latch circuit 3 locks and produces the 8-bit data Q0-Q7 of the counter

  1 when an LA lock signal is applied.

  A controller 4 controls an analog conversion-

  digital. That is, when a start-up signal CS is applied from the external device, the controller 4 produces a signal CLR at the counter 1 to clear the counter 1, thereby initiating the conversion A / N and concurrently produces an OCC busy signal which indicates that the A / D conversion is currently being performed. Also, when an output level of the comparator CP1 goes to a low level, the controller 4 produces the signal LA to the latch circuit 3 to lock the 8-bit data Q0-Q7 produced by the counter 1 and also produce a complete signal of

  CC conversion to indicate the end of the A / D conversion.

  The operation of the RAS type A / D converter having the above structure will now be described in

reference to Figure 2.

  When the conversion start signal CS is applied by the external device, the controller 4 produces the erase signal CLR at the counter 1 so that the

counter is reset.

  As a result, the output data Q0-Q7 of the counter 1 is set to "0000 0000" and the data is applied to the comparator CP1 via the digital-to-analog converter 2 so that a voltage level signal " 0 "is applied to the inversion port (-) of the

CP1 comparator.

  In the comparator CP1, when a level voltage signal "0" is applied to the inverting port (-) and an analog input signal IN having no level "0" is applied to the non-inverting port (+), an output of the comparator CP1 is set high. The high level signal is applied to a port of the AND gate AND1 and thus the input clock signal CLK1 is applied to the counter 1 via the AND gate ET1 at the same time.

time.

  When the clock signal CLK1 is applied to a clock input port CLK of the counter 1 as above, the counter 1 counts the number of clock pulses and the 8-bit data corresponding to the value of counting through output port Q0-Q7. Here, the count data that is produced by the counter 1 is applied to the digital-to-analog converter 2 and converted to a digital

  level signal corresponding to the count value.

  Also, the level signal is applied to the inverting port (-) of the comparator CP1. Thus, a comparison signal of a high level is produced by the comparator

  CP1 until the count value of the counter, that is,

  that is, an output voltage of the digital converter-

  analog 2 corresponding to the count value,

  equal to or greater than the analog input signal IN.

  Then, as the count value by the counter 1 increases, when an input voltage signal for the inverting port (-) of the comparator CP1 becomes equal to or greater than the level of the analog input signal IN, the signal The output of the comparator CP1 becomes a low signal as shown in FIG. 2. As a result, the input clock signal CLK1 which is applied by AND gate ET1 is blocked.

  and counting of counter 1 stops.

  Also, when the output level of the comparator CP1 becomes a low level, the controller 4 outputs the signal LA to the latch circuit 3 to latch the Q0-Q7 data produced by the counter 1 at this point and also terminates the A / D conversion. with respect to an input signal by outputting the DC conversion completion signal to the outside. As a result, the conventional A / D converter having a relatively simplified structure as above can perform analog input signal conversion.

in digital signals.

  However, in the conventional A / D converter since the count must continue through the counter 1 until a count value corresponding to the level of the analog input signal IN is obtained, it requires a lot of time to convert the signal. IN analog input

digital data.

  To overcome the above problem, it is an object of the present invention to provide an analog-to-digital converter that can accomplish a conversion.

  high speed analog-digital

  Therefore, for the above object, there is provided an analog-to-digital converter which converts input signals applied to digital data correspondingly, the analog-to-digital converter being characterized in that it comprises: a generator initial value to produce digital data approximating a level of the analog input signal; a counter for counting applied clock signals with an initial value of the data produced by the initial value generator, a digital-to-analog converter for producing a voltage signal corresponding to a count value produced by the counter, and a gate for comparing a level of the analog input signal to a reference value produced by the digital-to-analog converter and applying a clock signal to the counter when the level of the analog input signal is greater than the

reference value.

  The initial value generator also comprises a number of comparators for comparing the analog input signal with a different predetermined reference voltage for each of them, an encoder for encoding a comparison signal produced by the comparator and a data converter. to convert produced data

  by the encoder in initial value data of the counter.

  According to the present invention having the structure

  thereon, digital data approximating an input signal is generated by the initial value generator and the counter counts clock pulses using the digital data produced by the value generator

initial value.

  As a result, the overall time required to perform an analog-to-digital conversion can be drastically reduced because of the reduction in the counting time of the

counter.

  The invention will be better understood and other purposes, features, details and advantages thereof

  will become clearer during the description

  explanatory text which will follow with reference to the accompanying schematic drawings given solely by way of example illustrating an embodiment of the invention and in which: - Figure 1 is a circuit diagram showing a configuration of an A / D converter; conventional type

RAS;

  FIG. 2 is a timing diagram for explaining the operation of the A / D converter shown in FIG. 1; Fig. 3 is a circuit diagram showing a configuration of the RAS type A / D converter according to an embodiment of the present invention which can convert data at high speed; FIG. 4 is a circuit diagram showing a detailed configuration of the initial value generator shown in FIG. 3; and FIG. 5 is a timing diagram for explaining the operation of the A / D converter represented in FIG. 4. In FIG. 3, the elements represented in FIG.

  the same reference numbers and a detailed description

of these will be omitted.

  Referring to Fig. 3, reference numeral 31 represents an initial value generator for producing digital data approximating a level of an analog input signal IN when an OE output enable signal is applied by a controller 33 described later. The digital output data of the initial value generator 31 is coupled to a data input port of a counter and loads into the counter 32 into an initial count value thereof.

by a CHARGE charge signal.

  Also, reference numeral 33 represents a controller for analog-to-digital conversion. As described with reference to FIG. 1, when a start-up signal CS is applied by the external device, the controller 33 produces an output enable signal OE at the initial value generator 31 and the load signal CHARGE at counter 32 so that the 8-bit data produced by the initial value generator 31 are

  loaded as the initial count value of counter 32.

  Figure 4 details a configuration of the generator of

initial value 31.

  The initial value generator 31 comprises 16 comparators CP41-CP416 for comparing an analog input signal IN with each predetermined reference level different from each of them and producing a high level comparison signal when the input signal analog IN is above the reference level, a 16: 4 encoder 41 for encoding and outputting the output received from comparators CP41-CP416 into 4-bit data and a ROM table 42 to produce 8-bit data corresponding to a

  address of the output data of the encoder 41.

  That is, analog input signals are applied to each non-inverting port (+) of respective comparators CP41-CP416. A number of resistors R1-R16 are connected in series between a predetermined reference voltage VREF and the ground and each inverting port (-) of the respective comparators CP41-CP416 is connected to the respective connection nodes of the resistors R1-R16. Here, resistors R1-R16 are set as the same initial value. Thus, the reference voltage becomes higher with a level difference of a uniform value as

  it passes from the comparator CP416 to the comparator CP41.

  The 16-bit data produced by the comparators CP41-CP416 are encoded and produced in 4-bit data by the 16: 4 encoder 41. The ROM table 42 uses 4-bit A0-A3 inputs as an address and product. 8-bit data DO-D7 for an initial counting value of the counter 32. The following table 1 represents an example of

  data configuration of the ROM table.

Table 1.

  Encoder output 41 Data produced Hex

Q3 Q2 Q1 Q0 D7 D6 D5 D4 D3 D2 D1 DO

O O O O O O O O O O O OH

0 0 0 1 0 0 0 1 0 0 0 0 10H

O O 1 0 O O 1 0 0 0 0 0 20H

O O 1 1 O O 1 1 0 0 0 0 30H

O 1 0 0 O 1 0 0 0 0 0 0 40H

O 1 0 1 O 1 0 1 O O O O 50H

O 1 1 0 O 1 1 0 0 0 0 0 60H

0 1 1 1 O 1 1 1 0 0 0 0 70H

1 0 0 0 1 O O O O O O O 80H

1 0 0 1 1 0 0 1 0 0 0 0 90H

1 0 1 0 1 0 1 0 0 0 0 0 AOH

1 0 1 1 1 0 1 1 0 0 0 0 BOH

1 1 0 0 1 1 0 0 0 0 0 0 COH

1 1 0 1 1 1 0 1 0 0 0 0 DOH

1 1 1 0 1 1 1 0 0 0 0 0 EOH

1 1 1 1 1 1 1 1 0 0 0 0 FOH

  Next, the operation of the above converter having the above structure will be described with reference to the

figure 5.

  When the conversion start signal CS is applied by the external device, i.e., the conversion start signal CS becomes a "low active" state, the controller 33 produces the erase signal CLR on the counter 32 to clear the counter 32. The controller 33 outputs the output enable signal OE to the initial value generator 31 and also generates the load signal CHARGE

on the counter 32.

  At this time, as shown in FIG. 4, the initial value generator 31 produces the 8-bit data DO-D7 approaching the level of the analog input signal IN and the output data DO-D7 are loaded into the

  counter 32 as initial count value.

  Then, the output data Q0-Q7 corresponding to the count value of the counter 32 is applied to the comparator CP1 via the D / A converter 2. Here, the data value of the ROM table 42 is set so that the signal level applied to the comparator CP1 by the D / A converter 2 is not greater than the input signal

analog IN.

  At the same time, when the output of the comparator CP1 becomes a high level, the clock signal CLK1 is applied to the counter 32 via the AND gate AND1 and the counter 32 performs a count with the initial value loaded to produce the count value by

  through the D / A converter 2.

  As the above operation continues so that the voltage value produced by the D / A converter 2 becomes higher at the level of the analog input signal IN, the output of the comparator CP1 becomes a low level, as shown in FIG. Here, the controller 33 produces the lock signal LA to the latch circuit 3 to latch the digital data (Q0-Q7) produced by the comparator 32 that corresponds to the level of the analog input signal IN and concurrently produces the completion signal from DC conversion to the external device to complete the

  so the analog-digital conversion.

  In the preferred embodiment, since the counting action of the counter 32 starts not from a level "0" but from an initial value approaching the level of the signal

  IN analog input, the analog conversion speed-

  digital is significantly improved.

  Therefore, it should be understood that the present invention is not limited to the particular embodiment described herein as the best mode of implementation of the present invention, but rather that the present invention is not limited to the mode of operation of the present invention. specific achievement

  described in this description except that it is defined

  in the appended claims. For example, in the mode

  embodiment above, the number of comparators in the initial value generator 31, here 16 (CP41-CP416), for calculating a data value approaching the analog input signal IN is not particularly limited and thus can be arbitrarily established according to the system that

uses the present invention.

  Also, in the above embodiment, after the output of the comparators CP41-P416 is encoded by the encoder 41 in the initial value generator 31, the encoding data is used as the address data of the table. ROM 42. However, the output of the comparators can be used as the address data of the ROM table 42 in

  appropriately establishing the number of comparators.

  As described above, the A / D converter according to the

  The present invention can achieve an analog conversion

high speed digital.

1l

Claims (5)

  An analog-to-digital converter which converts applied input signals to corresponding digital data, characterized by comprising: initial value producing means (31) for generating digital data approximating a level of said analog input signal; counting means (32) for counting a clock signal applied with an initial value of the data produced by said initial value producing means (31); digital-to-analog converting means (2) for producing a voltage signal corresponding to a count value produced by said counting means (32); and gate means for comparing a level of said analog input signal with a reference value produced by the digital-to-analog converter means (2) and applying a clock signal to said counting means (32) when the level of said analog input signal is   greater than said reference value.   2. Converter according to claim 1, characterized in that the aforementioned initial value generating means (31) comprises: at least two comparison means (CP41-CP416) for comparing the aforementioned analog input signal with a reference voltage predetermined different from each of them; data conversion means (41) for converting a comparison signal produced by said comparing means into initial value data of the counting means. Converter according to claim 2, characterized in that said data conversion means comprises a ROM table (42).   A converter according to claim 1, characterized in that said initial value generating means (31) comprises: a number of comparison means (CP41-CP416) for comparing said analog input signal with a voltage of predetermined reference different from each of them; encoder means (41) for encoding a comparison signal produced by said comparing means; and data conversion means (42) for converting data produced by said encoding means to data   initial value of the counting means.   5. Converter according to claim 4, characterized in that the aforementioned data conversion means comprises a ROM table (42).