FR2509889A1 - Central data collection from multiple peripheral sources - uses straight branch network with address to call peripheral device which puts its data onto network when called - Google Patents

Abstract

The data collecting unit includes a central processing unit (1) having a circuit (4,5,6,7,22) furnishing an interrogation signal (U(t)) containing an address (AO........A7) chosen from a set of addresses; (ii) several peripheral units (2) having a particular address (BO......B7). Each peripheral unit has an address recognition circuit (14,15,17, to 19) responding to the interrogation signal (U(t)) by emitting a control signal (LD) which causes (16,12) the data in the peripheral to be transferred to the central processor (1). The interrogation signal (U(t)) comprises two superposed signals, the first a constant DC level (U1) and the second a logic signal containing the peripheral address. Each peripheral device contains an electric circuit (11) to separate the logic signal from the DC level. The peripheral data is placed on the communication bus as a current loop signal.

Description

DATA COLLECTION INSTALLATION
The present invention relates to a data collection installation, of the type comprising a central unit capable of interrogating any one of several peripheral units. For this purpose, each peripheral unit has a particular address, and the central unit sends to all the peripheral units an interrogation signal containing address information. The peripheral unit whose address corresponds to this address information reacts to the interrogation signal by sending in turn to the central unit data which this peripheral unit has.

 Such an installation requires means for the transmission of the interrogation signal from the central unit to the peripheral units, means for the transmission of the signal containing said data, from a peripheral unit to the central unit, and means for the power supply of the central unit and each of the peripheral units.

 One of the aims of the invention consists in simplifying the installation by using the same means for the transmission of the interrogation signal and for the electrical supply of each peripheral unit from the central unit.

 To this end, in accordance with the invention, the interrogation signal is formed of at least two superposed electrical voltage signals: one of these signals is a DC voltage signal of constant amplitude at least equal to the voltage nominal supply of peripheral units; the other of these signals is a logic voltage signal containing address information.

 Each peripheral unit is equipped with a circuit for separating said signals from one another. The supply voltage of each peripheral unit is extracted from the DC voltage signal of constant amplitude; this supply voltage is applied to the supply terminals of said peripheral unit, while the other signal - the logic signal - is applied to the input of an address recognition circuit.

 According to a preferred embodiment, the data available in each peripheral unit are transmitted to the central unit by means of a modulation of the current flowing in a single bi-wire bus connecting the central unit to the peripheral units and already serving to convey the interrogation signal. Each peripheral unit has, on the one hand, a circuit for generating a sequential logic signal containing said data, and, on the other hand, means responding to said sequential logic signal by connecting or not connecting an electrical resistance between the conductors of the bus , depending on the state of said logic signal. The value of said electrical resistance is chosen so that each connection of this resistance between the conductors of the bus causes a significant variation in the current flowing in this bus.

 Thus, thanks to the invention, a single bi-wire bus is used both for the transmission of the interrogation signal, that of the data signal, as well as that of the supply voltage of the peripheral units. , these three transmissions can be carried out simultaneously. This results in a considerable simplification of the data collection installation.

 Furthermore, it is possible to carry out data collection installations very economically using the already existing two-wire connection networks.

 The characteristics and advantages of the invention will be better understood on reading the following description of an embodiment, description made with reference to the accompanying drawings in which: - Figure 1 is a general diagram of an installation according the invention; - Figure 2 is a block diagram showing the different functional elements of the central unit and a peripheral unit, according to an embodiment of the invention; - Figure 3 is a diagram showing, in more detail, a part of the central unit shown in Figure 2; - Figure 4 is a diagram of the electronic circuit of the remaining part of the central unit of Figure 2; - Figure 5 is an electrical diagram of a first part of the peripheral unit of Figure 2; - Figure 6 is a block diagram of another part of the peripheral unit of Figure 2; and FIG. 7 represents, in time correspondence, the signal diagrams present at various points of the installation shown in FIGS. 2 to 6.

 The data collection installation shown in FIG. 1 comprises a central unit 1 and several peripheral units 2 which are all connected to the central unit 1 by means of the same two-wire bus 3a, 3b on which said peripheral units 2 are connected in rings.

 In the direction going from the central unit 1 to the peripheral units 2, the bus 3a, 3b transmits the supply voltage of said peripheral units, a fixed frequency F1, and information constituted by the address of the peripheral unit 2 which must be questioned.

To this end, the central unit 1 is designed to produce between its output terminals la, lb a voltage signal U (t) the diagram of which is shown in FIG. La. As can be seen in this figure, the signal U (t) is formed by a succession of periods P1, P2, Pi ..., of durations equal to T, inside each of which the signal U (t ) successively takes fixed values
U2 and U1. If we designate by ti the time during which the signal
U (t) is equal to U2 during the period Pi, we note on the figure la that ti can take only two discrete values: respectively a quarter and three quarters of T. If we associate a binary logical value "O" or "1" for each of these two different values of ti, it is understood that the signal U (t) can represent a series of bits.

 The lowest voltage value U1 is chosen at least equal to the nominal value Va of the supply voltage of the peripheral units 2.

 As will be explained below, each peripheral unit 2 reacts to the reception of a signal U (t) containing information corresponding to its own address, by causing a modulation of the current I (t) flowing on the conductors 3a, 3b of the bus, this current modulation allowing the transmission of the data that said peripheral unit has.

According to the example shown in FIG. 2, the central unit 1 comprises - a microprocessor 4 which can supply via its data bus 4a (FIG. 3) the address bits AO, ..., A7, of a particular peripheral unit to be interrogated, - a parallel-series converter circuit 5, reacting to the signals representing the address bits AO, ..., A7, as well as to a write signal WR, by producing a signal SA containing the sequence of address bits AO, ..., A7, associated with protocol bits, - a logic circuit 6 transforming the signal SA into a logic signal SAM having the form of a signal analogous to the signal U (t) but in which U1 is equal to 0, - a circuit 7 supplying, from the SAM signal, the signal
U (t) being able to take only two values precisely set on the values U2 and U1, and - a circuit 8 connected by its inputs 8a, 8b across a resistor 9 traversed by the current I (t) flowing along the bus conductors 3a, 3b. The circuit 8 responds to the voltage existing across the resistor 9 by supplying, on its output 8c, a logic signal SD, containing in sequential form the data bits supplied by the peripheral unit 2 interrogated.

Each peripheral unit 2 comprises: - a GRAETZ bridge 10 (FIG. 5) having two inputs 10a, 10b connected to the inputs 2a resp. 2b of the peripheral unit 2, - a circuit 11 (figure 5) extracting the supply voltage
Go from the peripheral unit 2, the voltage present between the output terminals 10c, 10d of the GREATZ bridge 10, - a circuit 12 (figure 5) reacting to a logic signal SD by connecting or not connecting between the terminals 2a and 2b, an electrical resistance 13, according to the state of said signal SD, - a circuit 14 transforming the voltage signal U (t) present between terminals 2a and 2b into a SAM signal 'of identical shape to the SAM signal described here above, a circuit 15 developing, from said signal SAM ', on the one hand a clock signal F1' having an equal period T, and, on the other hand, a logic signal DA taking, at each period Pi signal
SAM ', the value O or the value 1 depending on whether the duration ti is equal to a quarter respectively three quarters of T. As will be explained below, the signal DA comprises a series of bits corresponding to the address information transmitted by the central unit 1.

 Each peripheral unit 2 further comprises an address recognition circuit for comparing the address contained in the signal DA with the proper address BO, ... B7 of said peripheral unit, and for reacting to a coincidence between said addresses in causing the transmission, by a latched memory circuit 16, of the signal SD which contains a series of bits corresponding to the data located in the peripheral unit 2.

 As can be seen in FIGS. 2 and 6, the address recognition circuit comprises - a serial-parallel converter 17 receiving on an input 17a the signal DA, - a memory with parallel outputs 18 providing permanently, on seven of its outputs, the bits BO ,. ..B7 corresponding to the proper address of the peripheral unit 2, and - a comparator 19 comparing two by two each bit Q1, ... Q12 of the DA signal with the following series of bits: 0, O, BO .. .B7, Bp, 1, delivered in parallel form by memory 18.

 When there is coincidence between each bit Qi and the corresponding bit of the series of bits delivered in parallel form by the memory 18, the comparator 19 emits a loading signal LD which is applied to the loading input 16a of the circuit 16. This last circuit permanently receives on eight of its inputs 162 to 169, a respective bit D1, ... D8 supplied by a device 20 which may be a sensor with digital output for measuring any parameter, for example a temperature sensor. On a first input 161, circuit 16 receives the logic signal 1, while on its last two inputs 161l and 1612, this circuit 16 receives logic signal 0. Finally on a tenth input 1610, circuit 16 receives a parity bit Dp developed by a circuit known per se 21, from bits D1 ... D8 received in parallel by this circuit 21.

 According to the example shown in FIG. 3, the circuit 4 is a microprocessor marketed by the company INTEL under the reference number 8085 and the parallel-series converter circuit 5 is a circuit marketed by this same company under the number 8251.

The central unit 1 is, moreover, provided with a circuit 22 supplying a clock signal F1 identical to the signal F1 'described above, and a second clock signal, of double frequency,
FO. The circuit 22 comprises (FIG. 3) a frequency generator,
such as an oscillator, 22a providing the FO signal, and a divider
par 2, 22b supplying the signal F1 from the signal FO.

Circuit 6 includes (Figure 3) a first NAND gate 6a
having two inputs receiving the signals FO and F1 respectively,
a second NAND gate 6b having two inputs receiving respectively
signal FO and signal SA, a third NAND gate 6c
having two inputs receiving respectively the signal SA and the
signal F1. The output of the NAND gate 6a is connected to two terminals
RxC and TxC of circuit 5. An AND gate 6d has three connected inputs
each at the exit of a respective NAND gate 6a, 6b, 6c. The
output of AND gate 6d constitutes the output of circuit 6, on
which is present the SAM signal.

As can be seen in Figure 4, circuit 7 includes
a first NPN transistor 7b, the base of which is connected, via a
resistor 7x, at the input terminal 7a of circuit 7, a first
Zener diode 7c of nominal voltage U1 which is connected in series with a resistor 7d between a + V supply terminal and the
collector of transistor 7b, a second voltage Zener diode 7th
nominal U2, which is connected between a GRD ground and the base of a
second transistor 7f. The terminal la is connected to the transmitter of the
transistor 7f while terminal lb is connected to ground GRD and to
the emitter of the first transistor 7b. Finally, the collector of the second
transistor 7f is connected, via resistor 9, to the power supply terminal
tati-on + V.

According to the example shown in Figure 4, the circuit 8
includes an 8d differential amplifier connected by its inputs
8a and 8b between the terminals of the resistor 9, a circuit 8e for
remove the DC component from the signal supplied by the amplifier
tor 8d and to rectify this signal, and a comparator circuit 8f
to put in binary form the signal provided by the circuit 8e.

According to FIG. 5, the circuit 11 comprises a Zener diode 11a
nominal voltage VA, connected in series with an iib resistor,
between terminals 10c, 10d of the GRAETZ bridge 10.

The circuit 12 includes a transistor 12a whose base is
connected to the control terminal 12b of circuit 12, control terminal
receiving the signal SD supplied by the circuit 16. The emitter-collector path of the transistor 12a is connected in series with the resistor 13 between the ground GRD and the terminal 10c of the GRAETZ bridge 10.

 The circuit 14 comprises a Zener diode 14a of nominal voltage equal to 1/2 (U1 + U2-Va), connected in series with a resistor 14b, between the terminals 10c and 10d. A SCHMITT flip-flop 14c is connected by its input, at the junction point 14d between the resistor 14b and the diode 14a.

The operation of the data collection installation shown in the drawings is as follows:
When the microprocessor 4 wants to interrogate a particular peripheral unit 2, it transmits to the circuit 5 the address AO, ... A7 of this peripheral unit via the data bus 4a, and it also applies to the circuit 5 a write signal WR.

 Circuit 5 transforms the address data AO, ... A7 received in parallel, into a sequential logic signal constituted by the series of address bits AO, ... A7, preceded by a start bit (in English "start bit") and followed by a parity bit Ap and two stop bits. This succession of bits, which constitutes the signal SA, the diagram of which is shown in FIG. 7, is transmitted at the frequency of the clock signal F1 produced by the circuit 22 of the central unit 1.

The signal SA is transmitted to circuit 6 which can be called "duty cycle modulator". Circuit 6 produces, from the signal SA, the signal SAM in the following manner: for each period
Pi of the clock signal F1 the SAM signal takes the value "1" for a duration ti equal to 1/4 or 3/4 of T depending on whether SA is in the state O or respectively.

 The SAM signal is used to control circuit 7, which can be called "controlled voltage source". This circuit 7 associates the fixed voltages U1 and U2 with the logic "O" and "1", respectively, of the signal SAM.

 Each peripheral unit 2 can be connected either in one direction or the other, between the conductors 3a, 3b of the single bus. This indifference of direction of connection is obtained by the GRAETZ 10 bridge.

 The circuit 11 extracts from the signal U (t) the voltage Va necessary for the electrical supply of the peripheral unit 2.

 Each peripheral unit 2 also extracts the logic component of the composite signal U (t) using circuits 14 and 15.

 As can be seen in FIG. 6, the circuit 15 comprises a flip-flop D, 15a whose input D receives the signal SAM, and whose output Q is connected to the input 17a of the circuit 17. The circuit 15 comprises at besides a monostable 15b whose input B receives the signal SAM, and whose output Q is connected to the clock input CL of the flip-flop 15a. The monostable 15b has a time constant equal to T / 2.

 Thus, the circuit 15 extracts from the signal SAM, the signal F1 'present at the output Q of the monostable 15b, the complementary clock signal 1 present at the output Q of the monostable 15b, as well as a signal DA identical to the signal SA containing the address information sent by circuit 5 of the central unit.

 The address sequence "O", AO, ... A7, Au, "1", "1" is applied to the rhythm of F1 on the input 17a of the serial-parallel converter 17. When the start bit, which is in this example the bit "O", arrives in twelfth position of circuit 17, the latter is automatically reset by a flip-flop D, 23, in order to be ready to receive the following address sequence. The input D of the flip-flop 23 is connected to the output of rank 12, Q12 of the circuit 17; the output Q of this flip-flop is connected to the reset input 17b of circuit 17, and the clock input CL of flip-flop 23 receives the signal F1 emitted by the output Q of the monostable 15b.

 If, just before this reset operation of circuit 17, there is a concordance between the content of the address message DA and the address message pre-programmed in the memory 18, a loading signal LD is emitted by the comparator 19 and is it applied to the loading input 16a of the parallel-series converter circuit 16. This circuit 16 responds to the signal LD by admitting, by its parallel inputs, a data message consisting of a data sequence D1 ,. ..D8 present on the output terminals of the device 20.

The parallel-series converter 16 transmits on its output 16b, at the rate of the frequency of the clock signal F1, a series of bits formed by the series of data bits D1, ... D8, preceded by a start bit which, in the example shown, is the bit "1", e followed by a bit of parity Bp supplied by the circuit 21 and of two: stop bits which, in the example shown, are the bits "O ". C data message constitutes the SD signal.

 This signal SD is used to modulate the current I (t) flowing on the conductors 3a, 3b of the single bus. This modulation is performed by the circuit 12 in synchronism with the frequency dt clock signal F1, in the following manner: depending on whether the signal S [is in the state "O" or "1", the transistor 12a is, respectively , the blocked state or the on state, which results in the non-connection respectively the connection of the resistor 1 between the terminals 10c and 10d. Each connection of the resistor 1: between said terminals 10c and 10d causes an increase in current db I (t).

 The variations of the current I (t) are detected by the circuit 8 which provides on its output 8c a logic signal SD 'identical to the signal SD supplied by the circuit 16.

As shown in Figure 3, the signal SD 'is applied to the terminal RxD of circuit 5. This last circuit clears the signal
SD of the protocol consisting of the start bit, the parity bit and the stop bits, and it is capable of transmitting to the microprocessor 4, in parallel form, the series of data bits
D1, ... D8, extracts from signal SD ', when said circuit 5 receives a read signal R emitted by this same microprocessor 4.

 The installation which has just been described finds particular application in the realization of an installation for managing the data supplied by several temperature sensors with digital output signal, these sensors being, for example, placed in various places of a residential building. It is advantageous to use temperature sensors requiring for their operation, a fixed reference frequency which can be precisely the frequency F1 transmitted by the central unit 1 to each peripheral unit 2, by means of the interrogation signal U (t). These temperature sensors can be of the oscillating quartz type.

Claims (4)

 1. Installation-data collection, of the type comprising  - a central unit (1) having a circuit (4,5,6,7,22) for  provide an interrogation signal (U (t)) containing an address  any (AO, ... A7) chosen from a set of addresses;  - several peripheral units (2) each associated with a  specific address (BO, ... B7), each peripheral unit includes  nant: (a) an address recognition circuit (14,15,17 to 19)  responding to said interrogation signal (U (t)) to react to the iden  between said transmitted address (AO, ... A7) and said party address  (BO, ... B7) by issuing a control signal (LD), (b) a  circuit (16,12) reacting to said control signal (LD) in the oven  supplying a signal (I (t)) containing data information (DO, ... D8) located in said peripheral unit, and (c)  power supply means for said peripheral unit (2) ;;  and  - a connection bus comprising several conductors (3a, 3b)  to transmit the interrogation signal (U (t)) to the perished units  spheres (2) and the data signal (I (t)) to the central unit  (1),  characterized in that said interrogation signal (U (t)) comprises  at least a first and a second signal superimposed, the first  signal being a DC signal of constant amplitude  (U1), and the second signal being a logic voltage signal related  providing the information of said address whatever (AO, ... A7), and  what said power supply means of each unit  peripheral include a circuit (11) for extracting signal  interrogation U (t) a direct voltage (Va).  2. Installation according to claim 1, characterized in that  that the circuit providing the data signal includes a circuit  (16) responding to the control signal (LD) by providing a signal  sequential logic (south) containing said data information  (DO, ... D8), and a circuit (12) comprising an electrical resistance  (13) and switching means (12a) responsive to said signal  sequential logic (SD) by connecting or not connecting between  conductors (3a, 3b) of the connection bus, said resistor (13),  and in that the central unit (1) comprises means (8, 9) for measuring the variations of the current (I (t)) flowing in said conductors (3a, 3b) of the connection bus.  3. Installation according to one of claims 1 and 2, characterized in that the connection bus consists of two conductors (3a, 3b).  4. Installation according to one of claims 1 to 3, characterized in that a two-wave rectification circuit (10) is provided at the input of each peripheral unit (2).