KR100223673B1 - Sense amp circuit - Google Patents

Abstract

The bicymoss sense amplifier circuit of the present invention includes a sense amplifier section including a pair of bipolar transistors each receiving an input level applied thereto as a base, and emitters coupled to each other, and MOS transistors serving as current sources of the transistors; A voltage drop connected between both output terminals of the sense amplifier and a power supply voltage, and having a MOS transistor in the voltage drop so that the amount of the voltage drop is determined by the resistance and the combined parallel resistance value of the MOS transistor. It is characterized by stabilization.

Description

Anti-saturation biscimos sense amplifier circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier circuit applied to a semiconductor memory device, and more particularly to a bicymoss sense amplifier circuit capable of preventing undesirable saturation during a sensing operation.

In general, saturation of transistors in the sense amplifier circuit is a factor that reduces noise and sensing speed. Therefore, since an unstable output level is generated from the sense amplifier, it often causes an error in data sensing, which needs to be solved.

FIG. 1 shows a conventional biCMOS sense amplifier circuit composed of a bipolar transistor and a MOS transistor. When the voltage level of the source wing width is applied to the input terminals INA and INB during sensing, the voltages dropped by the threshold voltages of the bipolar transistors B1 and B2 are displayed at the nodes A and B, respectively. When the sense amplifier enable signal SAE is applied, the MOS transistors M1, 2, and 3, which act as current sources, are turned on and each base receives the voltages of the nodes A and B and emits couplers to the operation of the bipolar transistors B3 and B4. As a result, the sensed voltage levels appear in the output terminals OUTA and OUTB. In this case, the output voltage levels of the output terminals OUTA and OUTB are determined depending on the voltage difference of the nodes A and B, the current source, and the resistances of the resistors R1 and R2 respectively connected to the collectors of the bipolar transistors B3 and B4.

However, considering the reliability of the device, the sense amplifier should be able to satisfy noise immunity and sensing speed and stable output level in all regions of low VCC and high VCC. In view of this, the sense amplifier circuit has a low output level at the low VCC, which is lower than the level at the input terminal due to the increase in the collector current due to the decrease in the voltage drop of the resistors R1 and R2 due to the increase in the source current at the high VCC. There is. In this case, the swing width of the output voltage is drastically reduced so that the bipolar transistor operates in the saturation region. 8 is a simulation waveform diagram showing the waveform of each part according to FIG. 1. Referring to FIG. 8, it can be seen that when the operating waveforms of the low VCC and high VCC regions are compared with each other, the output level is rapidly reduced due to saturation in the high VCC region. That is, it can be seen that the waveform 80 at the low VCC is 84 at the high VCC, the waveform 82 is 85, and 83 rapidly changes to 86. Therefore, this conventional sense amplifier has a problem that causes malfunction and speed delay of the device.

An object of the present invention is to provide a sense amplifier circuit that can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a bicymoss sense amplifier circuit capable of preventing undesirable saturation phenomenon during a sensing operation.

Another object of the present invention is to provide a sense amplifier circuit capable of satisfying noise immunity, sensing speed, and stable output level in all regions of low VCC and high VCC.

1 is a conventional bismosose sense amplifier circuit diagram.

2 is a bicymoss sense amplifier circuit according to an embodiment of the present invention.

3 to 7 are bicymossense amplifier circuit diagrams showing various embodiments of the present invention.

8 and 9 are simulation waveform diagrams showing the waveforms of each part according to FIGS. 1 and 2, respectively.

A bicymoss sense amplifier circuit according to an embodiment of the present invention for achieving the above objects, each of which receives an input level applied as a base and functions as a pair of bipolar transistors and the emitter of each other coupled as a current source of the transistor And a voltage drop portion connected between both output terminals of the sense amplifier portion and a power supply voltage, wherein a voltage transistor is included in the voltage drop portion so that the amount of the voltage drop is combined with the resistance and the MOS transistor. Characterized in that it is determined by the value of the parallel resistance.

Hereinafter, various exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

2 shows a bicymoss sense amplifier circuit according to an embodiment of the present invention. Referring to FIG. 2, in order to prevent saturation, a sense amplifier unit includes a pair of bipolar transistors each receiving an input level applied as a base, and emitters coupled to each other, and MOS transistors serving as current sources of the transistors. 10 and a voltage drop unit 20 connected between both output terminals of the sense amplifier unit and the power supply voltage, and the transistors MP1 and MP2 are provided in parallel in the voltage drop unit. Therefore, in this case, the amount of voltage drop is determined by the combined parallel resistance value of the resistor R1 and the MOS transistor. In addition, when the resistors R3 and 4 are connected in series with the MOS transistors MP1 and 2, the synthesized parallel resistance is expressed as a parallel resistance value between the resistance of the R1 and the (R3 + MP1) resistance.

In this sense amplifier circuit, the output level in the low VCC region and the output level in the high VCC region are almost the same. This is because in the high VCC region, saturation is prevented because the voltage of the MOS transistors MP1 and 2 connected to the resistors R1 and R2 decreases accordingly. Therefore, in this case, the swing width of the output voltage is similar without being reduced in the low VCC region or the high VCC region. 9 is a simulation waveform diagram showing the waveform of each part according to FIG. 2. In comparison with the case of FIG. 8, it can be seen that the operating waveforms in the low VCC and high VCC regions are similar. That is, it can be seen that waveform 90 at low VCC becomes 94 at high VCC, waveform 92 is 95, and 93 hardly changes to 96. Therefore, such a sense amplifier can solve the conventional problem that causes malfunction and speed delay of the device.

3 to 7 are bicymossense amplifier circuit diagrams illustrating various embodiments of the present invention. 3 shows an embodiment in which the voltage drop unit 20 of FIG. 2 is applied to a two stage amplifier as it is. Referring to FIG. 4, the configuration of the voltage drop section is modified to the configuration of FIG. 2 to show the voltage drop section 21 in which a resistor and a type MOS transistor are connected in series. In this case, the amount of voltage drop is determined by the resistance and the synthesized series resistance of the type MOS transistor. In FIG. 5, the configuration of the voltage drop unit 20 of FIG. 2 is modified and replaced with the N-type MOS transistors MN1 and 2. Similarly, in the case of FIG. 6 and FIG. 7, it can be seen that the example is composed of voltage drop parts 23 and 24, respectively.

As described above, according to the present invention, noise immunity, sensing speed, and stable output level are satisfied in all regions of the low VCC and the high VCC.

Claims (4)

A sense amplifier circuit comprising: a sense amplifier unit comprising a pair of bipolar transistors each receiving an input level applied thereto as a base and having emitters coupled to each other, and MOS transistors serving as current sources of the transistors; A circuit having a voltage drop connected between both output terminals of the amplifier unit and the power supply voltage, wherein a voltage transistor is provided in the voltage drop unit so that the amount of the voltage drop is determined by the resistance and the combined parallel resistance value of the MOS transistor; . The circuit of claim 1, wherein the MOS transistor in the voltage drop is a type MOS transistor having a channel connected in parallel to the resistor and a gate of which is grounded. A sense amplifier circuit comprising: a sense amplifier unit comprising a pair of bipolar transistors each receiving an input level applied thereto as a base and having emitters coupled to each other, and MOS transistors serving as current sources of the transistors; And a voltage drop connected between both output terminals of the amplifier unit and the power supply voltage, and having a type MOS transistor in the voltage drop unit so that the amount of the voltage drop is determined by the resistance and the synthesized series resistance value of the type MOS transistor. Circuit. A sense amplifier circuit comprising: a sense amplifier unit comprising a pair of bipolar transistors each receiving an input level applied thereto as a base and having emitters coupled to each other, and MOS transistors serving as current sources of the transistors; And a voltage drop connected between both output terminals of the amplifier unit and the power supply voltage, wherein an N-type transistor is provided in the voltage drop unit so that the amount of the voltage drop is determined by the resistance and the combined parallel resistance value of the PMOS transistor. Circuit.