JP3076101B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power consumption and high speed Bi
The present invention relates to a semiconductor integrated circuit device (LSI) having a CMOS configuration.

In recent LSIs, a Bi-CMOS LS having an ECL input / output circuit and a TTL input / output circuit capable of handling ECL level signals and TTL level signals is known.
I is required. In addition, L of this Bi-CMOS configuration
It is necessary for SI to have high speed, and T
It is necessary to increase the speed of the TL output circuit.

[0003]

2. Description of the Related Art FIG. 3 shows a TTL output circuit 20 in a conventional Bi-CMOS LSI.

The TTL output circuit 20 comprises an input circuit section 21 and an output circuit section 22, and the P
The CMOS inverter 23 composed of the MOS and NMOS transistors MP1 and MN1 is connected between the ground GND and the low power supply VEE, and the Bi-CMOS level input signal IN is input to the gate terminals of both transistors MP1 and MN1. A node a between both transistors MP1 and MN1 is a transistor T1 and a PMOS transistor M
It is connected to the high power supply VCC through P2. The base terminal of the transistor T1 and the gate terminal of the PMOS transistor MP2 are connected to the ground GND.

The collector terminal of the phase dividing transistor T2 constituting the output circuit section 22 is a PMOS transistor MP
3, the emitter terminal is connected to ground GND via a resistor R1, and the base terminal is connected to the collector terminal of the transistor T1. Note that a Schottky barrier diode D1 is connected with a reverse bias between the collector and the base of the phase division transistor T2 to prevent saturation of the phase division transistor T2. Further, a Schottky barrier diode D2 is connected between the base terminal of the phase division transistor T2 and the ground GND to prevent the base potential of the phase division transistor T2 from dropping below a predetermined potential.

The emitter terminal of the output transistor T3 is connected to the ground GND, and the base terminal is connected to the emitter terminal of the phase division transistor T2. An output transistor T4 and a transistor T5, which are Darlington connected to each other, are connected between the collector terminal of the phase division transistor T2 and the collector terminal of the output transistor T3. Output transistor T4
Is connected to the high power supply VCC through a resistor R2, and the emitter terminal is connected to the collector terminal of the output transistor T3. The base terminal of the output transistor T4 is connected to the collector terminal of the output transistor T3 via the resistor R3 and the Schottky barrier diode D3. The base terminal of the transistor T5 is connected to the collector terminal of the phase division transistor T2. The output terminal Vout is connected between the output transistors T3 and T4, and a Schottky barrier diode D4 is connected between the output terminal Vout and the ground GND to prevent the output from dropping too much.

Therefore, the PMOS transistor MP1 is turned on based on the Bi-CMOS level input signal IN, and
When the MOS transistor MN1 is turned off, the base potential of the phase division transistor T2 is increased, and the phase division transistor T2 is turned on.
5, T4 is turned off, the output transistor T3 is turned on, and the TTL level L-level output signal is output from the output terminal Vout. When the PMOS transistor MP1 is turned off and the NMOS transistor MN1 is turned on based on the input signal IN, the base potential of the phase dividing transistor T2 is lowered to turn off the phase dividing transistor T2. Based on this, the transistor T5 and the output transistor T4 are turned off. Is turned on and the output transistor T
3 is turned off, and an H-level output signal of TTL level is output from the output terminal Vout.

[0008]

However, the propagation delay time tpd of the output signal of the TTL output circuit 20 shown in FIG.
Is determined by the switching speed of the phase division transistor T2, that is, the vertical speed of the base potential of the transistor T2. Since this is determined by the switching speed of the CMOS inverter 23, there is a problem that the propagation delay time tpd becomes long.

The current flowing through the NMOS transistor MN1 greatly affects the vertical speed of the base potential of the phase division transistor T2.
The amplification factor β that determines the threshold voltage of N1, the drain current,
The current flowing through the NMOS transistor MN1 fluctuates due to inevitable manufacturing variations in parameters such as the on-resistance and the fluctuation of the low power supply VEE.
There is a problem that the operation speed of the TL output circuit 20 fluctuates greatly.

The TTL output circuit 20 has a Bi-CM
The threshold value of the OS level is determined by the CMOS inverter 23, and ideally becomes VEE / 2, which is an intermediate value between the ground GND and the low power supply VEE. However, actually, in order to control the base potential to increase the switching speed of the phase division transistor T2, the drain current of the PMOS transistor MP2 and the NMOS transistor M2 are controlled.
Considering the balance with the drain current of N1, NMOS
The size of the transistor MN1 (the gate length and the gate width of the MOS transistor) must be determined. As a result, the threshold value of the CMOS inverter 23 is determined by the NMOS transistor MN1, and may not always be VEE / 2. In this case, there is a problem that a margin for noise is reduced and normal level conversion cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. In a Bi-CMOS semiconductor integrated circuit device having an ECL input / output circuit and a TTL input / output circuit, the speed of the TTL output circuit is increased. It is another object of the present invention to provide a semiconductor device capable of suppressing fluctuations in operation speed due to manufacturing variations and power supply fluctuations, and stabilizing a threshold voltage to perform normal level conversion.

[0012]

According to a first aspect of the present invention, an ECL input / output circuit and a TTL input / output circuit are provided, and a TTL output circuit is provided for inputting a Bi-CMOS level input signal. Circuit, a phase division transistor that performs on / off operation based on an output signal of the input circuit unit, and an output transistor that is driven based on the on / off operation of the phase division transistor and outputs a TTL level output signal -CMOS provided with a section
In the semiconductor integrated circuit device having the above structure, the input circuit portion of the TTL output circuit is configured such that a first transistor for inputting a Bi-CMOS level input signal and a second transistor for inputting a Bi-CMOS level threshold voltage as a reference voltage. A differential circuit portion having an emitter-coupled transistor and a constant current source connected to the emitter side of the differential circuit portion, wherein an output signal of a collector terminal of the first transistor is supplied to a base terminal of the phase division transistor. I entered it.

[0013] In the second invention, the TTL output circuit has an ECL.
A threshold voltage generation circuit is provided for generating a Bi-CMOS level threshold voltage input to the second transistor from a bias voltage for an input / output circuit.

[0014]

According to the first aspect of the present invention, the input circuit in the TTL output circuit includes the differential circuit in which the first and second transistors are emitter-coupled, and the constant current source. The switching speed of the unit is increased, and particularly, since a constant current source is used, the fall of the base potential of the phase division transistor is accelerated and the propagation delay time of the output signal from the L level to the H level is shortened. Further, since a constant current source is used in the input circuit section, fluctuations in the current flowing in the input circuit section are suppressed even if there are manufacturing variations or power supply fluctuations in the first and second transistors, and the operation speed of the TTL output circuit is reduced. Hardly fluctuates. Further, the reference voltage input to the second transistor of the differential circuit unit is Bi-C
Since the threshold voltage is at the MOS level, the noise margin is improved, and stable level conversion is performed.

Further, according to the second aspect, the threshold voltage of the Bi-CMOS level is easily generated from the bias voltage for the ECL input / output circuit.

[0016]

FIG. 1 shows an embodiment of the present invention.
This will be described with reference to FIG. For convenience of description, the same components as those in FIG.

FIG. 2 schematically shows an LSI 1 having a Bi-CMOS configuration. A TTL input circuit 3, an ECL input circuit 4, an internal circuit 5, a TTL output circuit 6, and a TTL output circuit 6 having a Bi-CMOS or CMOS configuration are provided on a chip 2. A circuit 7 is formed. TTL input circuit 3, ECL input circuit 4, TTL
The output circuit 6 and the ECL output circuit 7 are supplied with a high power supply VCC and a low power supply VEE, and the internal circuit 5 is supplied with a low power supply VEE. In this embodiment, +5 volts is used as the high power supply Vcc, and B of -5.2 volts is used as the low power supply VEE.
An i-CMOS level power supply is used.

The TTL input circuit 3 inputs a TTL level (+3 volt to 0 volt in this embodiment) input signal and outputs
i-CMOS level (0 volts to -5.2 in this embodiment)
Volts) and outputs the signal to the internal circuit 5,
The ECL input circuit 4 has an ECL level (−0.
9 volts to -1.7 volts)
-Output the signal converted to the CMOS level to the internal circuit 5.

The TTL output circuit 6 receives a Bi-CMOS level signal output from the internal circuit 5, converts the signal to a TTL level signal, and outputs the signal to the outside. The ECL output circuit 7 outputs the signal from the internal circuit 5. The input Bi-CMOS level signal is input, level-converted to an ECL level signal, and output to the outside.

FIG. 1 shows details of the TTL output circuit 6, which comprises an input circuit section 10 and the output circuit section 22,
The input circuit section 10 includes a differential circuit section 11, a constant current source 12, a threshold voltage generation circuit section 13, and the like.

The differential circuit section 11 includes a first transistor T6
And the second transistor T7 are emitter-coupled. The base terminal of the first transistor T6 has B
An input signal IN at the i-CMOS level is input, and a threshold voltage at the Bi-CMOS level is input to the base terminal of the second transistor T7 from the threshold voltage generation circuit unit 13 as a reference voltage Vref. The collector terminal of the first transistor T6 is connected to the high power supply VCC via the PMOS transistor MP2, and is connected to the base terminal of the phase division transistor T2 of the output circuit unit 22.

The constant current source 12 comprises a constant current transistor T8 connected to the emitter side of the differential circuit section 11, and a resistor R4 connected between the emitter terminal of the constant current transistor T8 and the low power supply VEE. A bias voltage VCS is input to a base terminal of the current transistor T8 from a bias voltage generation circuit (not shown) for an ECL input / output circuit.

The threshold voltage generating circuit 13 has a collector terminal connected to the ground GND and a base terminal connected to the bias voltage V of the bias voltage generating circuit (not shown).
A transistor T9 to which BB1 (-1.3 volts in the present embodiment) is input, a Schottky barrier diode D5 for lowering the level connected to the emitter terminal of the transistor T9, and between the diode D5 and the low power supply VEE. And a constant current source comprising a constant current transistor T10 and a resistor R5. The constant current transistor T
10, the bias voltage VCS is input.

Then, the threshold voltage generation circuit 13
By lowering the bias voltage VBB1 for the CL input / output circuit by the transistor T9 and the Schottky barrier diode D5, the reference voltage Vref input to the base terminal of the second transistor T7, that is, the threshold voltage of the Bi-CMOS level Is generated. Therefore, if the base-emitter voltage of the transistor T9 is about 0.8 volts and the voltage drop of the Schottky barrier diode D5 is about 0.4 volts, the base potential of the second transistor T7 is about -2.5 volts. This is Bi-CM
It is almost equal to the OS level threshold value VEE / 2 (= -2.6 volts).

Now, in the TTL output circuit 6 configured as described above, the input signal IN at the Bi-CMOS level
Becomes smaller than the reference voltage Vref, the transistor T6
Turns off and the transistor T7 turns on. As a result, the base potential of the phase-dividing transistor T2 increases, turning on the transistor T2. Based on this, the transistors T5 and T4 are turned off and the output transistor T2 is turned off.
3 is turned on, and an L-level output signal of TTL level is output from the output terminal Vout.

Further, the input signal IN at the Bi-CMOS level
Becomes larger than the reference voltage Vref, the transistor T6
Turns on and the transistor T7 turns off. As a result, the base potential of the phase-dividing transistor T2 is lowered and the transistor T2 is turned off. Based on this, the transistor T5 and the output transistor T4 are turned on and the output transistor T3 is turned off. An H-level output signal is output.

At this time, the input circuit unit 1 of the TTL output circuit 6
0 comprises a differential circuit section 11 in which the first and second transistors T6 and T7 are emitter-coupled, and a constant current source 12, so that the switching speed of the input circuit section 10 can be reduced by the conventional CMOS inverter 23. In particular, since the constant current source 12 is used, the fall of the base potential of the phase division transistor T2 becomes faster, and the propagation delay time of the output signal from the L level to the H level can be reduced. Thus, the speed of the TTL output circuit 6 can be increased.

Further, in this embodiment, since the constant current source 12 is used for the input circuit section 10, even if there is a variation in the manufacturing of the first and second transistors T6 and T7 and a change in the power supply VCC and VEE, the input circuit is changed. The fluctuation of the current flowing through the unit 10 is suppressed,
The operation speed of the TTL output circuit 6 hardly changes.

Further, in the present embodiment, the threshold voltage generating circuit unit 13 includes the transistor T9, the Schottky barrier diode D5, the constant current transistor T10, and the resistor R5.
, The bias voltage V for the ECL input / output circuit
By lowering BB1 with the transistor T9 and the Schottky barrier diode D5, a threshold voltage of Bi-CMOS level can be easily generated. or,
This Bi-CMOS level threshold voltage is referred to as a reference voltage V
Since the signal ref is input to the base terminal of the second transistor T7, the noise margin can be improved and stable level conversion can be performed.

[0030]

As described above in detail, according to the first aspect, a B having an ECL input / output circuit and a TTL input / output circuit is provided.
In a semiconductor integrated circuit device having an i-CMOS configuration, TT
The speed of the L output circuit can be increased, the fluctuation of the operation speed due to manufacturing variations and power supply fluctuation can be suppressed, and the threshold voltage can be stabilized to perform normal level conversion.

According to the second aspect, the threshold voltage at the Bi-CMOS level can be easily generated from the bias voltage for the ECL input / output circuit.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing a TTL output circuit according to one embodiment.

FIG. 2 is a block diagram schematically illustrating an LSI according to an embodiment;

FIG. 3 is an electric circuit diagram showing a conventional TTL output circuit.

[Explanation of symbols]

 Reference Signs List 6 TTL output circuit 10 Input circuit section 11 Differential circuit section 12 Constant current source 13 Threshold voltage generation circuit section 22 Output circuit section T2 Phase division transistor T3, T4 Output transistor T6 First transistor T7 Second transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 19/08

Claims (2)

(57) [Claims] An TTL output circuit (6) comprising an ECL input / output circuit and a TTL input / output circuit, comprising: an input circuit section (10) for inputting a Bi-CMOS level input signal; and an input circuit section (10). A phase division transistor (T2) that performs on / off operation based on an output signal; and a TTL that is driven based on the on / off operation of the phase division transistor (T2)
Output transistor (T3,
T4) and an output circuit section (22) comprising
In a semiconductor integrated circuit device having a CMOS configuration, an input circuit section (10) in the TTL output circuit (6)
A first transistor (T6) for inputting a Bi-CMOS level input signal (IN) and a second transistor (T7) for inputting a Bi-CMOS level threshold voltage as a reference voltage. Differential circuit (1
1) and a constant current source (12) connected to the emitter side of the differential circuit section (11), and outputs an output signal from the collector terminal of the first transistor (T6) to a phase division transistor (T2). A semiconductor integrated circuit device, wherein the input is made to a base terminal of the semiconductor integrated circuit. 2. An input circuit section (10) in a TTL output circuit (6) includes a bias voltage (VBB) for an ECL input / output circuit.
1) Bi-input to the second transistor (T7)
2. A threshold voltage generation circuit section for generating a threshold voltage of a CMOS level.
3. The semiconductor integrated circuit device according to 1.