KR100212834B1 - A monitor using a plasma display panel - Google Patents

Abstract

The present invention relates to a monitor employing a plasma display panel, the apparatus comprising: a phase locked loop (100); A horizontal position setting unit 200; A vertical position selection unit 300; An enable signal generator 400; An amplifier unit 500; An A / D converter 600; And a buffer unit 700. According to the present invention configured as described above, the horizontal / vertical synchronizing signal input from the computer and the computer signal of the progressive scanning method are converted into interlaced scanning computer data, It is possible to scan the panel by the interlaced scanning method, thereby improving the compatibility of the monitor employing the plasma display panel.

Description

Monitor using plasma display panel

FIG. 1 is a partial block diagram of a monitor employing a plasma display panel according to the present invention; FIG.

Figure 2 is a block diagram of the configuration of the phase locked loop shown in Figure 1;

FIG. 3 is a block diagram of the vertical position setting unit shown in FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

100: Phase locked loop 120: Phase comparator

140: Loop filter 160: Voltage controlled oscillator

180: N divider 200: Horizontal position setting unit

300: vertical position setting unit 400: enable signal generating unit

420: AND gate 500: Amplification unit

600: A / D conversion unit 700: Buffer unit

The present invention relates to a monitor employing a plasma display panel and, more particularly, to a plasma display panel in which a horizontal / vertical synchronizing signal and a progressive scan type computer signal are received from a computer and converted into interlaced scan type computer data, Monitor.

In general, cathode ray tubes (CRTs) are still in the spotlight in the field of display devices, and such CRTs have a few drawbacks. That is, since the CRT itself has a fresco-like structure, it is large in size and high in operating power, requiring a voltage of about 10,000 V, and also has the drawback that display distortion occurs.

In order to solve the drawbacks of the CRT, a method of solving the drawbacks of the CRT is specifically described. The matrix structure is used to solve the display distortion phenomenon, and the planar structure is adopted. Solves the problem of size, and solves the problem of high voltage by not using electron beam driven by high voltage.

The above-mentioned flat panel display device includes an active element EL, a light emitting diode (LED), a plasma display panel (PDP), and the like. Passive elements include a liquid crystal display (LCD) (ECD) and the like.

Of the above flat panel display devices, the PDP is a flat display device using a penning mixed gas for the discharge phenomenon, and a gas based on neon (Ne) or helium (He) gas of relatively high atmospheric pressure (100 Torr or more) A display device using a light emission phenomenon due to a discharge between narrow electrodes, and has a performance suitable for a computer terminal and an educational system, and has been partially put to practical use as a computer display.

The above-described penning gas is mainly Ne + Xe, Ne + He + Xe, and the reason why such a mixed gas is used is that the discharge starting voltage can be lowered when the mixed gas is more than one gas component. The discharge start voltage depends on the type of gas, the penning gas input, and the structure and form of the panel.

Since such a PDP is suitable for a large-area display device and can be colored, a planar wall-mounted television is also being accessed. Particularly, an AC type (indirect discharge type) PDP is capable of displaying a large- Has attracted attention as a panel.

The types of PDPs can be classified as follows.

First, according to the discharge type, the PDP is classified into an AC type PDP (indirect discharge type) and a DC type PDP (direct discharge type) depending on the type of the driving voltage applied to the discharge cell.

That is, the AC type PDP is driven by the sinusoidal AC voltage or the pulse voltage, while the DC type PDP is driven by the DC voltage.

In general, two types of PDPs have different structures. In an AC type PDP, the electrode is covered with a dielectric of the glass, whereas a DC type PDP is exposed to an electrode, and a discharge current flows while a discharge voltage is applied.

The AC type PDP has a storage function inside the cell, but the DC type PDP has a merit such as facilitating image display by adding a gray scale.

In other words, there are a memory type in which the panel itself stores display information and a refresh type in which the panel itself has a memory of display information on the outside of the panel and displays it on the panel repeatedly.

Third, according to the shape of the display, the panel has a lattice-shaped electrode, the intersection of each electrode constitutes a pixel, a dot matrix type in which the degree of freedom is relatively high and characters and figures are displayed according to the relationship of the points, There is a segment type used for small display.

Fourthly, according to the type of the addressing mechanism of the discharge spot for display, the self-scan PDP, which is a functioning panel display giving the self-scanning function of the discharge point, and the self- There is a PDP.

The above-described PDP has the following advantages over other display devices. That is, since discharge is not performed when the voltage is less than a certain voltage (firing voltage), there is no restriction on the number of plasma display lines due to such nonlinearity, so that a large-scale fabrication is possible and a multiplexing technique for reducing the number of driving circuits can be used.

A large matrix display also has a memory function, which is needed to eliminate high brightness and blinking, while the CRT has a lifetime of 20,000 hours, while a PDP has a lifetime of 50,000 hours.

PDP is suitable for mass production because it does not have easily broken parts other than glass. Because it is simple in structure, large panel can be manufactured and it is possible to have a resolution of 100 lines / inch or more due to strong nonlinearity.

Since the discharge material is gas, the refractive index is 1, which means that the light does not disappear due to internal reflection and that external light is not reflected or scattered by the display material.

Unlike other flat panels, the PDP is sealed with glass at a temperature of 400 ° C or higher. This means that the plasma display can operate even in the presence of a high-humidity condition or a reactive gas. In most cases, It only changes by the circuit.

The computer system will be briefly described as follows.

The peripherals of the personal computer system include a printer that prints various kinds of information contained in a main personal computer (PC) on paper, a display monitor that displays various information on the screen, a floppy disk drive (FDD) , An auxiliary storage device such as a hard disk drive (HDD), and a modem used to connect various information to a computer in another place by a telephone line.

Among them, a display monitor is a device that displays the information of the main device in the easiest and quickest manner as an image. In the present invention, a display monitor is implemented as a PDP.

Subsequently, the scanning method can be broadly divided into interlaced scanning and noninterlaced scanning.

The interlaced scanning is a method of scanning an image by scanning one or more scanning lines from top to bottom in a screen when scanning an image and outputting it as an electric signal or displaying on a screen. In this method, one frame is divided into a field composed of odd- And then the odd field is scanned first and then the even field is scanned.

On the other hand, the progressive scan refers to a method of scanning an image and outputting it as an electric signal or displaying the image on the screen without skipping the scan line sequentially from the top to the bottom of the screen, and the progressive scan is denser than the interlace scan.

In general, the computer signal is scanned according to the progressive scanning method (60 frames per second) and the television signal is scanned according to the interlaced scanning method (30 frames per second). Recently, there is a tendency to integrate the computer and the television into a single system In view of compatibility, the PDP monitor needs to process signals to display not only television signals but also computer signals.

In order to solve this problem, it is necessary to generate a signal capable of interlacing a computer signal. In this case, deterioration of image quality is expected due to interlaced scanning. However, the present invention will be described in view of compatibility of a PDP monitor.

When a plasma display FP intends to scan a panel according to an interlaced scanning method in a monitor employing a plasma display panel, a computer signal of a progressive scanning system input from a computer is converted into a non- There is a need to provide a device for converting a computer signal into a computer signal in a monitor.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and it is an object of the present invention to provide a plasma display apparatus and a plasma display apparatus capable of performing interlaced scanning on a plasma display panel by converting a horizontal / vertical synchronizing signal input from a computer and a computer signal of a progressive scanning system into non- And it is an object of the present invention to provide a monitor employing a plasma display panel.

According to an aspect of the present invention, there is provided a monitor employing a plasma display panel, including: a phase locked loop that receives a horizontal synchronizing signal from a computer roll and outputs a signal synchronized with the frequency and phase of the horizontal synchronizing signal; A horizontal position setting unit for receiving a signal from the phase locked loop and a horizontal synchronization signal from a computer to output a horizontal position signal by setting a horizontal position; A vertical position setting unit for receiving a horizontal synchronizing signal and a vertical synchronizing signal from a computer and outputting a vertical position signal by setting a vertical position; An enable signal generator for receiving a horizontal position signal from the horizontal position setting unit and a vertical position signal from the vertical position setting unit and outputting an enable signal; An amplifier for receiving a computer signal from a computer and performing amplification and level shifting; An A / D converter for receiving an amplified analog computer signal from the amplifying unit and converting the amplified analog computer signal into data to be decoded by a decoded computer according to a signal from the phase locked loop; And a buffer unit for receiving computer data from the A / D converter and buffering the data, and for outputting computer data in units of fields for interlaced scanning according to an enable signal from the enable signal generator, .

Hereinafter, the structure of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a partial block diagram of a monitor employing a plasma display panel according to the present invention. The monitor of the present invention receives a horizontal synchronizing signal H Sync from a computer (not shown) Phase locked loop (PLL) 100 for outputting a signal synchronized with a frequency and a phase of a synchronous signal; A vertical position setting unit which receives a signal from the phase locked loop 10 and a horizontal synchronizing signal H Sync and a vertical synchronizing signal V Sync from a computer and outputs a vertical position signal by setting a vertical position V Position, (300); An enable signal generator 400 for receiving a horizontal position signal from the horizontal position setting unit 200 and a vertical position signal from the vertical position setting unit 300 and outputting an enable signal enable; An amplifying unit 500 for receiving a computer signal (R, G, B signal) from a computer and performing amplification and level shifting; (R, G, B data) according to a signal from the phase-locked loop 100 and receiving the amplified analog computer signals R, G, B from the amplifying unit 500, / D converter 600; And buffering the computer data (R, G, and B data) from the A / D converter 600 and outputting the buffered data according to an enable signal from the enable signal generator 400 And a buffer unit 700 for outputting field-level computer data (R, G, B data) for interlaced scanning.

FIG. 2 is a block diagram of the phase-locked loop shown in FIG. 1. The phase-locked loop 100 receives a horizontal sync signal H Sync and a feedback signal from a computer (not shown) A phase comparator 120 (Phase Comparator or Phase Detector: PC) for generating a voltage corresponding to a phase difference of an input signal; A loop filter (LF) 140 for removing a high-frequency component generated in the phase comparator 120; A voltage controlled oscillator (VCO) 160 in which the oscillation frequency is fluted by the control voltage output from the loop filter 140; And an N-divider 180 for dividing the output frequency of the voltage-controlled oscillator 160 by an integer N and then transmitting the divider to the phase comparator 120.

FIG. 3 is a block diagram of the vertical position setting unit 300 shown in FIG. 1. Referring to the vertical position setting unit 300 of the present invention, A first counter 310 for receiving a horizontal synchronizing signal H Sync and a vertical synchronizing signal V Sync from a vertical blanking unit (not shown) and counting a line corresponding to a vertical blanking interval; A first D flip flop 320 for receiving a counting signal from the first counter 310 and outputting an enable signal; A first AND gate 330 for performing a logical AND operation on a horizontal synchronizing signal H Sync from the computer and an input signal from the first D flip flop 320; A second counter 340 for receiving the signal from the first AND gate 330 and counting the lines of the section having the video information; A second AND gate 350 for receiving a horizontal synchronizing signal H Sync from the computer and a counting signal from the second counter 340 to perform a logical AND operation; A third counter 360 for outputting a counting signal in accordance with an input signal from the second AND gate 350; A second D flip flop 370 for receiving a vertical synchronization signal V Sync from the computer and outputting an enable signal for obtaining odd field data; A third 3D flip-flop 380 for receiving a vertical synchronization signal V Sync from the computer and outputting an enable signal for obtaining even field data; And a counting signal from the second counter 340, a counting signal from the third counter 360, and an enable signal from the second flip-flop 370 and the third flip-flop 380 And a vertical position output unit 390 for outputting a vertical position (V Position).

Here, the vertical position output unit 390 outputs a counting signal from the second counter 340, a counting signal from the third counter 360, and an enable signal from the second flip-flop 370 A third AND gate 390-1 for receiving the input and performing a logical AND; An inverter 390-2 for inverting the counting signal from the third counter 360; A fourth logical product gate for receiving a counting signal from the second counter 340, an inverted signal from the inverter 390-2, and an enable signal from the third flip-flop 380, 390-3); And an OR gate 390-4 for performing a logical OR operation on the two signals from the third AND gate 390-1 and the fourth AND gate 390-3 to output a vertical position.

The enable signal generator 40 shown in FIG. 1 receives a horizontal position signal from the horizontal position setting unit 200 and a vertical position signal from the vertical position setting unit 300, And an AND gate 420 for outputting an enable signal (enable) after being performed.

Next, operations and effects of the present invention will be described in detail.

The phase locked loop (PLL) 100 shown in FIG. 1 adjusts an output frequency and a phase to an input frequency and a phase using a feedback signal. In other words, an input signal, that is, Here, the circuit receives a horizontal synchronizing signal (H Sync) from a computer and outputs the synchronized signal synchronized with the frequency and phase of the horizontal synchronizing signal (H Sync) And outputs a signal.

The operation of the phase-locked loop 100, which coincides the output frequency with the input frequency, will be described in detail as follows.

2, the phase comparator 120 generates a voltage corresponding to the phase difference between the two input signals, and the loop filter 140 removes high frequency components generated in the phase comparator 120 The voltage-controlled oscillator 160 is an oscillator whose oscillation frequency varies according to a control voltage. The N-divider 180 is connected to the voltage-controlled oscillator 160, 160 to an integer N and then feeds back the result to the phase comparator 120. [

Claim the V _i (t) and θ _i shown in FIG. 2 is an input signal (here, the horizontal synchronization signal) and the phase, V _o (t) and θ _o is the output signal voltage of the voltage-controlled oscillator 160 and the phase , V _d (t) represents the output voltage of the phase comparator 120, and V _c (t) represents the control voltage of the voltage controlled oscillator 160.

V _i (t) is applied to the phase comparator 120, the ground phase comparator (120), and generates a V _d (t) corresponding to the phase difference between V _o (t) and V _i (t) V _d (t) is a high-frequency component is removed by the loop filter 140, only the low frequency component and the V _c (t) is the control voltage of the voltage-controlled oscillator (160) V _c (t) is V _i (t) and V _o ( control the oscillation of the voltage controlled oscillator 160 so that the frequency difference of the oscillator 160 becomes smaller.

At this time, in the synchronous state, the frequency of the voltage-controlled oscillator 160 matches the frequency of the input signal, but the phase difference is the frequency of the voltage-controlled oscillator 160 at the oscillation frequency V _c (t) = 0 (The oscillation frequency of the voltage-controlled oscillator 160 of the oscillator 160) to the frequency of the input signal.

The horizontal position setting unit 200 shown in FIG. 1 receives a signal from the phase locked loop (PLL) and a horizontal synchronizing signal (H Sync) from a computer (not shown) ). In this horizontal position (for example, in a computer VGA mode corresponding to 640 * 480, 640 clocks are counted and 640 clock periods are output at a high level) It is necessary to set only an appropriate section of the video information in one line.

The vertical position setting unit 300 shown in FIG. 1 receives a horizontal synchronizing signal H Sync and a vertical synchronizing signal V Sync from a computer and sets a vertical position H Position. Refers to an appropriate section of the frame when image information is to be set in a frame.

In setting the vertical position, 240 H is set for only odd lines in the first frame, and 240 H is set for even lines in the second frame to set a total of 480 lines for two frames.

For reference, the standard of the computer signal is that the interval of the vertical sync signal (V Sync) corresponds to 2 H, the interval of vertical blanking (vertical blacking) which does not include the image information corresponds to 42 H, The included section corresponds to 480 H.

The vertical position setting unit 300 shown in FIG. 3 will be described in detail as follows.

The first counter 310 receives a horizontal synchronizing signal H Sync and a vertical synchronizing signal V Sync from a computer (not shown) and counts 42 H corresponding to a vertical blanking interval And outputs a signal corresponding thereto.

The first D flip-flop 320 receives the counting signal from the first counter 310 and outputs an enable signal. In the first D flip-flop 320, a 480 H line including a video signal and a 1 H line, Quot ;.

The first AND gate 330 receives the horizontal sync signal H Sync from the computer and the signal from the first D flip flop 320 and performs an AND operation.

The second counter 340 receives the signal from the first AND gate 330 and counts the lines of the section having the video information to output a signal. That is, the second counter 340 outputs a signal only for 480H sections, Level.

The second AND gate 350 receives the horizontal sync signal H Sync from the computer and the counting signal from the second counter 340 to perform a logical AND.

The third counter 360 outputs a counting signal according to an input signal from the second AND gate 350.

The second D flip-flop 370 and the third D flip-flop 380 receive the vertical synchronization signal V Sync from the computer and output an enable signal for obtaining the odd field data and the even field data, respectively, The enable signal is output to the high level alternately from the second D flip-flop 370 and the third D flip-flop 380.

In the vertical position output unit 390, a counting signal from the second counter 340, a counting signal from the third counter 360, and a counting signal from the 22D flip-flop 370 and the third flip- The third AND gate 390-1 outputs a counting signal from the second counter 340 and a third counter 360 from the third counter 360. [ And an enable signal from the second flip-flop 370. The inverter 390-2 inverts the counting signal from the third counter 360, The 4-ary gate 390-3 receives the counting signal from the second counter 340, the inverted signal from the inverter 390-2, and the enable signal from the 3-D flip-flop 380 And performs a logical AND operation on the OR gate 390-4 Is output to the vertical position by performing a third logical AND gate (390-1) and the second 4 (OR) sum fun receives the two signals from the logical product gate (390-3).

The enable signal generator 400 shown in FIG. 1 receives the horizontal position signal from the horizontal position setting unit 200 and the vertical position signal from the vertical position setting unit 300, and performs an AND operation And then outputs an enable signal (enable).

1, the amplifying unit 500 receives analog computer signals (R, G, and B signals) from a computer and performs amplification and level shifting. In the A / D converting unit 600, G, and B data from the phase-locked loop 100 and converts the analog computer signals R, G, and B into digital computer data R, G, and B data according to a clock signal from the phase-

The buffer unit 700 shown in FIG. 1 receives the computer data (R, G, B data) from the A / D converter 600 and buffers the computer data (R, G, B data) for interlaced scanning in accordance with an enable signal (enable)

Accordingly, interlace scanning can be performed by providing data to the plasma display panel of the monitor capable of scanning 30 screens per second.

As described above, according to the present invention, the horizontal / vertical synchronizing signal inputted from the computer and the computer signal of the progressive scan method are converted into the interlaced scanning computer data, so that the interlaced scan can be performed on the plasma display panel, It is possible to improve the compatibility of the monitor using the display panel.

The embodiments described above are merely illustrative in all respects and should not be construed as limiting the scope of the present invention, but all modifications that fall within the true spirit and scope of the present invention belong to the scope of the present invention.

Claims (2)

A phase locked loop (100) for receiving a horizontal synchronizing signal from a computer and outputting a signal synchronized with the frequency and phase of the horizontal synchronizing signal; A horizontal position setting unit 200 for receiving a signal from the phase-locked loop 100 and a horizontal synchronizing signal from a computer and outputting a horizontal position signal by setting a horizontal position; A vertical position setting unit 300 for receiving a horizontal synchronizing signal and a vertical synchronizing signal from a computer and outputting a vertical position signal by setting a vertical position; And an AND gate 420 for receiving a horizontal position signal from the horizontal position setting unit 200 and a vertical position signal from the vertical position setting unit 300 to perform an AND operation, A signal generator 40; An amplification unit 500 for receiving a computer signal from a computer and performing amplification and level shifting; An A / D converter 600 for receiving an amplified analog computer signal from the amplifier 500 and converting the amplified analog computer signal to digital computer data according to a signal from the phase-locked loop 100; And computer data from the A / D converter 600. The A / D converter 600 buffers the computer data in units of fields for interlaced scanning according to an enable signal from the enable signal generator 400 And a buffer unit (700) for controlling the plasma display panel. The apparatus of claim 1, wherein the vertical position setting unit (300) receives a horizontal synchronizing signal and a vertical synchronizing signal from a computer and counts a line corresponding to a vertical blanking interval; A first D flip flop 320 for receiving a counting signal from the first counter 300 and outputting an enable signal; A first AND gate 330 for performing a logical AND of a horizontal synchronizing signal from the computer and an input signal from the first D flip-flop 320; A second counter 340 for receiving the signal from the first AND gate 330 and counting the lines of the section having the video information; A second AND gate 350 for receiving a horizontal synchronizing signal from the computer and a counting signal from the second counter 340 to perform a logical AND operation; A third counter 360 for outputting a counting signal in accordance with an input signal from the second AND gate 350; A second D flip flop (370) for receiving a vertical synchronization signal from a computer and outputting an enable signal for obtaining odd field data; A third 3D flip-flop 380 for receiving a vertical synchronization signal from the computer and outputting an enable signal for obtaining even field data; And a counting signal from the second counter 340, a counting signal from the third counter 360, and an enable signal from the second flip-flop 370 and the third flip-flop 380 A third AND gate 390-1, a counting signal from the second counter 16, an inverted signal input from the third counter 360 via an inverter 390-2, Flop 380 and a fourth AND gate 390-3 for performing an AND operation on the third AND gate 390-1 and the fourth AND gate 390-3 And a vertical position output unit 390 configured to perform a logical OR operation on the two signals from the vertical address output unit 390-4 to output a vertical position. monitor.