KR100954327B1 - Liquid crystal display device and method for operating the same - Google Patents

Abstract

The present invention provides a liquid crystal display device and a driving method suitable for solving the spot phenomenon caused by external pressure by applying double speed driving and increasing the ability to cope with moving images in VA mode. A liquid crystal module comprising a display panel, a gate driver and a source driver for driving the display panel; An interface circuit for outputting vertical and horizontal synchronization signals, clocks, and R, G, and B control signals; And a liquid crystal driving circuit having a timing controller that sequentially outputs the image data and the black data to the liquid crystal module at twice the speed to receive the output signals of the interface circuit and drive the image frame to the reset frame for one frame time. It is done.

VA mode, double speed, reset frame, image frame

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR OPERATING THE SAME}

1 is a cross-sectional view showing a liquid crystal instability in a conventional VA mode LCD.

2 is a circuit configuration diagram of a liquid crystal display device according to the related art and the present invention.

3 is a view illustrating input / output signals of a timing controller of a liquid crystal display according to the related art.

4 is a schematic diagram of image output per frame of an LCD according to the related art.

5 is an output waveform diagram comparing SSC and data of a liquid crystal display according to the related art and the present invention.

6 is a configuration diagram of a timing controller of the liquid crystal display according to the present invention.

7 is a schematic diagram showing double-speed driving of the liquid crystal display according to the present invention.

8 is a light distribution according to the time of the present invention

Explanation of symbols on the main parts of the drawings

2: interface circuit 4: transmitter

6: liquid crystal drive circuit 8: receiver

12: multi-scan circuit 14: reference voltage generator

16: gate driving voltage generator 18: storage voltage generator                 

20: common voltage generator 22: liquid crystal module

24: Gate Driver 26: Source Driver

28: display panel 60: timing controller

61: frame buffer part 62: black data part

63: switching unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device driven by double speed by inserting a reset frame between frames and a driving method thereof.

As the information society develops, the demand for display devices is gradually increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELDs), and VFDs (Vacuum) Various flat panel display devices such as fluorescent display have been studied, and some are already used as display devices in various devices.

Among them, LCD is the most used as a substitute for CRT (Cathode Ray Tube) for mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption. In addition to mobile type such as notebook computer monitor, BACKGROUND ART Various developments have been made in televisions and computer monitors for receiving and displaying broadcast signals.

Although various technical advances have been made in order for such a liquid crystal display device to serve as a screen display device in various fields, the task of improving the quality of an image as a screen display device is often arranged with the above characteristics and advantages.

Therefore, in order to use a liquid crystal display as a general screen display device in various parts, it is a matter of how high quality images such as high definition, high brightness, and large area can be realized while maintaining the characteristics of light weight, thinness, and low power consumption. Can be.

The liquid crystal display may be divided into TN, IPS, and VA modes according to the driving mode of the liquid crystal. The VA mode liquid crystal display including the TN and IPS modes is driven by the liquid crystal display as shown in FIG. The circuit configuration thereof is briefly described as follows.

As shown in FIG. 2, the liquid crystal display device for applying the prior art has a liquid crystal module 22, a liquid crystal drive circuit 6 for driving the liquid crystal module 22, and an analog input signal in a digital form. It consists of an interface circuit (2) for converting and adjusting the resolution.

The liquid crystal drive circuit 6 and the interface circuit 2 are each mounted on a separate board (or board) and electrically connected to each other by a flexible printed circuit (FPC) and a connector. do.

The liquid crystal module 22 includes a display panel 28 and a gate driver 24 and a source driver 26 for driving the display panel 28 as shown in FIG. 2.                         

The display panel 28 includes a pixel matrix in which liquid crystal cells are arranged in a matrix form between two glass substrates (not shown).

The gate driver 24 divides and drives the ROW lines of the pixel matrix, and the source driver 26 supplies the image data to the column lines of the pixel matrix.

In addition, the interface circuit 2 may display the horizontal resolution signal Hsync and the vertical synchronization signal so that the input resolution or data of various frequencies may be displayed at the resolution of the display panel 28 (for example, XGA (1024 × 768)). A multi-scan circuit 12 for generating Vsync and a transmitter 4 for reducing electromagnetic interference by reducing image data supply lines.

The liquid crystal drive circuit 6 includes a receiver 8 for separating the three primary color data of the main clock Clk and the red cyan RGB from the image data supplied from the transmitter 4, the gate driver 24, and the source. A timing controller 10 for supplying a timing signal necessary for the driver 26, a reference voltage generator 14 for generating a reference voltage for converting image data into analog data, and a drive voltage of the gate driver 24; The gate driving voltage generator 16 for generating a voltage, the storage voltage generator 18 for supplying a storage voltage Vst to the auxiliary capacitor electrode 32, and the common voltage for the pixel electrode 30 are provided. And a common voltage generator 20 for supplying Vcom.

In the liquid crystal display device configured as described above, the timing controller 10 has the gate driver 24 according to the main clock CLKmain and the horizontal and vertical synchronization signals Hsync and Vsync supplied from the receiver 8 as shown in FIG. 3. ) And the source driver 26 to supply start pulses, scanning clocks, and the like, as well as digital RGB data.

That is, as shown in FIG. 3, the timing controller 10 has a vertical and horizontal synchronization signal (Vsync, Hsync) of the display, a DENB (Data Enable) signal indicating a section in which valid data is present, and a basic value of all synchronization signals. The clock CLK signal and the R, G, and B signals are input from an LCD driving system (for example, a computer).

By combining these signals, the GSP, GSC, and GOE signals used to control the gate driver 24 and the SSP, SSC, Load, Pol, and existing data signals used to control the source driver 26 are divided by two. (even), generate R, G, B data signals of order pairs.

The conventional liquid crystal display device driving by receiving the control signal of the timing controller outputs a corresponding image during each frame as shown in FIG. 4.

5A and 5B are timing diagrams showing a clock signal SSC and a data signal Data latching data on the rising or falling edge for one frame.

As described above, a liquid crystal display device that outputs a corresponding image during each frame may be divided into TN, IPS, and VA modes according to the driving mode of the liquid crystal. In this case, the VA mode is different from the horizontal alignment modes such as TN and IPS modes. As shown, since the liquid crystals are vertically aligned on the upper and lower substrate surfaces, the constraint force for tilting the liquid crystals in the center of the cell gap is very weak compared to the horizontal alignment mode.

As such, when a pressure is applied to the LCD surface in VA mode, the tilt direction is different from the normal driving part in the externally pressurized part, and the liquid crystal array becomes unstable, and stains remain easily even with small force.

When the liquid crystal array becomes unstable in this manner, the VA mode is normally a black mode, so that the liquid crystal returns to the normal driving state only after the black driving which becomes the initial alignment state causes a problem that the original recovery is not performed for a long time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to solve a stain phenomenon caused by external pressure in a VA mode liquid crystal display device, and to improve the ability to cope with moving images in VA mode. And a driving method thereof.

The liquid crystal display device of the present invention for achieving the above object comprises a display panel, a liquid crystal module comprising a gate driver and a source driver for driving the display panel; An interface circuit for outputting vertical and horizontal synchronization signals, clocks, and R, G, and B control signals; And a liquid crystal driving circuit having a timing controller that sequentially outputs the image data and the black data to the liquid crystal module at twice the speed to receive the output signals of the interface circuit and drive the image frame to the reset frame for one frame time. It is done.                     

The timing controller may include: a frame buffer unit for storing input image data and outputting image data stored during the image frame time in one frame, a black data unit for outputting black data during the reset frame time in one frame; And a switching unit for selectively connecting the frame buffer unit and the black data unit at an image frame and reset frame time, respectively.

According to an exemplary embodiment of the present invention, a method of driving a liquid crystal display device may include outputting vertical, horizontal synchronization signals and clock, R, G, and B control signals in an interface circuit; Outputting the image data and the black data for driving the image frame to the reset frame at double speed for one frame time by the timing controller receiving the output signals of the interface circuit; And sequentially outputting the image frame and the reset frame for one frame time in the liquid crystal module which receives the image data and the black data sequentially from the timing controller.

When the timing controller outputs the image data, the timing controller is connected to a frame buffer unit in which a switching element stores the image data.

When outputting the black data, the switching element is connected to the black data portion storing the black data.

The double speed output of the image data and the black data proceeds in accordance with the source sampling clock SSC at the double speed of the timing controller.

The present invention having the above characteristics relates to a liquid crystal display and a driving method thereof for performing double speed driving so as to enable two frame driving in the order of an image frame to a reset frame for one frame time.

Such a liquid crystal display and its driving method are particularly effective when applied to a VA mode liquid crystal display device that does not react quickly to stains caused by external pressure.

Hereinafter, a liquid crystal display and a driving method thereof according to an exemplary embodiment of the present invention will be described.

2 is a circuit diagram of a liquid crystal display device for applying the present invention, and FIG. 6 is a block diagram of a timing controller of the liquid crystal display device according to the present invention.

As shown in FIG. 2, the LCD according to the present invention uses a liquid crystal module 22, a liquid crystal driver circuit 6 for driving the liquid crystal module 22, and an analog input signal in a digital form. It consists of an interface circuit (2) for converting and adjusting the resolution.

Although not shown in the drawings, the liquid crystal drive circuit 6 and the interface circuit 2 are mounted on separate boards (or boards), and a flexible printed circuit (FPC) and a connector ( Electrically connected by a connector, etc.

The liquid crystal module 22 includes a display panel 28 and a gate driver 24 and a source driver 26 for driving the display panel 28 as shown in FIG. 2.

The display panel 28 includes a pixel matrix in which liquid crystal cells are arranged in a matrix form between two glass substrates (not shown).

The gate driver 24 divides and drives the ROW lines of the pixel matrix, and the source driver 26 supplies the image data to the column lines of the pixel matrix.

In addition, the interface circuit 2 may display the horizontal resolution signal Hsync and the vertical synchronization signal so that the input resolution or data of various frequencies may be displayed at the resolution of the display panel 28 (for example, XGA (1024 × 768)). A multi-scan circuit 12 for generating Vsync and a transmitter 4 for reducing electromagnetic interference by reducing image data supply lines.

The liquid crystal drive circuit 6 includes a receiver 8 for separating the three primary color data of the main clock Clk and the red cyan RGB from the image data supplied from the transmitter 4, the gate driver 24, and the source. A timing controller 10 for supplying a timing signal necessary for the driver 26, a reference voltage generator 14 for generating a reference voltage for converting image data into analog data, and a drive voltage of the gate driver 24; Gate driving voltage generation unit 16 for generating a voltage, a storage voltage generation unit 18 for supplying a storage voltage Vst to the auxiliary capacitor electrode 32, and a common voltage to the pixel electrode 30. And a common voltage generator 20 for supplying Vcom.

In the liquid crystal display device configured as described above, the timing controller 60 according to the present invention has a DENB (Data Enable) indicating a section in which the vertical and horizontal synchronization signals (Vsync, Hsync) and valid data of the display are present, as shown in FIG. 6. ), The start pulse and scanning of the gate driver 24 and the source driver 26 in accordance with the clock (CLK) signal supplied from the receiver 8 and the R, G, B signals input from the interface circuit 2. In addition to supplying clocks, it also supplies digital R, G, and B data.                     

In addition, the timing controller 60 according to the present invention may enable the frame buffer unit 61, the black data unit 62, and the switching unit (MUX) 63 to be driven in the order of an image frame to a reset frame for one frame time. Is further provided.

The frame buffer unit 61 stores R, G, and B image data input for one frame time and outputs the image data during the image frame time, and the black data unit 62 outputs the image data to reset the screen. It outputs black data (reset data) during the reset frame time.

The switching unit (MUX) 63 is connected to the frame buffer unit 61 so as to output image data during the image frame time, which is the first half frame time of one frame, and the second half frame after the one frame. During the reset frame time, which is a time, the black data section 62 is connected to output black data (reset data).

The gate start pulse (GSP), gate shift clock (GSC) and gate output enable (GOE) signals used to control the gate driver 24 and the source driver 26 are controlled by the timing controller 60. R, G, and B data of even and order pairs, which are used to divide source start pulse (SSP), source sampling clock (SSC), load, polarity reverse (POL), and existing data signals. The signal is generated.

The GSP (Gate Start Pulse) serves to inform the start line of the screen, that is, the first (1st) line, among the 1 vertical, and the GSC (Gate Shift Clock) is a thin film transistor configured on the display panel 22. Specify the time that the gate of the (TFT) is turned on (ON), the GOE (Gate Output Enable) serves to control the output of the gate driver 24.

The source start pulse (SSP) informs the start point of the data, that is, the first (1st) pixel, in one horizontal, and the source sampling clock (SSC) latches the data based on the rising and falling edges. LOL (Polarity Reverse) is a signal that informs the polarity to drive the liquid crystal to be positive or negative polarity.

Next, a driving method of the liquid crystal display device using the liquid crystal display device configured as described above will be described.

5 is an output waveform diagram comparing SSC and data of a conventional LCD according to the present invention, and FIG. 7 is a schematic diagram illustrating double-speed driving of the LCD according to the present invention.

8 is a light distribution diagram over time of the present invention.

According to an exemplary embodiment of the present invention, a method of driving a liquid crystal display device includes outputting vertical, horizontal synchronization signals and clock, R, G, and B control signals in an interface circuit 2 and receiving output signals of the interface circuit 2. Outputting image data and black data for driving in the order of image frame → reset frame in the order of one frame time in the timing controller 60 at a double speed, and sequentially inputting the image data and black data from the timing controller 60; And sequentially representing the image and the reset for one frame time in the received liquid crystal module 22.                     

As such, in order to drive the double speed for one frame time, the frequency of the signals output from the timing controller 60 should be doubled in the related art.

However, since the clock frequency and the data signal frequency output from the interface circuit 2 are output in accordance with the 1x speed driving, the frequency is lowered in half as described above after the actual timing controller 60. If the frequency is used as it is in the timing controller 60, it is possible to double the output signal frequency.

In addition, when the image data and the black data are applied for one frame time through the double-speed driving, the image signal is one time, and thus the speed of accepting the existing data is sufficient, and after storing it in the frame buffer unit 61, the source driver When applying to (26), it may be applied at twice the speed.

That is, as shown in FIGS. 5C and 5D, after the image data corresponding to one frame is output in accordance with the SSC signal at the double speed, the switch of the switching unit 63 switches to black data. The black data is output in accordance with the double speed SSC signal.

By this operation, the double speed driving can be performed to enable substantially two frame driving in one frame time, and the image frame and reset frame driving can be performed for one frame time.

That is, since the reset frame is periodically entered between each frame, it is possible to solve the unevenness caused by the external pressure caused in the VA mode.

In addition, as shown in FIG. 8, an image is output during the previous 1/2 frame time of one frame time, so that there is an effect of impulse driving according to time, and thus motion blur is generated when driving a moving image. It can be minimized.

The present invention is not limited to the above embodiments, and includes various forms that can be easily derived by those skilled in the art from the above embodiments.

As described above, the liquid crystal display and the driving method thereof according to the present invention have the following effects.

First, by performing image frame → reset frame driving for one frame time, since the reset frame is periodically entered between each frame, the uneven phenomenon caused by the external pressure caused by the VA mode liquid crystal display device can be solved.

Second, the moving picture correspondence capability of the VA mode is increased.

Claims (6)

Display panel; A liquid crystal module comprising a gate driver and a source driver for driving the display panel; An interface circuit for outputting vertical, horizontal synchronization signals, clocks, and R, G, B control signals; And And a timing controller that sequentially receives the output signals of the interface circuit and sequentially outputs the digital image data and the black data to the liquid crystal module at a double speed to drive an image frame → reset frame for one frame time. The timing controller A frame buffer unit for storing digital image data input from the interface circuit according to the output signals and outputting image data stored during the image frame time of the one frame; A black data unit configured to output digital black data during the reset frame time of the one frame; And The image data is supplied to the source driver during the image frame time which is 1/2 frame time of the 1 frame, and the digital black data is supplied to the source driver during the reset frame time which is 1/2 frame time of the 1 frame. And a switching unit. delete Outputting vertical, horizontal synchronizing signals and clock, R, G, B control signals in an interface circuit; Outputting the digital image data and the black data for driving the image frame to the reset frame at double speed for one frame time by the timing controller receiving the output signals of the interface circuit; And And sequentially expressing the image data and the digital black data for one frame in a liquid crystal module which receives the digital image data and the black data sequentially from the timing controller. Outputting the digital image data and the digital black data at a double speed; Storing digital image data input from the interface circuit according to the output signals through a frame buffer unit built in the timing controller and outputting digital image data stored during the image frame time of the one frame; Outputting digital black data during the reset frame time of the one frame through the black data unit embedded in the timing controller; And The reset frame time, which is 1/2 frame time of the 1 frame, while supplying the digital image data to the liquid crystal module during the image frame time which is 1/2 frame time of the 1 frame by using a switching unit built in the timing controller. And supplying the digital black data to the liquid crystal module. delete delete The method of claim 3, The double speed output of the image data and the black data And a source sampling clock (SSC) at a double speed generated by the timing controller.

Images