KR100209100B1 - Full flash a/d converter - Google Patents

Abstract

According to the present invention, a plurality of comparators for comparing an analog input voltage with each reference voltage, an ultra-short encoder for generating a lower bit based on an output signal of the comparator, and a higher order based on the lower bit generated by the ultra-short encoder A rear end encoder for generating a bit, and means for generating a complement bit of the most significant bit of the lower bits, wherein the rear end encoder generates or suppresses the upper bit only in response to the most significant bit and the complement bit. It relates to a parallel comparative A / D converter comprising a means for.

Description

Parallel Comparative A / D Converter

1 is a block diagram of a conventional parallel comparative A / D converter.

2 is a main block diagram of the A / D converter shown in FIG.

3 is a main block diagram of another conventional parallel comparative A / D converter.

4 and 5 are block diagrams showing the operation of the circuit portion shown in FIG.

6 is a block diagram of a parallel comparative A / D converter according to a first embodiment of the present invention.

7 (a) is a block diagram of the A / D converter shown in FIG.

FIG. 7 (b) shows a table in the circuit section shown in FIG. 7 (a).

8 is a block diagram of another part of the A / D converter shown in FIG.

9, 10 and 11 are block diagrams showing the operation of the circuit portion shown in FIG.

12 is a main block diagram of a parallel comparative A / D converter according to a second embodiment of the present invention.

13 (a) and 13 (b), 14 (a) and 14 (b) show tables in which the circuit portion shown in FIG. 12 operates.

15 is a main block diagram of a parallel comparative A / D converter according to a third embodiment of the present invention.

16 (a), 16 (b), 17 (a), and 17 (b) show a table in which the circuit portion shown in FIG. 15 operates.

18 is a main block diagram of a parallel comparative A / D converter according to a fourth embodiment of the present invention.

19 (a) and 19 (b), 20 (a) and 20 (b) are tables showing the operation of the circuit portion shown in FIG.

21 is a main block diagram of a parallel comparative A / D converter according to a fifth embodiment of the present invention.

22 and 23 are main block diagrams of an error detection circuit used in the parallel comparative A / D converter shown in FIG.

24 is a main block diagram of an error detection circuit used in the parallel comparative A / D converter shown in FIG.

25 (a), 25 (b), 26 (a), 26 (b) and 27 show tables in which error detection and correction circuits operate.

28 is a main block diagram of a parallel comparison type according to the sixth embodiment of the present invention.

29 (a), 29 (b) and 29 (c) are tables showing the operation of the circuit unit shown in FIG.

30 is a main block diagram of a parallel comparative A / D converter according to a seventh embodiment of the present invention.

31 (a), 31 (b) and 31 (c) are tables showing the operation of the circuit portion shown in FIG.

32 is a main block diagram of a parallel comparative A / D converter according to an eighth embodiment of the present invention.

33 is a table showing a form in which the circuit portion shown in FIG. 32 operates.

34 is a main block diagram of a parallel comparative A / D converter according to a ninth embodiment of the present invention.

35 is a table showing a form in which the circuit portion shown in FIG. 34 operates.

36 is a main block diagram of a parallel comparative A / D converter according to a tenth embodiment of the present invention.

37 to 40 are block diagrams illustrating the generation of glitches in the circuit portion shown in FIG. 36;

* Explanation of symbols for main parts of the drawings

1: reference voltage divider 2: comparator group

3: end gate group 7: error suppression circuit

12: comparator group 14: encoder block

15: encoder 16: error suppression circuit

23: Andgate group 24: Encoder

40: error detection circuit 50: error detection circuit

60: error detection circuit 92: comparator group

93: differential circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel comparison type A / D converter, and in particular, it can be suitably designed as a large scale integrated circuit (LSIC) to convert a high definition television signal with a frequency of 50 MHz or more into a digital signal at high speed. And a full flash A / D converter.

A conventional parallel comparative A / D converter will be described in detail below with reference to FIGS. 1 to 5 of the accompanying drawings.

Japanese Patent Laid-Open No. 62 (1987) -32724, for example, introduces a parallel comparative A / D converter capable of operating at high speed while suppressing digital errors.

1 is a parallel comparison type A / D including a reference voltage divider 1 made up of a plurality of series connection resistors having the same resistance value and connected between terminals Vra and Vrb supplied with different voltages by a predetermined potential. A schematic diagram of a transducer, wherein the reference voltage divider (1) is located between the resistors and the 2 ⁿ reference potential points (VR _{1 to} VR _x ) respectively connected to the 2 ⁿ comparators of the comparator group (2). The voltage at the reference potential points VR _{1 to} VR _x is compared with the analog input signal supplied from the input terminal Vin. The output signal from the comparator group 2 is supplied to two encoders 4 and 5 via the AND gate group 3, and the output signal is converted into a digital signal based on the level of the analog input signal. .

If the parallel comparative A / D converter is assumed to be an 8-bit A / D converter, 256 comparators are divided into four blocks and 256 end gates are divided into four blocks, as shown in FIG. As described above, each of the AND gate blocks 3A to 3D includes 64 AND gates A1 to A64. The output signals of the comparators C1 to C64 (not shown) are two-phase buffers P1 to P64 which generate two output signals of positive and inverse phases through the respective input terminals # 1 to # 64. For example, a positive phase output signal is supplied from the buffer Pi to each of the AND gates Ai of the second and gate blocks 3B, and an antiphase output signal is supplied from the buffer Pi + 1. The polarity of the input terminals of the comparators is reversed from that shown in FIG. The output signals of the AND gates A1 to A64 are wired OR circuits on the seven bit lines SUP and D5 to D0 of the second ultra-short encoder blocks 4B via the distribution amplifiers B1 to B64. Each WOR circuit consists of a switching transistor, for example, while the WOR circuit is arranged as indicated by 1 in the connection diagram of FIG. 2 (b).

As shown in FIG. 2 (a), each of the four AND gates constitutes one unit, and the D5 to D2 bits of the lower 6 bits of each unit are shared by the four AND gates. The most significant bit line SUP of the encoder block 4B includes three AND gates A1 to A3 of the first and eighth units 3e and 3l among the second to fourth and fourth block 3B to 3D. The most significant bit output signals from the three AND gates A30 to A32 are supplied.

The third and fourth encoder blocks 4C and 4D are configured in the same manner. In the first encoder block 4A, the WOR circuit is not arranged on the SUP line, while each WOR circuit has six bit lines D5 to D0. And the WOR circuit on the SUP line in FIG. 2 (b) is indicated by 1 ^* .

3 shows another conventional parallel comparative A / D converter, and as shown in FIG. 3, the 6-bit output signals D5 to D0 of the ultra-short encoder blocks 4A to 4D are connected to the AND gate and the inverter, respectively. The output signals D5 to D0 from the second to fourth encoder blocks 4B to 4D are supplied to the lower bit lines D5 to D0 of the rear end encoder 5 via the configured error suppression circuits 6A to 6D. ) Is applied to the upper bit lines D7 and D6, and the uppermost bit output signal SUP of the encoder blocks 4B to 4D is supplied to the upper bit lines D7 and D6 so that the upper two bits D7 and D6 are supplied. Is generated.

The output signals SUP and D5-D0 of the third encoder block 4D (not shown) are applied to the most significant bit line D7.

The output signal SUP of the first encoder block 4A is used as an overflow signal, and the error prevention circuit 6B-6D to which the output signals SUP of the second to fourth encoder blocks 4B-4D correspond. In addition to the power supply, the power supply is also supplied to the adjacent error suppression circuits 6A-6C.

The output signals of the bit lines D7-D0 of the encoder 5 are transmitted to each output terminal via an output inversion circuit 7 composed of exclusive oragates.

When the input voltage Vin is supplied from the conventional parallel comparative A / D converter, the output signal from the first to the i-th comparator becomes high, and the comparator is from the (i + 1) th to the last. The output signal of becomes low, and only the output signal of the i-th AND gate becomes high at the level change point. As the high output signal from the i-th AND gate is supplied to the encoder, a corresponding binary code is generated at the level change point.

When the slew rate of the input signal Vin goes high, the comparators cannot be switched synchronously to the input signal, so the H and L levels are increased near the level change point of the comparator array.

HHLH ^* LLL...

It may have an irregular distribution such as If a binary code of such an irregular level pattern is supplied to the AND gate group 3, since two Hs are supplied to the encoder 4, a very large sparkle is generated based on the position where such an irregular pattern occurs. FF is output if an error pattern H ^* occurs between 7F and 80 in hexadecimal representation.

In order to prevent the occurrence of such an error, the output signal SUP of the second to fourth encoder blocks 4B-4D is supplied to the error suppression circuits 6A-6D.

For example, as shown in FIG. 4, when an irregular pattern is generated near the point where the D5 bit is changed in one AND gate block, the output signals of the AND gates A31 and A32 become H and H ^* , respectively. The output codes generated by the AND gates A31 and A32 are as follows:

D5 D0

Output code generated by AND gate (A31): 011110

Output code generated by the AND gate (A32): 100000

Since the D5 bit is suppressed by the WOR circuit on the SUP line to generate the original output code 11110, an error of 16 LSB or more is suppressed and an error for the lower 5 bits (D4-D0) is also suppressed.

Further, as shown in FIG. 5, for example, when an irregular pattern is generated between adjacent end blocks 3A and 3B, and the output signals of the AND gates A63 and A1 become H and H ^* , respectively, the AND block 3A. Lower 6 bits (D5-D0) are suppressed, and upper bits (D7, D6) are also suppressed if the irregular pattern does not exceed 32 LSB.

According to the conventional A / D converter, all output signals of the lower 6 bits + 1 bit are wired or processed to generate the lower 2 bits, so that the WOR circuit on the upper bit lines D7 and D6 of the rear end encoder 5 is used. The number of sources is 16, and the number of sources of the WOR circuit on the six bit lines D5-D0 is 32 in the ultra-short encoder blocks 4A-4D. Since the output logic amplitude of the emitter side of the WOR circuit is smaller than the input logic amplitude of the base side, a large amplitude is required for the drive of each WOR circuit, and the time required for reaching the desired amplitude becomes longer.

Since the load capacitance of the most significant bit line SUP of each ultra-short encoder block 4A-4D is considerably larger than that of other bit lines, the limit of delay, that is, the limit of processing speed, is lowered.

A first object of the present invention is to provide a parallel comparative A / D converter having a simple encoder and capable of suppressing the occurrence of digital sparks.

The second object of the present invention is parallel comparison, in which an encoder can generate a complement bit of a trailing least significant bit and detect the predetermined error pattern supplied to the encoder by processing the complementary bit and the trailing least significant bit without increasing the delay time. It is to provide a type A / D converter.

It is a third object of the present invention to provide a parallel comparative A / D converter capable of detecting a predetermined error pattern supplied to an encoder without increasing the delay time.

A fourth object of the present invention is to use an encoder for generating odd and even parity bits for a plurality of information bit signals, and parity check on information bits using parity bits to easily detect a predetermined error pattern applied to the encoder. It is to provide a parallel comparative A / D converter with an error detection circuit for performing.

A fifth object of the present invention is to provide an all-parallel comparative A / D converter capable of easily detecting a predetermined error pattern or bit random error applied to an encoder and correcting such an error.

A sixth object of the present invention is to provide an all-parallel comparative A / D converter capable of reducing the number of elements to be added, enabling high-speed operation, and suppressing sparkle errors caused by the metastable state of the comparator.

A seventh object of the present invention is to provide a parallel comparative A / D converter which is simple in construction and capable of suppressing glitch (digital error) generated in an encoder for encoding a supplied signal into a binary code.

According to the present invention, a plurality of comparators for comparing an analog input voltage with each reference voltage, an ultra short encoder for generating a low bit based on an output signal of the comparator, and a low bit generated by the ultra short encoder A rear end encoder for generating an upper bit, and means for generating a complement bit of the most significant bit of the lower bits, wherein the rear end encoder generates the upper bit only in response to the most significant bit and the complement bit. A parallel comparative A / D converter is provided, comprising means for suppressing.

Further, according to the present invention, a plurality of comparators for comparing an analog input voltage with each reference voltage, and an encoder for generating a plurality of comparisons based on an output signal of the comparator, the second and second of the plurality of bits. The encoder including means for generating an additional bit by OR processing the AND logic of the three low-bit complementary bits and the first low-bit complementary bit of the plurality of bits; And a logic circuit for ANDing the additional bit and the complement bit of the additional bit, and means for detecting an error pattern in an output signal of the comparator based on an output signal of the logic circuit. A comparative A / D converter is provided.

Further, according to the present invention, a plurality of comparators for comparing the analog input voltage with each reference voltage, and an encoder for generating a plurality of information bits based on the output signal of the comparator, each corresponding to each of the information bits The encoder comprising means for generating a plurality of pairs of complementary bit signals, the encoder comprising a logic synthesis circuit coupled to receive the pair of bit signals, and generating an output in response to the pair of bit signals. A parallel comparative A / D converter is provided.

According to the present invention, a plurality of comparators for comparing an analog input voltage with each reference voltage and an encoder for generating a plurality of bits based on an output signal of the comparator, the second lower bit of the plurality of comparisons An error pattern in the output signal of the comparator based on an encoder including means for generating a complement bit of the logic bit, an AND circuit for the complement bit and the second lower bit, and an output signal of the logic circuit. A parallel comparative A / D converter is provided, comprising means for detecting.

Further, according to the present invention, a plurality of comparators for comparing the analog input voltage with each reference voltage, and an encoder for generating a plurality of information bits based on the output signal of the comparator, the radix for the plurality of information bits And an encoder including means for generating even parity bits, and an error detection circuit for detecting an error pattern in an output signal of the comparator based on the radix, even parity bits, and information bits. A parallel comparative A / D converter is provided.

In addition, according to the present invention, a plurality of comparators for comparing the analog input voltage with each reference voltage, a differential circuit for detecting a difference between the output voltage of each of the comparators and every other comparator, and the differential circuit An encoder means for generating a binary code based on an output signal, for generating a [m-1] bit binary code in response to a (2m-1) th output signal (m is a natural number) of said differential circuit. The encoder means including a first encoder and a second encoder for generating an [m] -bit binary code in response to the 2 m-th output signal of the differential circuit, and finally outputting the output signals of the first and second encoders. A parallel comparative A / D converter is provided that includes a synthesis circuit for synthesis into binary code.

And, according to the present invention, a plurality of comparators for comparing the analog input voltage with each reference voltage, a differential circuit for detecting a difference between the output voltage of each of the comparators and every other comparator and the differential circuit An encoder means for generating a binary code based on an output signal, for generating a [m-1] bit binary code in response to a (2m-1) th output signal (m is a natural number) of said differential circuit. The encoder means including a first encoder and a second encoder for generating an [m] bit code in response to the 2 m-th output signal of the differential circuit, and a final binary output signal of the first and second encoders. I (i is a natural number) bit counted from the least significant bit of the binary code generated in response to the (2m-1) th output signal of the differential circuit, and i First rain When the lower bit is 0 and the (i + 1) th bit of the binary bit is 1, the (2m-1) th output signal of the differential circuit is the (i) of the first encoder. A parallel comparison type A / D converter is provided which is arranged to be supplied to the (i + 1) th bit line of the second encoder rather than the +1) th bit line.

Further, according to the present invention, a comparator of a first comparator N (N ≥ 2) comparator block, each of which is composed of a plurality of comparators, an upper bit encoder, a lower bit encoder, and a comparator of the first comparator block. An upper bit control and gate block connected to an output terminal and selecting one block of the plurality of comparator blocks depending on the level of an analog input signal to control the upper bit encoder. A parallel comparison type A / D conversion device is provided, each of which is connected to an output terminal and constitutes a first to Nth low bit control and gate block for controlling the low bit encoder.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the invention according to the accompanying drawings in which like parts are designated by like reference numerals.

6 is a block diagram of a parallel comparative A / D converter according to a first embodiment of the present invention, and FIGS. 7A and 8 are parallel comparative A / D shown in FIG. The other part of the transducer is shown, and the same reference numerals or unit digits refer to the same components as those of FIGS. 6 and 7 (a) and 8 corresponding to those shown in FIGS. 1 to 3. The detailed description is omitted by the reference numeral.

In FIG. 6, the parallel comparative A / D converter is composed of 256 comparators and 2 comparator blocks 2A-2D divided by 256 2-phase buffers, and each comparator block 2A-2D is As shown in FIG. 7 (a), it consists of 64 comparators C1-C4 and 64 two-phase buffers P1-P64. The output signal from the comparator blocks 2A-2D is supplied to the AND gate blocks 13A-13D, and the output signal of each of the AND gate blocks 13A-13D is supplied to the first encoder 14A-14D. The output signals of the first stage encoders 14A-14D are sequentially supplied to the rear stage encoder 15.

As shown in Fig. 7 (a), each of the end gate blocks 13A-13D has 64 end gates A1-A64, and Japanese Patent Application No. 1 (1989) -155846, which is a corresponding application of the present application. As shown in Fig. 2, the positive phase output signal of the (4n + 1) th buffer P4n + 1 is supplied to the (4n + 1) th AND gate A4n + 1 of each of the AND gate blocks 13A-13D. The anti-phase output signal from the (4n + 4) th buffer P4n + 1 is supplied to the (4n + 1) th AND gate A4n + 1 and the (4n + 4) th AND gate A4n It is also supplied to +4). Further, the (4n + 2) and (4n + 3) th buffers (P4n + 2, P4n +) for the (4n + 2) and (4n + 3) th AND gates A4n + 2 and A4n + 3. In addition to supplying the positive phase output signal from (3), the antiphase output signals from the (4n + 3) and (4n + 4) th buffers (P4n + 3, P4n + 4) are supplied, respectively (4n). The antiphase output signal from the +2) th buffer P4n + 2 is not supplied anywhere.

Each ultra-short encoder block 14A-14D additionally has two bit lines D1b equivalent to the bit line D5N for the complement of the most significant bit D5 of the lower bits and the lower two bit lines D1a and D0a. And D0b, and the bit lines D1a and D0a; D1b and D0b are disposed on both layers of each ultra-short encoder block in order to reduce capacitance.

The output signals of the end gates A1 to A64 are connected to each of the bit amplifiers D5, D5N, D4 to D2, D1a, D0a, and D0b, for example, through the distribution amplifiers B1 to B64. It is applied to a predetermined WOR circuit, which is arranged as indicated by 1 in the connection of Fig. 7 (b).

As shown in FIG. 7 (a), each of the four end gates is composed of one unit, and each of the first end gates A1, A5, ..., A29 of the eight units 13e-13l. While the output signal is supplied to the upper bit line D5N, the output signal from the first and second gates A33, A37, ..., A61 among the other eight units 13m-13t becomes the upper bit line D5N. And D4-D2), the number of WOR circuits on the upper bit lines D5, D5N and D4-D2 of the ultra-short encoder block 14B is significantly reduced.

The lower two bits from the eight units 13e-13l are supplied to a predetermined WOR circuit on the bit lines D1a and D0a, while the lower two bits of the other eight units 13m-13t are the other bit lines D1b. Since it is supplied to a predetermined WOR circuit on D0b, the number of WOR circuits on the bit lines D1a, D0a, D0l, D0b is reduced by half.

The output signal of the first and gate A1 of the AND gate block 13B is supplied to the most significant bit line D5N of the encoder block 14B.

The third and fourth encoder blocks 14C and 14D are configured in the same manner, and the output signal of the first and gate A1 of the AND gate block 13B in the first encoder block 14A is the most significant bit line ( While not supplied to D5N), it is employed as an overflow signal and is indicated by 1 ^* as the WOR circuit on the D5N line in FIG. 7 (b).

As shown in FIG. 8, the lower bit lines D1a, D0a; D1b, D0b of the ultra-short encoder blocks 14A-14D are connected to the lower bit lines of the encoder 15 by the respective oragates 01, 00. Commonly connected to D1 and D0, the middle 3 bit lines D4-D2 of the encoder blocks 14A-14D are connected in common to the middle bit lines D4-D2 of the encoder 15. The output signals from the most significant bit line D5 and the complement bit line D5N of each ultra-short encoder block 14A-14D are transmitted through the corresponding error suppression circuits 16A-16D to the bit line D5 of the encoder 15. ) And upper bit lines D7 and D6, and also to adjacent error suppression circuits 16A-16D.

The output signals of the bit lines D7-D0 of the encoder 15 are transmitted to the corresponding output terminals via the output inversion circuit 7.

An operation of the parallel comparative A / D converter according to the first embodiment of the present invention will be described below with reference to FIGS. 9 to 11.

As shown in FIG. 9, the fourth (4n + 1) th AND gate A4n + 1 of each of the AND gate blocks 13A-13D processes the upper bit D5 of the ultra-short encoder blocks 14A-14D. On the other hand, three (4n + 2), (4n + 3), and (4n + 4) th AND gates (A4n + 2, A4n + 3, A4n + 4) process the lower bits (D0, D0). Done.

Therefore, as shown in FIG. 10, in an irregular pattern including every three bits of error bits, digital errors of more than D2 bits are not generated, and thus the encoder in this embodiment is essentially an irregular pattern of the comparator. It is difficult to be affected by the error.

The bit lines D5N of each of the ultra-short encoder blocks 14A-14D are essentially results of OR processing of the output signals of the AND gates A1-A32, and intuitively serve to generate the complement of the bit lines D5. Normally, at least one of the eight bit lines D5 and D5N goes high when any one of the encoder blocks 14A-14D needs to generate an output signal. Therefore, in the WOR circuits on the bit lines D5 and D5N, the upper bits D6 and D7 of the output signal are generated and the number of WOR circuits on the bit lines D6 and D7 is considerably reduced.

Further, as shown in FIG. 11, for example, an irregular pattern is generated in the vicinity of an input signal that is a multiple of 32, and the bit D5 is changed in the end block so that the bit lines D5 and D5N of the encoder blocks 14A-14D. If two of them become H, the D5 or D5N bits located in the direction in which the output code increases (right in FIG. 8) are suppressed by the error suppressing circuits 16A-16D shown in FIG. In this case, unlike the conventional configuration, it is not necessary to distinguish between areas inside and outside the block in the same encoder block in order to suppress errors.

According to the present embodiment, when an irregular pattern including error bits every other 7 bits is generated, the level cannot be accurately defined only by the output signal of the comparator, but the error can be reduced below the level of about 16LSB.

As described above, since the complement bit (D5N) of the most significant bit (D5) of the ultra-short encoder is provided, the bits (D5N, D5) are 0R processed to generate the higher bit, so that the source number is reduced by the WOR circuit for the higher bit. As a result, the logic amplitude can be reduced, and since the number of sources in the WOR circuit for the lower bits is also the same number as the number of sources in the WOR circuit for the upper bits, the signal levels of the upper bits and the lower bits are equal. Can be.

In addition, the load capacity of the parallel comparative A / D converter is also reduced for high speed A / D conversion.

By using the complement bit D5N, the error can be suppressed without distinguishing the outer and inner regions of the ultra-short encoder block.

According to the above-described embodiment, the low end bit is generated in the first encoder, and the most significant bit of the most significant bit is generated in the first stage, and the uppermost bit is generated using the most significant bit of the first stage and the complement bit of the subsequent encoder. Therefore, the parallel comparative A / D converter can have a simple encoder while preventing the occurrence of a digital error (sparkle).

12 to 14 (a) and 14 (b) are diagrams showing a parallel comparative A / D converter according to a second embodiment of the present invention.

FIG. 12 is a block diagram of a parallel comparative A / D converter according to a second embodiment. FIG. 13 (a) and FIG. 13 (b) are views showing a connection of a parallel comparative A / D converter. .

As shown in FIG. 12, the parallel comparison type A / D converter has a comparator group 22 and an end gate group 23. For example, the parallel comparison type A / D converter is a 6-bit A / D converter. The comparator group 22 is composed of 64 comparators C1-C64, while the endgate group 23 is composed of 64 endgates F1-F64. The output signals from the comparators C1-C64 are supplied to the two-phase buffers E1-E64 capable of obtaining output signals in the normal and reverse phases. A positive phase output signal from the buffer Ei and an antiphase output signal of the buffer Ei + 1 are supplied to each of the AND gates Fi, and the output signals of the AND gates F1 to F64 are distributed amplifiers G1 to G64. Is supplied to the WOR circuit on the seven bit lines D5-D0, D ^* of the encoder 24.

The output signals of the two bit lines D1 and D ^* of the encoder 24 are supplied to the AND gate 25.

As shown in FIG. 13 (a) and FIG. 13 (b), each WOR circuit is disposed at a position corresponding to one of the ordinary binary codes on the first to sixth bit lines D5-D0. The seventh bit D ^* is the complement of the second lower bit D1, and the output signals of the same AND gate Fi are not commonly supplied to the respective WOR circuits on the bit lines D ^* and D1. .

The operation of the parallel comparative A / D converter according to the second embodiment will be described below with reference to the fourteenth (a) and the fourteenth (b).

If there is no error included in the output signal of each of the gates, the output of the encoder 24 is the first to sixth bits D5- as shown in the 13th (a) and 13th (b) diagrams. While D0) indicates a normal binary code, the seventh bit D ^* becomes a signal indicating the inversion of the second lower bit D1.

For example, an AND gate Fi, in which a 2-in error occurs, and an output signal from an AND gate Fi + 2 following one stage after the gate, for example, AND gates F1 and F3, are high. When the H output signals of the AND gates F1 and F3 are supplied to the respective WOR circuits on the bit lines D1 and D ^* , the output signals of the encoder 24 in correspondence with the input signals of the AND gate F1. The bit D1 is set to 1, and the output signal of the encoder 24 corresponding to the input signal of the AND gate F3 is set to bit D ^* . Comparing the thirteenth (a) and thirteenth (b) it can be seen that the output pattern of the encoder 24 is different from the normal extraction pattern of the encoder 24.

As shown in FIG. 14 (a) and 14 (b), the output pattern of the encoder 24 corresponding to the input signal of each AND gate Fi also has a normal output in which bits D1 and D ^* are 1s. It is different from the pattern.

In this embodiment, the AND gate 25 acts to AND the bits D1 and D ^* to detect a 2-in error including every other bit, so that such an error increases the delay time. Can be reliably detected by a simple configuration.

Although the parallel comparative A / D converter is a 6-bit A / D converter, the principle of the present embodiment can be applied to A / D converters of other bits.

In addition, the parallel comparative A / D converter can be configured to detect other two-in-one errors, including error bits every three or seven bits.

Also, in the above embodiment, the AND gate 25 is employed to AND process the signal, but any other suitable logic circuit can be used to achieve the same result.

As described above, since the complement bit of the second low bit is generated by the encoder and the complement bit and the second low bit are ANDed, the parallel comparison type A / D converter increases the delay time of a predetermined error pattern supplied to the encoder. It can be easily detected without.

15 to 17 (a) and 17 (b) are diagrams showing a parallel comparative A / D converter according to a third embodiment of the present invention.

FIG. 15 is a block diagram showing the parallel comparative A / D converter according to the third embodiment, and FIG. 16 (a) and FIG. 16 (b) show the connection of the parallel comparative A / D converter.

As shown in FIG. 15, the parallel comparison type A / D converter has a comparator group 22 and an end gate group 23. For example, if the parallel comparison type A / D converter is a 6-bit A / D converter, The comparator group 22 is composed of 64 comparators C1-C64, and the AND gate group 23 is composed of 64 endgates F1-F64. The output signals of the comparators C1-C64 are applied to the two-phase buffers E1-E64 capable of generating output signals in the positive and reverse phases. A positive phase output signal of the buffer Ei and an antiphase output signal of the buffer Ei + 1 are supplied to each of the AND gates Fi, and the output signals of the AND gates F1-F64 are distributed amplifiers G1-G64. ) Is supplied to the WOR circuit on seven bit lines D5-D0, D ^* of the encoder 24.

As shown in Figs. 16A and 16B, each WOR circuit is disposed at a position corresponding to one of the normal binary codes on the first to sixth bit lines D5-D0.

The seventh bit D ^* is an additional bit for detecting an error and is generated by logically associating the lower three bits D2-D0 according to the following equation (1):

The error detection circuit 40 is composed of an or gate 41 and a three-input and gate 42, and the or gate 41 has third and second lower bit lines D2 and D1 of the encoder 24. The output signal of is supplied, and the output signal of the lowest and additional bit lines D1 and D ^* is supplied to the AND gate 42, and the output signal of the oragate 41 is also supplied.

The operation of the parallel comparison type A / D converter according to the third embodiment will be described below with reference to FIGS. 17A and 17B.

When an error is not included in the input signal of each AND gate Fi, the output signal of the encoder 24 has the first to sixth bits D5 as shown in FIG. 16 (a) and 16 (b). -D0) becomes a signal representing a normal binary code.

The additional bits D ^* generated in accordance with the above formula (1) are repeated in the eighth level period with the same pattern as shown in the sixteenth (a) and the sixteenth (b) diagrams and the following table.

Since the inverting bits D2N-D0N of the lower three bits D2-D0 are given as shown in the above table, the additional bits D generated by the logical operation according to Equation (1) ) Repeats patterns of 1 and 0 in a period of 8 levels.

For example, when a 2-in error occurs and the output signal from the AND gate Fi and the subsequent AND gate Fi + 3 two steps behind this gate, that is, the AND gates F1 and F4, becomes high, the AND gate ( H output signal of F1, F4 is bit line (D2-D0, D) When supplied to the respective WOR circuits, the output signal of the encoder 24 corresponding to the input signal of the AND gate F1 becomes different from the normal output code of the encoder 24 with bits D1 and D0 set to one. .

As shown in FIG. 17 (a) and 17 (b), the output signal from the encoder 24 in response to the input signal of each of the AND gates F2-F60 is different from the normal output code. This error code has lower 3 bits (D2-D0) in which the same pattern is repeated in a period of 8 levels.

The error detection circuit 40 performs a logical operation according to the following equation (2) to add an additional bit (D). Inversion bit (D) Will generate N).

The AND gate 42 serves to process an additional bit D ^* and its inverted bit D ^* N in order to detect a 2-in error including error bits every other bit.

In the above-described embodiment, the 2-in error can be reliably detected without increasing the delay time by the simple configuration consisting of the orifice 41 and the 3-input and gate 42.

The parallel comparative A / D converter described above is a 6-bit A / D converter, but the principle of this embodiment can be applied to A / D converters of other bits.

In addition, in the above embodiment, the error detection circuit 40 composed of the or gate 41 and the AND gate 42 is employed to AND process the circuit, but other suitable logic circuits can be used to obtain the same result.

As described above, the encoder generates additional bits by rounding out the AND logic of the complement bits of the second and third lower bits and the complement of the first lower bits of the plurality of bit signals, and generates the additional bits. Since the additional bits are complemented, the parallel comparison type A / D converter can easily detect a predetermined error pattern applied to the encoder without increasing the delay time.

18 to 20 (a) and 20 (b) are diagrams illustrating a parallel comparative A / D converter according to a fourth embodiment of the present invention.

Fig. 18 shows a parallel comparative A / D converter according to the fourth embodiment in block form, and Figs. 19 (a) and 19 (b) show connection of the parallel comparative A / D converter.

18, the parallel comparison type A / D converter has a comparator group 32 and an end gate group 23, and if the parallel comparison type A / D converter is a 6-bit A / D converter, In this case, the comparator group 22 is composed of 64 comparators C1-C64, and the AND gate group 23 is composed of 64 endgates F1-F64. The output signals of the comparators C1-C64 are applied to the two-phase buffers E1-E64 capable of generating the output signals of the positive phase and the antiphase, and the buffer Ei of each of the end gates Fi. The positive phase output signal and the reverse phase output signal of the buffer Eik + 1 are supplied.

The output signals of the AND gates F1-F64 are supplied to the WOR circuits on the eight bit lines D5-D0, Dp, Dq of the encoders 24 through the distribution amplifiers G1-G64.

As shown in FIG. 19A and FIG. 19B, each WOR circuit is disposed at a position corresponding to 1 of the ordinary binary code on the first to sixth bit lines D5-D0. .

The seventh and eighth bit lines Dp and Dq are odd and even parity bit lines, and the parity bits Dp and Dq are complementary to each other.

The error detection (parity check) circuit 50 is composed of an exclusive NOR gate 51, an exclusive OR gate X 52, and an ora gate 53. The output signal of the bit lines D5-D0 of the encoder 24 is supplied to the XNOR gate 51 and the XOR gate 52, and the output signal of the odd parity bit line Dp is supplied to the XNOR gate 51. do. The output signal of the even parity bit line Dp is supplied to the XOR gate 52, and the output signals of the XNOR 51 and the XOR gate 52 are transmitted via the ora gate 53.

An operation of the parallel comparative A / D converter according to the fourth embodiment will be described below with reference to FIGS. 20 (a) and 20 (b).

If an error is not included in the input signal from each of the AND gates, the output signal of the encoder 24 has the first to sixth bits as shown in FIGS. 19A and 19B. (D5-D0) becomes a signal representing a normal binary code.

The radix and even parity bits (Dp, Dq) are between the first 32 data items and the last 32 data items among the total of 64 data items, and between the first 16 data items and the last 16 data items of each 32 data item group and each 16 data items. 1 and 0 are to be replaced between 8 data items in front of the crowd and 8 data items in the latter.

For example, when a 2-in error occurs and the AND gate and the subsequent AND gate Fi + 2 one step after the AND gate become high, the encoder 245 corresponding to the input signal of the AND gate Fi is turned off. The output signal of is given as shown in FIG. 20 (a) and 20 (b), and is different from the normal output code of the encoder 24.

For example, when the output signals of the AND gates F1 and F3 become high, when the H output signals of the AND gates F1 and F3 are supplied to the respective WOR circuits on the bit lines D1, Dp, and Dq, the AND gate A1 is applied. The output code from the encoder 24 in response to the input signal of is a signal of 1, as shown in Figs. 20 (a) and 20 (b), with only the information bit D1 being the odd and even parity. (Dp, Dq) becomes one.

Since only the output signal from the XNOR gate 51 to which the odd parity bit Dp is supplied by the error detection circuit 50 becomes 1, the odd parity bit Dp detects an error, and the signal representing the detected error. Is output via the oragate 53.

If the output signals of the AND gates F2 and F4 go high, the information bits D1 and D0 of the output code of the encoder 24 corresponding to the input signals from the AND gate F2 become 1 and both parity bits. (Dp, Dq) becomes one.

In this case, since the output signal of the XOR gate 52 to which the even parity bit Dq is supplied becomes 1, the even parity bit Dq detects an error, and the signal representing the detected error is the oragate 53. Is output via

If the output signals of the AND gates F1 and F4 become high, the information bits D1 and D0 of the output code of the encoder 24 corresponding to the input signals of the AND gate F2 become 1 and Both parity bits Dp and Dq become one. In this case, since the output signal of the XOR gate 52 to which the even parity Dq is supplied becomes 1, the even parity bit Dq detects an error.

If an error including an error bit every other bit is generated at the gate Fi of any of the AND gates F3-F62, the error is the odd parity bit Dp or even parity bit in the same manner as described above. It is detected by (Dq).

Since the radix and even parity bits in the above embodiment are mutually complementary, an error including an error bit separated by one bit generated at any end gate can be reliably detected, and even a bit random error is used for parity check. Can be detected.

When an error is detected, the output code is prevented from updating, so that the error code is not output.

In addition, the all-parallel comparative A / D converter can detect an error including error bits two bits apart in the same manner as if the odd or even parity bits are employed alone.

The parallel comparative A / D converter is a 6-bit A / D converter, but the principle of this embodiment can be applied to A / D converters of other bits.

Further, in the above embodiment, the error detection circuit 50 is composed of the XNOR gate 51, the XOR gate 52, and the or gate, but any other various suitable logic circuits can be used to obtain the same result.

As described above, the encoder has an error detection circuit that generates radix and even parity among a plurality of information bit signals and performs parity check of information bits using the parity bits. Therefore, a parallel comparative A / D converter is provided to the encoder. A predetermined error pattern to be applied can be easily detected, and a bit random error can be detected.

A parallel comparative A / D converter according to a fifth embodiment of the present invention will be described below with reference to FIGS. 21 to 24.

21 is a block diagram of a parallel comparative A / D converter according to the fifth embodiment.

As shown in FIG. 21, the parallel comparison type A / D converter includes a comparator group 22 and an end gate group 23, and if the parallel comparison type A / D converter is a 3-bit A / D converter, the comparator The group 22 is composed of eight comparators C1-C8, and the AND gate group 23 is composed of eight AND gates F1-F8.

The output signals of the comparators C1-C8 are applied to the two-phase buffers E1-E8 capable of generating output signals of positive and inverse phases. A positive phase output signal from the buffer Ei and an antiphase signal from the buffer Ei + 1 are supplied to each of the AND gates Fi, and the output signals of the AND gates F1 to F8 are distributed amplifiers G1 to G8. Are supplied to the WOR circuits on the three information bit lines X2-X0 and the complement bit lines Y2-Y0.

The output signals of the information bit lines X2-X0 and the complement bit lines Y2-Y0 are applied to the error detection circuit 60 and the error correction circuit 61.

As shown in FIG. 22, the error detection circuit 60 is composed of three AND gates 63-65 and an oragate 66, and information bits X1-X0 are provided in the AND gates 63-65. And the corresponding complementary bits Y2-Y0 are supplied, and the output signals of the AND gates 63-65 are transmitted through the oragate 66.

FIG. 23 shows another error detection circuit 60A composed of three XOR gates 68-70 and an oragate 71, in which the output signal of the comparator C1 goes low. Is detected as an error, in order to avoid this, the buffer E1 and the AND gate F1 may be separated from each other, and the input signal supplied to the AND gate F1 may be at a fixed high level.

24 shows an error correction circuit 61, in which the upper information bits X2 are supplied to the respective AND gates 73 and 74, and the corresponding complementary bits Y2 are supplied to the AND gates. In addition to 73, the inverting bit is supplied to the AND gate 74.

The median information bit X1 is supplied to each of the AND gates 75 and 76, the corresponding complementary bit Y1 is supplied to the AND gate 75, and the inverting bit is transmitted through the oragate 77. The output signal of the AND gate 73 is supplied to the oA gate 77.

The lower information bit X0 is supplied to the AND gate 78, the corresponding complementary bit Y0 is inverted and supplied to the AND gate 78 through the oragate 79, and the AND to the oragate 79. The output signals of the gates 73 and 75 are supplied.

The AND gates 74, 76, and 78 output the corrected information bits D2, D1, and D0, respectively.

The parallel comparative A / D converter according to the fifth embodiment operates as follows.

As long as the output signal of the comparator group 22 is a normal code, the AND gate (differential circuit) 23 generates a single output signal, and the following equation (3) is established.

For example, an error including an error bit of one bit color is generated so that the output signal of the comparator group 22 deviates from a normal code, for example, the comparators C1-C4 and C6 generate an output signal of 1, and the comparator C5. When -C7, C8 generates an output signal of zero, the output signal of the AND gates F1 (F6) becomes one.

These output signals are supplied to the information bit line X2-X0 and the complement bit line Y2-Y0, and the encoder 24 inverts the X series binary output codes 11 and 101, and the X series binary output codes are inverted. Y-series binary output codes 100 and 10 are generated.

When the output signal of the AND gate F4 is corrected, the output code of the encoder 24 is 11, and when the output signal of the AND gate F6 is corrected, the output code of the encoder 24 is 101.

When an output signal from the AND gates 67 and 64 of the error detection circuit 60 is displayed as follows;

X2 = Y2 = 1, X1 = Y1 = 1

That is, when the information bits X2 and X1 and the corresponding complement bits Y2 and Y1 coincide, it is detected that Equation (3) does not hold and an error is detected accordingly.

In general, when a multi-in error occurs, the output code of the encoder is always 1, so that the corresponding bits of the X information bit group and the Y information bit group are detected to be 1.

When a bit random error occurs, only one of the combined X and Y bit groups may be an error, and in order to detect such an error pattern, the error detection circuit 60A shown in FIG.

Xi = Yi = 0 (i = 0 to 7)

Will be detected. Thus, the condition of whether the corresponding bits of the X and Y bit groups coincide with each other is detected.

In addition, when there is only one bit where an error is detected, the parallel comparative A / D converter according to the present invention can detect the error bit, for example, in which bit combination the original code is composed when such an error occurs. Because it is known, it can be corrected.

When a multi-in error occurs, the comparator group itself is an error, so there is no information to determine the correction bit, but only the place where the error occurs is limited to the vicinity of the part where the input to the encoder is 1 If a nearby code is printed, no problem occurs.

According to the present invention, the error correction circuit 61 corrects the detected error so that its most significant bit is zero.

That is, the AND gates 73 and 74 of the error correction circuit 61 perform a logical operation according to the following equation (4), and the complement bit Y2 corresponding to the higher information bit X2 is multi-in error. In the case of mutual coincidence with each other or the like, the corrected upper information bit D2 becomes zero.

In addition, the AND gates 75 and 76 and the OR gate 77 perform a logical operation according to the following equation (5), and the error that the complement bit Y corresponding to the median information bit X1 is multi-error. If they coincide with each other by, for example, the corrected median information bit D1 is zero.

Then, the AND gate 78 and the oragate 79 perform a logical operation according to the following equation (6), and the lower information bit X0 and the complement bit Y0 corresponding to each other are multi-errored due to an error. If there is a match, the corrected low information bit D1 becomes zero.

In the above embodiment, the bit configuration of the encoder 24 is doubled while the circuit configuration is simplified.

The error detection circuit 60 or 60A and the error correction circuit 61 may be configured to share an AND gate or the like.

The above-described parallel comparative type A / D converter is a 3-bit A / D converter, but the principle of this embodiment can be applied to A / D converters of other bits.

For example, in the case of the parallel comparison type A / D converter, the X series of the information bits of the encoder is configured as shown in FIGS. 25 (a) and 25 (b), and The Y series is realized by replacing 0 and 1 with 1 and 0 in the display, i.e., in FIG. 25 (a) and 25 (b), by inversion of the 25th (a) and 25th (b) degrees.

When an input signal having an error pattern including error bits one bit or two bits apart is supplied to the six-bit encoder, the error is corrected by the error correction circuit as described above, and the corrected code is output. This corrected code and the regular code do not differ from each other as shown in FIG.

로 표시된 차이가 잔존하게 된다.In addition, when an input signal having an error pattern including every three bits of an error pattern is supplied to a six-bit encoder, the corrected code Z5-Z0 is different from the normal code X5-X0. ) And in Figure 26 (b)

The difference indicated by remains.

)가 제27도에 도시된 바와 같이 되어, 8레벨이 주기로 자체적으로 반복하게 된다.And, in case of a multi-in error including error bits of 1 to 16 bits, the difference between the corrected code and the correct code (

), As shown in FIG. 27, the eight levels repeat themselves in cycles.

As described above, when a multi-in error occurs, it is impossible to determine whether the code is correct. However, when the difference is smaller than the interval between input signals supplied to the plurality of encoders, the corrected code is supplied to the encoder. It is located between the maximum and minimum input signals.

When the number of bits of the encoder is increased, the number of gates of the error correction circuit and the fan-in (input) are broken off, and an error in which the number of bits is properly emphasized from the LSB under the premise that a small sparkle cannot be detected. Correction circuits may be employed.

According to the embodiment described above, since the encoder generates a plurality of information bit signals and a plurality of complementary bit signals, the configuration of the parallel comparison type A / D converter is simplified, while the error can be detected and corrected quickly and effectively. have.

28 and 29 (a) to 29 (c) show an all-parallel comparative A / D converter according to a sixth embodiment of the present invention, which is constituted by a 4-bit A / D converter.

28 is a block diagram of a parallel comparative A / D converter according to the sixth embodiment.

As shown in FIG. 28, the parallel comparison type A / D converter has a comparator group 92 and a differential circuit 93, and the comparator group 92 is composed of 16 comparators C1-C16. In addition, the differential circuit 93 is composed of 16 AND gates H1-H6. The output signal of the comparator Cj is supplied to each of the AND gates Hj, and the inverted output signal of the comparator Cj + 2 every other comparator is also supplied from the comparator Cj.

The first and second encoders 94A and 94B have four bit lines DA0-DA3 and four bit lines DB0-DB3, respectively, and the WOR circuit corresponding to the binary code has a bit line DA0-. DA3, DB0-DB3).

The output signal of the second (2m-1) th AND gate (H2m-1, where m is a natural number) of the differential circuit 93 corresponds to the [m-1] binary code in the form of a bit of the first encoder 94A. Supplied to the lines DA0-DA3, and the output signal of the second m-th AND gate H2m of the differential circuit 93 is a bit line of the second encoder 94B in a form corresponding to the [m] binary code. DB0-DB3).

The synthesis circuit 90 is composed of XOR gates 96, end gates 95a, 95b, 95c, and oragates 97a, 97b, 97c.

The output signal of the least significant bit line of the encoders 94A, 94B is supplied to the XOR gate 96, and the second to fourth bit lines DA1-DA3 of the first encoder 94A are supplied to the AND gates 95a, 95b, 95c. Inverted output signal is supplied and output signals of the second to fourth bit lines DB1-DB3 of the second encoder 94B are supplied.

The output signals of the AND gates 95a, 95b, and 95c and the output signals of the lower 3 bit lines DA0-DA2 of the first encoder 94A are applied to the oragates 97a, 97b, and 97c, and the oragates The output signals of (97a, 97b, 97c) are output as the upper three bits (Z1, Z2, Z3) of the synthesis circuit 90, and the output signal of the XOR gate 96 is output as the least significant bit (Z0).

The operation of the parallel comparative A / D converter shown in FIG. 28 will be described below with reference to FIG.

The parallel comparison type A / D converter according to the present invention includes at least one metastable comparator, and in view of this feature, the differential circuit 93 is composed of every other comparator (Cj, Dj +) rather than from an adjacent comparator. The difference between 2) will be detected.

In a normal state, output signals of two adjacent AND gates Hj and Hj + 1 become high, and these H output signals are supplied to the first and second encoders 94A and 94B, respectively.

If the output signal of the (2m-1) th comparator of the comparator group 92 acts as a level change point, the output of the (2m-1) and (2m-2) th AND gates of the differential circuit 93 The signal goes high, and the encoders 94A and 94B generate the [m-2] and [m-1] binary codes, respectively, in response to these two H output signals.

Since the least significant bits DA0 and DB0 of the encoders 94A and 94B are not equal to each other, the least significant bit Z0 output from the XOR gate 96 of the synthesis circuit 90 becomes one. When the second bits DA2 and DB1 of the encoders 94A and 94B are 0 and 1, respectively, or the least significant bit DA0 of the encoder 94A is 1, the second bit Z1 of the synthesis circuit 90 is It becomes 1, and the 3rd and 4th bits Z2 and Z3 are also the same.

Therefore, the synthesis circuit 90 adds the [m-2] and [m-1] binary codes generated by the encoders 94A and 94B, including a carry.

If the output signal of the second m-th comparator of the comparator group 92 acts as a level change point, the output signals of the (2m-2) and second (m-1) -th and-th gates of the differential circuit 93 High, the encoders 94A and 94B generate [m-1] binary codes respectively in response to these two H output signals.

Since the least significant bits DA0 and DB0 of the encoders 94A and 94B are not equal to each other, the least significant bit Z0 output from the XOR gate 96 of the synthesis circuit 90 becomes zero. When the second bits DA1 and DB1 of the encoders 94A and 94B are 0 and 1, respectively, or the least significant bit DA0 of the encoder 94A is 1, the second bit E1 of the synthesis circuit 90 is 1. The third and fourth bits E2 and E3 are also the same.

Therefore, the synthesis circuit 90 adds the [m-1] binary code generated by the encoders 94A and 94B including the carry.

)가 0으로 된다.As shown in FIG. 29 (b) in the normal state, the difference between the output code of the synthesis circuit 90 and the normal binary code (

) Becomes 0.

When the output signal of the comparator Cj + 2 is in a metastable state, the output signal of the AND gate Hj + 1 of the differential circuit 93 becomes high and both sides of the AND gate Hj + 1. The output signals of the two AND gates Hj and Hj + 1 adjacent to are in a metastable state M. According to how the metastable state M is interpreted, three output signals H, HH, and HHH can be generated. In any case, the differential circuit reliably generates an output signal including an H level. The positional information about the metastable comparator is obtained.

)는 제29(a)도에 도시된 바와 같이 주어지게 된다.For example, if only one output signal at the AND gate Hj becomes a difference, the difference between the output code of the synthesis circuit 90 and the normal binary code (

) Is given as shown in Figure 29 (a).

)는 제29(c)도에 도시된 바와 같이 주어지게 된다.In addition, the difference between the output code of the synthesis circuit 90 and the normal binary code (

) Is given as shown in Figure 29 (c).

In this embodiment, the output signals from the encoders 94A and 94B can be used in a limited combination, so that the number of elements of the synthesis circuit 90 is smaller than that of the full adder, making the synthesis circuit 90 considerably simpler. It is also possible to employ a full adder, but the synthesis circuit in the above-described embodiment is very advantageous for applications requiring high speed operation without ripple carry.

Therefore, the parallel comparative A / D converter according to the sixth embodiment can reduce the number of components and enable high-speed operation, thereby preventing sparkle caused from the metastable state of the comparator.

30 and 31 (a) to 31 (c) show a parallel comparative A / D converter according to a seventh embodiment of the present invention.

30 is a block diagram of a parallel comparative A / D converter according to the seventh embodiment.

As shown in FIG. 30, the parallel comparison type A / D converter is composed of a comparator group 103 and a differential circuit 104, and the parallel comparison type A / D converter is formed of the derivative circuit 104. In the binary code of the output signal of the 2m-1) th AND gate (H2m-1), the i-th (i = natural number) bit from the least significant bit and the lower bit than the i-th bit are 0, and binary. When the (i + 1) th bit of the code is 1, the output signal of the AND gate H2m-1 is not supplied to the (i + 1) th bit line DAi + 1 of the first encoder 101A. The first and second encoders 101A, which are supplied to the (i + 1) th bit line DBi + 1 of the second encoder 101B differently from the encoders 94A and 94B shown in FIG. , 101B).

The synthesis circuit 100 is composed of an XOR gate 107, an AND gates 105a, 105b, 105c, and an oragate 106a, 106b, 106c.

The output signals of the least significant bit lines DA0 and DB0 of the encoders 101A and 101B are supplied to the XOR gates 107, and the first to 101th of the first encoders 101A to the AND gates 105a, 105b and 105c. The inverted output signal of the third bit line DA00DA2 is supplied and supplied to the second to fourth bit lines DB1-DB3 of the second encoder 101B.

The output signal of the XOR gate 107 of the synthesis circuit 100 is output as the least significant bit Z0, and the output signal of the least significant bit line DA0 of the first encoder 101A is the first signal of the synthesis circuit 100. It is output as 2 bits (Z1). The output signals of the AND gates 105a, 105b and 105c and the output signals of the lower 3 bit lines DA1-DA3 of the first encoder 101A are supplied to the oragates 106a, 106b and 106c. The output signals of the oragates 106a, 106b, and 106c are output as the upper three bit signals Z2, Z3, and Z4 of the synthesis circuit 90.

Other details of the parallel comparative A / D converter shown in FIG. 30 are the same as those of the parallel comparative A / D converter shown in FIG.

The operation of the parallel comparative A / D converter shown in FIG. 30 will be described with reference to FIG.

)가 증가된다.In the embodiment shown in FIG. 28, in particular, as shown in FIG. 29, the output signal of the differential circuit 93 in which the binary code first becomes 1 in the bit lines DA1-DA3 of the first encoder 94A. Difference in the vicinity of (the fifth, ninth, seventeenth, ....)

) Is increased.

In view of the above features of the embodiment shown in FIG. 28, the encoder 101A according to this embodiment is modified as described above, which is represented as follows:

f (Hn-2, DAi-1) = 1

f (Hn, DAi-1) = 0

f (Hn, DAi-1) = 1

Here, f is a function whose bits correspond to the encoder output values corresponding to the arguments. For example, in the AND gate H5, only the bit line DA1 becomes 0,

f (H5, DA0) = 0,

f (H5, DA1) = 1

It becomes

)가 0으로 된다.Under normal conditions, the difference between the output code of the synthesis circuit 100 and the normal binary code as shown in FIG.

) Becomes 0.

)가 제31(a)도에 도시된 바와 같이 주어지게 된다.If the output signal of the comparator Cj + 2 is metastable and only one output signal is high at the AND gate Hj, the difference between the output code of the synthesis circuit 100 and the regular binary code (

) Is given as shown in Fig. 31 (a).

)가 제31(c)도에 도시된 바와 같이 주어지게 된다.In addition, if the output signals of the three AND gates Hj, Hj + 1 and Hj + 2 are continuously high, the difference between the output code of the synthesis circuit 100 and the regular binary code (

) Is given as shown in Fig. 31 (c).

)가 감소되는 것을 명백하게 알 수 있게 된다.Comparing Figs. 29 (a) to 29 (c) with Figs. 31 (a) to 31 (c), in the embodiment shown in Fig. 30, the sparkle due to the metastable state of the comparator is further increased. Prevented the difference (

It can be clearly seen that) is reduced.

In addition, the synthesis circuit 100 shown in FIG. 30 may be combined with the echoder shown in FIG.

32 and 34 show parallel comparative A / D converters according to the eighth and ninth embodiments of the present invention, respectively.

Although the principle of the present invention is applied to the 4-bit parallel comparative A / D converter in the sixth and seventh embodiments described above, the present invention can also be applied to the six-bit parallel comparative A / D converter. Fig. 33 shows such a 6-bit parallel comparative A / D converter. The encoders 110A and 110B of the parallel comparison type A / D converter shown in FIG. 32 are configured as shown in FIG. 33, while the encoders of the parallel comparison type A / D converter shown in FIG. 120A and 120B are configured as shown in FIG.

In each of the eighth and ninth embodiments, the circuit configuration increases in size as the number of bits increases, and the parallel comparison type A / D converters according to the eighth and ninth embodiments are provided in the sixth and seventh embodiments. The parallel comparative A / D converter operates in the same form to provide the same characteristics.

The principles of the present invention are also applicable to serial / parallel A / D converters with multiple upper and lower analysis stages.

According to the above embodiment, the differential circuit detects every other difference between the output signals of the comparators, and the first encoder corresponds to the [m-1] corresponding to the (2m-1) th output signal of the differential circuit. While generating a binary code, the second encoder generates an [m] binary code corresponding to the second m-th output signal of the differential circuit, and the output signals of the first and second encoders are the final binary. Is coupled to the code. Therefore, the parallel comparison type A / D converter is made up of a small number of components, enabling high-speed operation, and preventing sparkle due to the metastable state of the comparator.

FIG. 36 is a block diagram of a parallel comparative A / D converter according to a tenth embodiment of the present invention. The parallel comparative A / D converter shown in FIG. 36 is a higher bit encoder and a lower bit. And a gate block for controlling these encoders. The polarity of the input signal supplied to the comparator is opposite to that of the comparators of the first to seventh embodiments.

As shown in FIG. 36, the parallel comparison type A / D converter includes an input terminal IN to which an analog input signal is supplied, and a first comparator block 130 to an Nth comparator block 131 (N≥2, For example, N = 3, and the first comparator 130 is composed of the comparators 130a-130d, and is composed of the Nth comparator blocks 131a-131d. The parallel comparison type A / D converter is composed of, for example, first to twelfth resistors R1 to R12 connected in series with the same resistance, and the resistors are connected between terminals VU and VL. In addition, they are interconnected through junctions P1-P12 where other reference voltages are generated.

The input terminal IN is connected to the input terminal in one phase of the comparators 103a and 130d of the first comparator block 130 and the comparators 131a to 131d of the Nth comparator block 131, and the junction point P1. -P12 is connected to the other input terminal in the inverse phase of these comparators 130a-139d. The parallel comparable A / D converter is, for example, of the comparator 131d of the AND gate 133a connected to the output terminal of the comparator 130d of the first comparator block 130 and the N-th comparator block 131. The upper bit control and gate block 133 may further include an upper bit control and gate block 133 including an AND gate 133c connected to the output terminal. The upper bit control and gate block 133 may further include a first comparator block (3) according to the supplied analog input signal. 130 or the N-th comparator block 131 is selected to connect the selected comparator block to the higher bit encoder 134. An output terminal of the first comparator block 130 is connected to the first lower bit control and gate block 135 including the AND gates 135a to 135e, and an AND gate to the output terminal of the N-th comparator block 131. The Nth lower bit control and gate block 136 (for example, N = 3) consisting of 136a-136c is connected. The lower bit encoder 137 is controlled by the output signals of the first lower bit control and gate block 135 and the Nth lower bit control and gate block 136. The upper and lower bit encoders 134 and 137 include switching transistors Q1 to Q11 and digital output terminals D1 (MSB) to D4 (LSB).

The parallel comparison type A / D converter configured as described above is operated as follows: When the level of the analog input signal applied to the input terminal In is higher than the reference voltage of the junction point P4, the first comparator block 130 The output signal of one phase becomes high from the comparators 131a to 130d, and the output signal of the AND gate 113a of the upper bit control and gate block 133 also becomes high, and accordingly, the first comparator block ( 130 is selected. Therefore, since the switching transistors Q1 and Q2 of the higher bit encoder 134 are turned on, the digital output terminals D1 (MSB) to D4 (LSB) generate an output signal of 1100.

When the analog input signal level applied to the input terminal In is increased above the reference voltage at the junction point P3, the output signal of the comparator 130c of the first comparator block 130 and the first lower bit control and gate block The output signal of the AND gate 135c of 135 becomes high. Therefore, when the switching transistor Q3 of the lower bit encoder 137 is turned on, an output signal of 1101 is generated at the digital output terminals D1 (MSB) to D4 (LSB).

In addition, when the analog input signal level applied to the input terminal In is further increased above the reference voltage of the junction point P2, the output signal of the comparator 130d of the first comparator block 130 and the first lower bit control end The output signal of the AND gate 135b of the gate block 135 goes high. Therefore, when the switching transistor of the lower bit encoder 137 is turned on, the output signal of 1110 is generated at the digital output terminal D1 (MSB) and the AND gate 135c is turned off.

When the analog input signal level applied to the input terminal In is further increased above the reference voltage at the junction point P1, the output signal and the first lower bit control end of the comparator 130a of the first comparator block 130 are increased. The output signal of the AND gate 135a of the gate block 135 becomes high. Therefore, when the switching transistors Q5 and Q6 of the lower bit encoder 137 are turned on, an output signal of 1111 is generated at the digital output terminals D1 (MSB) to D4 (LSB) and the AND gates 135b and 135c are simultaneously generated. Is turned off.

It is assumed that the level of the applied input signal is near the junction points P9-P12 and the Nth comparator block (for example, N = 3) is selected.

When the analog input signal level applied to the input terminal In exceeds the reference voltage at the junction point P12, the output signal of the comparator 131d and the higher bit control and gate block 133 of the N-th comparator block 131. ), The output signal of the comparator 133c becomes high. Therefore, when the switching transistor Q7 of the upper bit encoder 134 is turned on, an output signal of 100 is generated at the digital output terminals D1 (MSB) to D4 (LSB).

When the analog input signal level applied to the input terminal In is further increased above the reference voltage at the junction point P11, the output signal of the AND gate 136c of the Nth low-bit control AND gate 136 becomes high. do. Therefore, when the switching transistor Q8 of the lower bit encoder 137 is turned on, an output signal of 101 is generated in the digital output terminals D1 (MSB)-D4 (LSB).

When the level of the analog input signal supplied to the input terminal In is further increased above the reference voltage of the junction point P10, the output signal of the AND gate 136c of the Nth lower bit control AND gate 136 is Goes high. Therefore, when the switching transistor Q9 of the lower bit encoder 137 is turned on, 110 output signals are generated at the digital output terminals D1 (MSB) to D4 (LSB).

When the level of the analog input signal supplied to the input terminal In is further increased above the reference voltage of the junction point P9, the output signal of the AND gate 136a of the N-th lower bit control AND gate 136 becomes Goes high. Therefore, since the switching transistors Q10 and Q11 of the lower bit encoder 137 are turned on, an output signal of 101 is generated in the digital output terminals D1 (MSB) to D4 (LSB).

The upper bit encoder 134 is controlled by the output signal of the upper bit control and gate block 133, and the lower bit encoder 137 controls the first lower bit control and gate block 135 or the Nth lower bit control. Since it is controlled by the output signal of the AND gate block 136, the all-parallel comparison type A / D converter can be easily configured as described below, and can prevent the occurrence of glitches. The parameter N is not limited to 3 but may be N ≧ 2. If the first and Nth lower bit control and gate blocks 135 and 136 are controlled by the output signal of the upper bit control and gate block 133, the first lower bit control and gate block 135 or the Nth block is controlled. The first lower bit control and gate block 136 is selected for the selected first comparator block 130 or the Nth comparator block 131. Therefore, the difference (digital error) to the true digital output signal can be reduced as much as possible.

The occurrence of a digital error (difference of true value = glitch) when two level change points are generated is described below with reference to FIG. When the level of the analog input signal supplied to the input terminal In corresponds to the reference voltage of the junction point P4, the input voltage according to the reference voltage of the junction point P1 is changed by the low speed operation of the comparator 130a. If held at 130a), the output signals of comparators 130a and 130d go high. Accordingly, the output signals of the AND gates 135a and 133a are all high, and the switching transistors Q1, Q2, Q5, and Q6 are activated. The digital output terminals D1 (MSB) -D4 (LSB) generate an output signal of 1111, which is an error every three steps or less (ignored) from the value of 1100.

38 shows another example of the form in which the glitch is produced. As shown in FIG. 38, when the level of the analog input signal supplied to the input terminal In corresponds to the reference voltage of the junction P10, the input voltage according to the reference voltage of the junction P7 is applied to the comparator. If it is maintained, the switching transistor Q12 is turned on, and the digital output terminals D1 (MSB) to D4 (LSB) generate 111 output signals every other stage or less.

In the examples of FIGS. 37 and 38, the first and Nth lower bit control and gate blocks 135 and 136 are not controlled by the output signal of the upper bit control and gate block 133.

In FIG. 39 and FIG. 40 showing another example of the form in which the glitch is generated, the first and Nth lower bit control and gate blocks 135 and 136 are connected to the output signal of the upper bit control and gate block 133. Is controlled by

As shown in FIG. 39, when the level of the analog input signal supplied to the input terminal In corresponds to the reference voltage of the junction P4, the input voltage corresponding to the reference voltage of the junction P1 is a comparator. If it is maintained in the comparator 130a by the low speed operation of 130a, the digital output terminals D1 (MSB) -D4 (LSB) generate the output signal of 1111 every three steps or less from the true value.

As shown in FIG. 40, when the level of the analog input signal supplied to the input terminal In corresponds to the reference voltage of the junction P10, the input voltage according to the reference voltage of the junction P7 is a comparator. If is maintained at, the output signal from the AND gate 133b of the upper bit control AND gate block 133 goes low to turn off the switching transistor Q12. The digital output terminals D1 (MSB) -D4 (LSB) generate 110 output signals every other step from the true value, so that the glitch is generated less than the glitch generated in the example shown in FIG.

The parallel comparative A / D converter shown in FIG. 36 is constituted by a 4-bit A / D converter, but may also be applied to, for example, a 16-bit or 3-bit parallel comparative A / D converter in the present invention.

According to the embodiment shown in FIG. 36, the parallel comparative A / D converter has an upper control and gate block and a lower control and gate block.

Therefore, the parallel comparison type A / D converter does not require a conversion circuit composed of XOR gates as in the conventional parallel comparison type A / D converters, so that the parallel comparison type A / D converter is relatively simple in configuration and generates glitch. Can be reduced.

If the lower bit control and gate block is controlled by the upper bit control and gate block, the difference with respect to the true digital output signal is minimized.

Referring to the accompanying drawings, preferred embodiments of the present invention, the present invention is not limited to the above embodiments, various changes and modifications as described in the appended claims without departing from the spirit or perspective of the present invention Of course it is possible.

Claims (11)

A plurality of comparators for comparing the analog input voltage with each reference voltage, an ultra-short encoder for generating a lower bit based on the output signal of the comparator, and an upper bit based on the lower bit generated by the ultra-short encoder And a means for generating a complement bit of the most significant bit of the lower bits, the latter encoder having means for generating or suppressing the higher bit in response to only the most significant bit and the complement bit. Parallel comparison type A / D converter comprising a. A plurality of comparators for comparing an analog input voltage with each reference voltage, and an encoder for generating a plurality of bits based on an output signal of the comparator, the complementary bits of the second and third lower bits of the plurality of bits; The encoder including means for generating an additional bit by OR processing an AND logical to a complement bit of a first lower bit of the plurality of bits, the additional bit and the additional bit And a means for detecting an error pattern in an output signal of the comparator based on an output signal of the logic circuit, and a logic circuit for AND processing the complement bit of the circuit. A plurality of comparators for comparing the analog input voltage with each reference voltage, and an encoder for generating a plurality of information bits based on the output signal of the comparator, the plurality of complementary bit signals respectively corresponding to each of the information bits The encoder comprising means for generating a pair, and a logic synthesis circuit coupled to receive the pair of bit signals and for generating an output in response to the pair of bit signals. / D converter. A plurality of comparators for comparing the analog input voltage with each reference voltage, and an encoder for generating a plurality of bits based on the output signal of the comparator, for generating a complement bit of the second lower bit of the plurality of bits. Means for detecting an error pattern in the output signal of the comparator based on an output signal of the encoder, the encoder including a means, a logic circuit for processing the complementary bit and the second lower bit, and an output signal of the logic circuit. Parallel comparative A / D converter, characterized in that. A plurality of comparators for comparing the analog input voltage with each reference voltage, and an encoder for generating a plurality of information bits based on the output signal of the comparator, generating odd and even parity bits for the plurality of information bits. And an error detection circuit adapted to detect an error pattern in an output signal of a comparator based on the radix and even parity bits and the information bits. A plurality of comparators for comparing the analog input voltage with each reference voltage, a differential circuit for detecting a difference between the output voltages of each of the comparators and every other comparator, and a binary based on the output signal of the differential circuit. An encoder means for generating a code, comprising: a first encoder for generating a [m-1] bit binary code in response to a (2m-1) th output signal of the differential circuit (m is a natural number) and the differential circuit The encoder means including a second encoder for generating an [m] -bit binary code in response to the 2 m-th output signal of < RTI ID = 0.0 >, < / RTI > and for synthesizing the output signals of the first and second encoders into a final binary code. Parallel comparison type A / D converter comprising a synthesis circuit. A plurality of comparators for comparing the analog input voltage with each reference voltage, a differential circuit for detecting a difference between the output voltages of each of the comparators and every other comparator, and a binary based on the output signal of the differential circuit. An encoder means for generating a code, comprising: a first encoder for generating a [m-1] bit binary code in response to a (2m-1) th output signal of the differential circuit (m is a natural number) and the differential circuit The encoder means including a second encoder for generating an [m] bit code in response to the 2 m-th output signal of < RTI ID = 0.0 > and < / RTI > a synthesis circuit for combining the output signals of the first and second encoders into a final binary code. And i (i is a natural number) bit counted from the least significant bit of the binary code generated in response to the (2m-1) th output signal of the differential circuit, and a lower bit than the i-th bit. Around 0 And (i + 1) th bit line of the differential encoder when the (i + 1) th bit of the binary bit is 1, the (2m-1) th output signal of the differential circuit is the (i + 1) th bit line of the first encoder. And arranged to be supplied to the (i + 1) th bit line of the second encoder. 7. The method of claim 6, wherein the i (i is a natural number) bit counted from the least significant bit of the output signals of the first and second encoders is represented by DAi-1 and DBi-1, respectively, and the synthesis circuit is a logical operation: Generate the least significant bit of the output signal according to (DA0 XOR DB0) and logical operation: (i + 1) counted from the least significant bit mentioned above according to [(NOT DAi) AND DBi) OR DAi-1] And means for generating the second bit. 8. The synthesis circuit according to claim 6 or 7, wherein the i (i is a natural number) bit counted from the least significant bit of the output signals of the first and second encoders is represented by DAi-1 and DBi-1, respectively. Generates the least significant bit of the output signal according to the logic operation (DA0 XOR DB0), and uses the bit DB0 to generate a second bit counted from the least significant bit mentioned above, and the logical operation: [( Means for generating the (i + 2) th bit counted from the least significant bit mentioned above according to DAi OR (DBi AND (NOT DAi-1)]. converter. A first to Nth (N≥2) comparator blocks, each of which is composed of a plurality of comparators, an upper bit encoder, a lower bit encoder, and a comparator of a predetermined comparator among the comparators of the first to Nth comparator blocks, And a higher bit control and gate block for controlling one of the comparator blocks according to the level of the analog input signal applied thereto to control the higher bit encoder, and an output terminal of the first to Nth comparator blocks. And a first to N-th sub-bit control and gate blocks for controlling the lower bit encoder. The A / D converter of claim 10, wherein the first to Nth lower bit control and gate blocks are controlled by an output signal of the higher bit control and gate block.