JP2844819B2 - Parallel comparison type AD converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel comparison (flash) type A / D converter suitable for high-speed conversion of a video signal, for example.

SUMMARY OF THE INVENTION According to the present invention, in a flash A / D converter, an encoder generates an odd parity bit and an even parity bit of a plurality of information bit signals, and performs a parity check of the information bits using both parity bits. By providing an error detection circuit, a predetermined error pattern input to the encoder can be easily detected, and an error generated randomly for each bit (hereinafter, referred to as a “bit random error”) is also detected. It is something that can be done.

2. Description of the Related Art Conventionally, a parallel comparison (flash) type AD converter has been known as useful for high-speed conversion.

First, a conventional flash type A / D converter will be described with reference to FIGS. 4 and 5. FIG.

In FIG. 4, (1) is a reference voltage divider, and a plurality of resistors having the same resistance value are connected in series between a terminal Vra and a terminal Vrb to which a voltage having a predetermined potential difference is supplied. Be composed. The 2 ⁿ reference potential points VR1 to VRx of the voltage divider (1) are connected to the 2 ⁿ comparators of the comparator group (2), and the analog input signal supplied to the input terminal
Vin and each voltage of the reference potential points VR1 to Vrx are compared.

The output of each comparator of the comparator group (2) becomes H in order from the top according to the input voltage value, for example,... HHHLLL,. The so-called "thermometer code". In the AND circuit group (3), the output of the "thermometer code" is differentiated, and a change point is detected. The output of the AND circuit group (3) in which only the output corresponding to this change point is H is supplied to the encoder (4), converted into a digital signal according to the level of the analog signal, and latched (5).
Is derived through

As shown in FIG. 5, for example, in the case of 6 bits, the encoder (4) outputs the output data A1 to A6 of the AND circuit group (3).
4 are each supplied with a plurality of wire-door circuits (W
OR) are arranged on the six bit lines D5 to D0.
Each WOR is composed of, for example, a switching transistor.

[Problems to be Solved by the Invention] By the way, in the above-mentioned conventional flash A / D converter, when the slew rate of the input signal Vin is high, the switching of the comparator cannot follow the input. In the vicinity of the boundary between the change points of H and L of the container pattern, for example, H, L such as {HHHLH * LLLL} {HHHLH * LLLL} May be scattered.
When the binary code of such a mottled pattern is supplied to the AND circuit block (3), the encoder (4)
Unlike the original input, for example, two Hs are input every other, such as {LL LHL H * LL L}, so depending on where such a pattern occurs, , A binary code (sparkle) far away from the original binary code
Has occurred, resulting in a very large digital error.

As described above, it is known that even in the case of a "multi-in error" in which a plurality of Hs are input to an encoder, sparkle of the encoder output is suppressed by using a gray code or a modified gray code (see Japanese Patent Application Laid-Open No. H10-163873). 62-32724, JP-A-1-181327, etc.).

However, Gray code or modified Gray code is
It is assumed that two or more “2-in errors” are adjacent to each other, and a bit random error cannot be dealt with.

On the other hand, in a normal digital circuit, a parity check is often used to detect a bit random error. As is well known, in the parity check, a check bit is provided in addition to the information bit, and "1" and "0" of the check bit are determined according to the odd / even number of "1" in the information bit. There are odd parity in which the total number of “1” is odd, and even parity in which the number is even.

In the case of odd parity, for example, a 6-bit encoder is shown by a chain line in FIG. 5, and as shown in FIG. 6, is provided with an odd parity bit line Dp in addition to the information bit lines D5 to D0. Also, in the case of even parity, the 6-bit encoder uses an information bit line as shown in FIG.
It is configured by providing an even parity bit line Dq in addition to D5 to D0.

However, when an odd or even parity check is used to detect a single error as described above,
As shown by “x” in FIGS. 8 and 9, respectively,
There was a problem that an error could not be detected for 1/3 of the data.

In view of the above, an object of the present invention is to provide a parallel comparison type A / D converter that can detect a predetermined error pattern input to an encoder and also detect a bit random error. It is in.

[Means for Solving the Problems] A parallel comparison type A / D converter according to the present invention includes a plurality of comparators for comparing an analog input voltage with a predetermined reference voltage, and a second comparator based on outputs of the plurality of comparators. A parallel comparator A / D converter having an encoder for generating a binary code, wherein the encoder generates an odd parity bit and an even parity bit of each of the binary codes, and outputs the odd parity bit and the even parity bit. , An error detection circuit for detecting each of the odd parity error and the even parity error based on the binary code.

[Operation] With this configuration, a predetermined error pattern input to the encoder is easily detected, and a bit random error is also detected.

Embodiment An embodiment of a parallel comparator A / D converter according to the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1 shows the overall configuration of an embodiment of the present invention, and FIG. 2 shows the configuration of the main part thereof. In FIG. 1, parts corresponding to those in FIG. 4 are denoted by the same reference numerals.

In FIG. 1, (12) is a comparator group, and (13) is an AND circuit group. For example, in the case of a 6-bit AD converter,
Each has 64 comparators C1 to C64 and AND circuits A1 to A64. The outputs of the comparators C1 to C64 are supplied to parallel buffers P1 to P64 for obtaining two outputs of normal phase and negative phase, respectively.
i is supplied with the normal-phase output of the buffer Pi and the negative-phase output of the buffer Pi + 1. Outputs of the AND circuits A1 to A64 are passed through distribution amplifiers B1 to B64 to predetermined wired OR circuits (WO) on eight bit lines D5 to D0, Dp, Dq of the encoder (14).
R).

As shown in the connection table of FIG. 2, on the first to sixth information bit lines D5 to D0, each WOR is "1" of a normal binary code.
Is arranged at a position corresponding to.

The seventh and eighth bit lines Dp and Dq are bit lines for odd parity and even parity, respectively, and both parity bits Dp and Dq are in a complementary relationship.

An error detection (parity check) circuit (20) is an exclusive NOR circuit (XNOR) (2) in the embodiment of FIG.
1) and exclusive OR circuit (XOR) (22) and OR circuit (2
3). Information bit D5 of encoder (14)
To D0 are commonly supplied to XNOR (21) and XOR (22), the output of odd parity bit Dp is supplied to XNOR (21), and the output of even parity bit Dq is supplied to XOR (22). Supplied. Through OR circuit (23), XNOR (21), XOR
Each output of (22) is derived.

Next, the operation of one embodiment of the present invention will be described with reference to FIG.

If there is no error in the input from each AND circuit Ai, the output of the encoder (14) is such that the first to sixth bits D5 to D0 are ordinary binary codes as shown in FIG.

As shown in the figure, the odd / even parity bits Dp and Dq are changed according to the respective definitions, with 64 data being "1" and "0" interchanged in the first half and the second half, respectively. A pattern in which "1" and "0" are interchanged even in the first half and the second half of the 16 data, and also in the first half and the second half of the 16 data.

"2-in error" occurs and any AND circuit Ai
In the case where the outputs of the one-and-AND circuit Ai + 2 are both H, the output code of the encoder (14) corresponding to the input from the AND circuit Ai is as shown in FIG.
As apparent from comparison with FIG. 2, the output code differs from that of the encoder (14) in the normal state. In this error code, the lower three information bits D2 to D0 repeat the same pattern in cycle 8.

For example, when the outputs of the AND circuits A1 and A3 are both H, the H outputs of the AND circuits A1 and A3 are the bit lines D1, Dp and Dq.
When supplied to each of the above WORs, in the output code of the encoder (14) corresponding to the input from the AND circuit A1, only D1 in the information bits becomes "1" as shown in FIG. The odd and even parity bits Dp and Dq both become "1".

In this case, in the error detection circuit (20), only the output of the XNOR (21) to which the odd parity bit Dp is supplied becomes "1". That is, an error is detected by the odd parity bit Dp, and this error detection signal is derived via the OR circuit (23).

When the outputs of the next AND circuits A2 and A4 both become H, as shown in FIG. 3, the information bit D in the output code of the encoder (14) corresponding to the input from the AND circuit A2.
1 and D0 are both "1", and the parity bits Dp and Dq are both "1". In this case, the output of the XOR (22) to which the even parity bit Dq is supplied becomes "1", and an error is detected by the even parity bit Dq.

Among the following AND circuits A3 to A62, any AND circuit Ai
In the case where a one-shot error occurs, the odd parity bit Dp or the even parity bit Dq
Detects an error.

In this embodiment, FIG. 3 showing the operation and FIG.
As is clear from the comparison with FIG. 9, both the odd and even parities complement each other, so that it is possible to reliably detect the skip error generated in an arbitrary AND circuit Ai. Also,
Bit-random errors can also be detected due to the inherent characteristics of the parity check.

Then, by suppressing the update of the output code when an error is detected, the output of the error code can be prevented.

In addition, the detection capability for the double error is the same as when the odd parity or the even parity is used alone.

Further, in the above-described embodiment, the case where the number of information bits of the AD converter is 6 has been described, but it is possible to easily cope with other numbers of bits.

As the error detection circuit (20), XNOR (21), X
Although the OR (22) and the OR circuit (23) are used, a similar measure can be taken by using an appropriate logic circuit.

If an error occurs when the C1 output becomes L (that is, when Vin becomes slightly larger than Vra), one of the inputs of A1 is connected to the positive-phase output of P1 in FIG. Just change it to

[Effects of the Invention] A parallel comparator A / D converter according to the present invention generates a plurality of comparators for comparing an analog input voltage with a predetermined reference voltage, and generates a binary code based on outputs of the plurality of comparators. A parallel comparison type A / D converter having an encoder that generates an odd parity bit and an even parity bit of each of the binary codes, and generates the odd parity bit and the even parity bit of the binary code. Based on the code, an error detection circuit for detecting each of the odd parity error and the even parity error is provided, so that it is possible to easily detect all the jump errors input to the encoder and to perform bit random There is an effect that an error can be detected.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing a configuration of an embodiment of a parallel comparison type AD converter according to the present invention, FIG. 2 is a diagram showing a configuration of a main part of an embodiment of the present invention, and FIG. FIG. 4 is a table for explaining the operation of the main part of one embodiment of the invention, FIG. 4 is a block diagram showing a configuration example of a conventional parallel comparison type A / D converter, and FIG. FIG. 6 to FIG. 9 are table diagrams for explaining the present invention. (1) is a reference voltage divider, (12) is a comparator group, (13) is an AND circuit group, (14) is an encoder, (20) is an error detection circuit, Dp is an odd parity bit, and Dq is an even parity bit. is there.

Claims (1)

(57) [Claims] An analog-to-digital converter having a plurality of comparators for comparing an analog input voltage with a predetermined reference voltage and an encoder for generating a binary code based on the outputs of the plurality of comparators. In the above, the encoder generates an odd parity bit and an even parity bit of each of the binary codes, and an odd parity error and an even parity error based on the odd and even parity bits and the binary code. A parallel comparison type A / D converter comprising an error detection circuit for detecting each of the above.