JPH03283917A - Parallel comparison type a/d converter - Google Patents

Abstract

PURPOSE:To easily detect a prescribed error pattern by providing an error detection circuit generating an odd number parity bit and an even number parity bit in plural information bit signals, and using both the parity bits so as to check the parity of the information bits. CONSTITUTION:Patterns of odd and even number parity bits Dp, Dq are patterns in which '1', '0' are replaced in 32 bits of first and latter halves of 64 bits, and '1', '0' are replaced in 8 bits of first and latter halves of 16 bits according to the definition of the parity bits. Both the odd and even number parity bits supplement each other and an error in every other bit caused in an optional AND circuit Ai is surely detected. Moreover, a bit random error is detected based on the substantial performance of the parity check. Then the output of an error code is prevented by preventing the revision of an output code at the time of detecting the error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel comparison (flash) type A-D converter suitable for high-speed conversion of video signals, for example.

[Summary of the Invention] This invention provides a flash type A-D converter in which an encoder generates odd parity pits and even parity bits of a plurality of information bit signals, and both parity bits! By providing an error detection circuit that performs a parity check on information bits using It is something.

[Prior Art] Conventionally, parallel comparison (flash) type A-D converters have been known as devices useful for high-speed conversion.

First, a conventional flash type AD converter will be explained with reference to FIGS. 4 and 5.

In FIG. 4, (1) is a reference voltage divider, in which a plurality of resistors having the same resistance value are connected in series between terminals Vra and Vrb, each of which is supplied with a voltage having a predetermined potential difference. configured. 2″ of this voltage divider (1)
The reference potential points VRI to VRX are 2 of the comparator group (2).
The analog input signal Vin supplied to the input terminal is compared with each voltage at the reference potential points VRI to VRX.

The output of each comparator in the comparator group (2) is, for example, ・HHH
LLL• becomes H in order from the top depending on the input voltage value, and changes to L from a certain point, resulting in a so-called "thermometer code." In the AND circuit group 3), this "thermometer code" output is differentiated and a point of change is detected. The output of the AND circuit group (3), in which only the output corresponding to this change point is H, is supplied to the encoder (4), converted to a digital signal according to the level of the analog signal, and passed through the latch (5). derived.

As shown in FIG. 5, for example, in the case of 6 bits, the encoder (4) outputs the output data A1 to A of the AND circuit group (3).
A plurality of wired OR circuits (WOR), each of which is supplied with bit lines D5 to D0, are arranged on six bit lines D5 to DO. Each WOR is composed of, for example, a switching transistor.

[Problems to be Solved by the Invention] By the way, in the conventional flash type AD converter as described above, when the slew rate of the input signal Vin is high, the switching of the comparator cannot follow the input. Near the boundary of the change point of H9L of the pattern, for example, ・・・HHHLH book LLL ・・・・・・・・・HH
H and L may be distributed unevenly, as in HLH book LLL... When such a binary code with a mottled pattern is supplied to the AND circuit block (3), unlike the original input, the encoder (4) receives a binary code such as... LLLHLH book LLL... , two H's are input every other time, so depending on where such a pattern occurs, a binary code (sparkle) that is far different from the original binary code may be generated, resulting in a very There was a problem that it became a big digital village.

As mentioned above, even in the case of a "multi-in error" in which multiple H's are input to the encoder, it is known to suppress sparkles in the encoder output by using a Gray code or a two-variant Gray code (Japanese Patent Application Laid-Open No. Showa 62-3272
(Refer to Publication No. 4, Japanese Unexamined Patent Publication No. 1-181327, etc.) However, Gray code or modified Gray code assumes "2-in errors" that are adjacent to each other or every other one, and bit random errors. There was a problem in that it was not possible to respond when this occurred. On the other hand, in ordinary digital circuits, parity checks are often used to detect bit random errors. As is well known, in the parity check, a check bit is provided in addition to the information bit, and "1" in the information bit is
``1'' or ``0'' in the check pit depending on whether the number is odd or even
'' is determined, and there is an odd parity in which the total number of 1s is an odd number, and an even parity in which the total number of 1s is an even number.

In the case of odd parity, for example, a 6-bit encoder is constructed by providing an odd parity bit line Dp in addition to the information bit lines D5 to DO, as shown by the chain line in FIG. 5 and also shown in FIG. Further, in the case of even parity, the 6-bit encoder is configured by providing an even parity bit line Dq in addition to the information bit lines D5 to DO, as shown in FIG.

However, when an odd or even parity check is used to detect the skipped error as described above, the number of parity checks is approximately 1 as shown by the "x" in FIGS.
There was a problem that error pressure detection could not be performed for data of /3.

In view of this, an object of the present invention is to provide a parallel comparison type A-D converter that is capable of detecting a predetermined error pattern manually entered into an encoder and also capable of detecting bit random errors. It is in.

[Means for Solving the Problems] The present invention includes a plurality of comparators (12) that compare an analog input voltage Vin with a predetermined reference voltage Vr, and a plurality of information bit signals based on the outputs of the plurality of comparators. D5~D
In a parallel comparison type A-D converter having an encoder (14) that generates O, the encoder generates odd parity bits Dp and even parity bits Dq of a plurality of information bit signals, and also outputs the odd parity pits and even parity bits. Based on the bit and multiple information bits,
This is a parallel comparison type A-D converter provided with an error detection circuit (20) that detects a predetermined error pattern in the outputs of a plurality of comparators.

[Operation] According to this configuration, a predetermined error pattern input to the encoder can be easily detected, and bit random errors can also be detected.

[Embodiment] Hereinafter, an embodiment of the parallel comparison type AD converter according to the present invention will be described with reference to FIGS. 1 to 3.

FIG. 1 shows the overall structure of an embodiment of the present invention, and FIG. 2 shows the structure of its main parts. In FIG. 1, parts corresponding to those in FIG. 4 are given the same reference numerals.

In FIG. 1, (12) is a comparator group, and (13) is an AND circuit group. For example, in the case of a 6-bit A-D converter, 64 comparators 01 to C64 and an AND circuit A
1 to A64. The outputs of the comparators 01 to C64 are supplied to parallel phase buffers P1 to P64 that obtain two outputs, positive phase and negative phase, and each AND circuit A1 receives the positive phase output of buffer Pi and the negative phase output of buffer pi+l. and are supplied. The outputs of the AND circuits A1 to A64 are distributed to the distribution amplifiers 81 to 81.
The signals are supplied to predetermined wired OR circuits (WOR) on eight bit lines D5 to DQ, Dp, and Dq of the encoder (14) via B64.

As shown in the connection table of FIG. 2, on the first to sixth information bit lines D5 to DO, each WOR is a normal binary code "
1".

Also, 7th. The eighth two bit lines Dp and Dq are bit lines for odd parity and even parity, respectively, and both parity bits Dp and Dq are in a complementary relationship.

(20) is an error detection (parity check) circuit, which is an exclusive NOR circuit (XNOR) in the embodiment shown in FIG.
(21), an exclusive OR circuit (XOR) (22), and an OR circuit (23). The outputs of the lower three information bits) D2 to DO of the encoder (14) are
21), XOR(22) l: Commonly supplied, and the output of the odd parity pit Dp is
1), and the output of the even parity bit Dq is supplied to XOR(22>).The outputs of XNOR(21) and XOR(22) are derived through the OR circuit (23). Ru.

Next, the operation of one embodiment of the present invention will be described with reference to FIG.

If there is no error in the input from each AND circuit Al, the output of the encoder (14) is as shown in FIG.
The 6th pitch) D5 to DO becomes a normal binary code.

In addition, as shown in the figure, the odd and even parity bits Dp and Dq have 32 "1" and "0" exchanged in each of the first half and second half of the 64 data according to their respective definitions. Even 16 pieces each of the first half and the second half of the data, or even 8 pieces each of the first half and the second half of the 16 pieces of data, ri'',
This is a pattern in which "ra" is replaced.

When a "2-in error" occurs, any AND circuit A1
If the outputs of every AND circuit A1+2 are both H, the output code of the encoder (14) corresponding to the input from the AND circuit A1 will be as shown in Figure 3, and as shown in Figure 2 above. It is different from the output code of the encoder (14) during normal operation, which is quite different from the output code of the encoder (14) in the normal state. This error code has lower 3 information bits) D2 to DO are cycle 8
repeating the same pattern.

For example, when the outputs of AND circuits A1 and A3 are both H, and the H outputs of AND circuits AI and A3 are supplied to each WOR on bit lines D2 to DQ, Dp, and Dq, the output from AND circuit A1 is As shown in FIG. 3, the output code of the encoder (14) corresponding to the input is "1" for only Dl among the information bits.

Also, odd/even parity pitch) Dp and Dq are both “
1".

In this case, in the error detection circuit (20), only the output of the X N OR (21) to which the odd parity bit Dp is supplied becomes "1". That is, an error is detected by the odd parity pit Dp, and this error detection signal is derived through an OR circuit (23).

When the outputs of the next AND circuits A2 and A4 both become H, as shown in FIG. are both "1", and the parity bits Dp and Dq are both "71".

In this case, X to which even parity bits Dq are supplied
The output of OR(22) becomes "1", and an error is detected by the even parity pit Dq.

Even if an error occurs in any AND circuit Ai among the AND circuits A3 to A62 below, the error is detected by the odd parity pit Dp or the even parity bit Dq in the same manner as described above.

In this embodiment, FIG. 3 showing its operation and the above-mentioned section 8.
As is clear from a comparison with FIG. 9, the odd and even parities complement each other, making it possible to reliably detect a single error occurring in any AND circuit Ai. Further, due to the inherent characteristics of parity check, bit random errors can also be detected.

By suppressing the update of the output code when an error is detected, it is possible to prevent the error code from being output.

Note that the detection ability for a double error is the same as when odd parity or even parity is used alone.

Further, in the above-described embodiment, the case where the number of information bits of the A-D converter is 6 has been described, but it is possible to easily accommodate other numbers of bits.

In addition, as the error detection circuit (20), XN0R (2
1), Using X0R (22) and t7 circuit (23) 1.
If N f: i:)<, a similar solution can be achieved using an appropriate logic circuit.

[Effects of the Invention] As detailed above, according to the present invention, an encoder generates odd parity pits and even parity checks for a plurality of information bit signals, and also performs a parity check for information bits using both parity bits. Since an error detection circuit is provided to detect errors, a parallel comparison type A-D converter can be obtained that can easily detect a predetermined error pattern input to the encoder and can also detect bit random errors. It will be done.

[Brief explanation of the drawing]

FIG. 1 is a wiring diagram showing the configuration of an embodiment of a parallel comparison type A-D converter according to the present invention, FIG. 2 is a table diagram showing the configuration of main parts of an embodiment of the invention, and FIG. FIG. 4 is a block diagram showing an example of the configuration of a conventional parallel comparison type A-D converter; FIG.
The figure is a wiring diagram showing the configuration of the main parts of the conventional example, and FIGS. 6 to 9 are table diagrams for explaining the present invention. (1> is the reference voltage divider, (12) is the comparator group, (13
) is an AND circuit group, (14) is an encoder, (20) is an error detection circuit, Dp is an odd parity pit, and Dq is an even parity bit. Agent Hidemori Matsukuma Figure 2A Figure 3A Shinmari no Ichigi's #UnagiHefudaiFigureB Hiroo's f*n*Kegome surname. Fig. 3B Conventional example Fig. 4 Key points of the conventional example Fig. 5 WS diagram with the introduction of conventional #t Dede removed B Fig. 8 Fig. 7 A Fig. 9 A Selling f) Adjunct example of the main course n Izuku Bane Fig. 7 B Seven Kei! Figure 9B

Claims (1)

[Claims] Parallel comparison type A- comprising a plurality of comparators that compare an analog input voltage with a predetermined reference voltage, and an encoder that generates a plurality of information bit signals based on the outputs of the plurality of comparators. In the D converter, the encoder generates odd parity bits and even parity bits of the plurality of information bit signals, and based on the odd parity bits and even parity bits and the plurality of information bits, A parallel comparison type A-D converter comprising an error detection circuit for detecting a predetermined error pattern in the outputs of the plurality of comparators.