JP2638802B2 - Parallel A / D converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel A / D converter for converting an analog value into a digital value.
It relates to a D converter.

2. Description of the Related Art As shown in FIG. 5, a conventional parallel type A / D converter inputs an input signal 1 in parallel to one input terminal of each comparator of a comparator array 4 and applies a reference voltage 2 to a reference resistor array. 3 to form respective reference voltages, which are sequentially input to the other input terminals of the respective comparators. Each comparator compares and amplifies the respective reference voltage and the input signal 1 and outputs a comparison result. . This comparison output has a boundary between the comparator having the closest potential difference between the input signal 1 and the reference voltage of each comparator. All comparators having a higher reference voltage are 1 level, and all comparators having a lower reference voltage are 0 level. Occur. Therefore, in the logic circuit row 5C, if each of the comparison outputs of the adjacent comparators is an input and one of the logic outputs is a logical product of the positive logic and the other is a negative logic, only the logic output of the logic circuit to which two signals having different comparison outputs are input is obtained. Is 1
, And the logic outputs of the remaining logic circuits become 0. Therefore, if this logical output is input to the encoder circuit 6D, only the code when the logical output is 1 is selected, the binary output is output to the output terminal 7, and the analog / digital conversion is performed.

Problems to be Solved by the Invention Such a parallel A / D converter has a first problem as follows.
When the offset voltage variation of the comparator increases, a large conversion error is likely to occur. As a second problem, it is necessary that only one of the logical outputs input to the encoder circuit 6B is 1 and the other is 0. If the logical output does not become 1 due to conversion delay of comparison output or noise, etc. , The conversion outputs are all 0, and large conversion errors are likely to occur. As a third problem, the circuit scale of the encoder circuit 6D is large,
For example, signal delay in the encoder unit is likely to occur.

Since the first problem is somewhat complicated, it will be described below. In FIG. 6, the horizontal axis indicates the comparator signal and the vertical axis indicates the reference voltage LSB of each comparator.
(Minimum bit). The V _rn as shown in the conventional example of FIG. 5 as a reference voltage including the offset voltage of the n-th comparator, the input signal voltage and V _i. Although the reference voltage for each comparator increases monotonically, the actual reference voltage may not be monotonic due to variations in the offset voltage of the comparator. Therefore, if the reference voltage V _r8 of the comparator number 8 is lower than the ideal reference voltage, the reference voltage V _r7 of the comparator number 7 is in the middle of the reference voltage V _r6 of the comparator number 6, and the LSB unit This is represented by V _r8 ′.

That is, as shown in FIG. 6, the reference voltage monotonically increases together with the comparator signal up to V _r7 , and ideally should monotonically increase from V _r7 to V _r8 as shown by the dotted line, but the solid line Assuming that there is a portion where monotonicity cannot be obtained from _Vr7 to _Vr8 'as shown in FIG. 7, the input / output characteristics of the conventional parallel A / D converter are as shown in FIG. FIG. 7 is an explanatory diagram of the occurrence of an error, showing the input / output characteristics of a conventional parallel A / D converter. Normal conversion is performed up to an input voltage of 6, but conversion characteristics at input voltages higher than 6 cause a very large error. The conversion of each comparator generates a comparison output of 1 when V _i ≧ V _rn (where V _rn is the reference voltage of the nth comparator) and a comparison output of 0 when V _i <V _rn . The output of each comparator and the output of the logic circuit when the input voltage changes are as shown in FIG.

First, when V _r6 ≦ V _i <V _r8 ′, the comparator outputs 6 and 7
Since the output state is 1, 0 during the number and the logic circuit output is 1 only at the 6th and all the others are 0, the encoder circuit
It is coded into 6 by 6D and becomes a converted output. Then V
_r8 output state between so sixth comparator output and the seventh and eighth and ninth _{'≦ V i V r6, V} i <V r7, V i ≧ V r8 <V i For V _r7>' Are 1 and 0, respectively, and the output of the logic circuit is 6 and 8 at the same time. Therefore, the coding on the encoder circuit 6D is performed by ORing the respective bits of 0110 of the 6th and 1000 of the 8th,
The conversion value becomes 1110, that is, 14, and a large conversion error occurs. Further, when V _r7 ≦ V _i <V _r9 , V _i ≧ V _r7 ,
Since V _i > V _r8 and V _i <V _r9 , the logical circuit output is No. 8 and the converted value is 8.

From the above considerations, the input / output characteristics of the A / D converter have a large error as shown by the oblique lines when the input voltage is between 6.5 and 7, as shown in FIG. Similarly, when the input voltage is 7
In (8), an error of about 1 LSB occurs. In particular, large errors, such as those occurring between input voltages of 6.5 and 7, significantly degrade the conversion characteristics and are unacceptable.

The present invention has been made in view of such a point, and an object of the present invention is to provide a high-speed parallel A / D converter with a simple method, a small error, and a low error rate.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a reference voltage generating means for generating a plurality of reference voltages in which the order of (i) (≧ 1) is assigned in a monotonically increasing order, Comparing the (i) reference voltage with the input voltage to generate a (i) comparison output, and comparing at least the (i) comparison column with a comparator array including a plurality of comparators having different reference voltages. Output and (i +
2) a logic circuit array comprising a logic circuit having a comparison output as an input, and an analog input voltage having a logic output active in a voltage range between the (i) reference voltage and the (i + 2) reference voltage; A parallel A / D converter including an encoder that receives a logical output from the logic circuit as an input and outputs a digital code corresponding to an A / D converted value.

The present invention uses an encoder that activates one logical output of a conventional parallel A / D converter to generate a predetermined digital code such as a binary code or a gray code. ) -Th comparison output and (i +
The comparison output of No. 2 is input, and the input voltage is adjacent to a logic circuit row composed of logic circuits whose logic outputs become active in a voltage range between the reference voltage of (i) and the reference voltage of (i + 2). By activating the two logic circuit outputs, the more significant bits of the encoder are coated with only the even-numbered portions of the logic circuit, and the least significant bits of the encoder are coded with the odd-numbered outputs. And a normal digital code can be generated. Therefore, the number of coding dots can be halved compared to the conventional encoder, so that the parallel A /
High speed and low power consumption of the D converter can be achieved.

Regarding the problem of generating a large error due to the non-monotonicity of the comparator output described above, even if the non-monotonicity of the comparator output occurs, the even-numbered and odd-numbered logic circuit outputs become active, respectively. Since no mixing between the upper bits occurs, a large error can be prevented from occurring in the A / D conversion output.

Further, in the present invention, when n is an integer of zero or more,
The output of the (4n + 1) th logic circuit activates the least significant bit of the encoder, and the bits other than the least significant bit are coded to generate the gray code corresponding to (2n) by the (2n) th logic output. In addition, a coding dot having a logic output of (2n + 1) as an input forms an encoder by a logical product of a dot coded by a (2n) th logic circuit output and a dot coded by a (2n + 2) th logic circuit output. By forming, the comparator malfunctions,
Regarding the error in which the converted data is dropped, by coding such that the distance in the logical space of the coding of the encoder activated by the adjacent logic circuit output is short, one of the two logical outputs to be activated becomes The encoder output can generate a value close to the original conversion value of the A / D converter by the other logic output remaining after dropping, so the error rate of the A / D converter which is a problem at high speed operation Can be reduced.

First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a parallel A / D converter according to the present invention. In FIG. 1, (i) of the comparator row 4
The comparison output of the (i + 2) th comparator is the logic circuit sequence
Input to the 5A logic circuit (i). The output of the logic circuit array 5A (the output of each logic circuit) is input to the encoder circuit 6A. Here, the output of the (4n + 1) th (n ≧ 0) logic circuit activates the first bit (LSB) of the encoder circuit 6A, and the output of the (2n) th logic circuit is (2n) The encoder circuit 6A is coded so as to generate a binary code corresponding to.

Further, the first bit (LSB) of the output of the encoder circuit 6A and the output of the second bit adjacent thereto are input to a code conversion circuit 8A composed of an exclusive OR circuit, and the output of the code conversion circuit 8A is output. Generates the least significant bit of the A / D converted value. The input signal 1, the reference voltage 2, the reference resistor row 3, the comparator row 4, the output terminal 7, and the like are the same as in the conventional example shown in FIG.

Next, the operation of this embodiment will be described. In the logic circuit row 5A, when the output of the (j) th logic circuit is denoted by _Doj , the input of the (j) th logic circuit is the (j) th comparator and (j)
+2) th comparator compares the output of the, D _ij, since an input of D _{i (j + 2),} the V _rj as (j) th reference voltage, the input voltage V _in which D _oj is active first It is expressed by equation (1).

D _oj = 1: V _rj ≦ V _in V _{r (j + 2)} (1) FIG. 9 is a graph of equation (1). In the figure, a portion surrounded by a line indicates a region where a logic circuit output is active. That is, in this way, the logic circuit generates the same output across 2LSB the input voltage V _in. Therefore, to obtain the correct A / D conversion value corresponding to the input voltage V _in As it can be seen from Figure 9. That is, in order to determine the A / D conversion value for one LSB, it is necessary to code the encoder circuit 6A so that the logic outputs of the two logic circuits are activated to obtain the conversion value.

For example, in FIG. 9, when the input voltage is 5, the outputs _Do4 and _Do5 of the logic circuit 4 and the logic circuit 5 output 1 at the same time. Therefore, when D _o4 = 1 and D _o5 = 1, this
It is necessary to code the encoder circuit 6A so that the A / D conversion value becomes 5.

This can be generally expressed as follows. The expression (1) in which the subscript (j) is changed to (j-1) in the expression (1) is as _follows : D _oj = 1: V _rj ≦ V _in <V _{r (j + 2)} (1) D _{o (j−1)} = 1: V _{r (j−1)} ≦ V _in <V _{r (j + 1)} (1) ′ Here, the logical product of the equations (1) and (1) ′ is obtained. And D _oj · D _{o (j−1)} = 1: V _rj ≦ V _in <V _{r (j + 1)} (2)

From the above equation, that is, the A / D converted value corresponding to the value of (j) is obtained by the operation between the outputs of _Doj and _{Do (j-1)} . In this example, a logical product is taken, but the present invention is not necessarily limited to this operation. Although the third, seventh, and eleventh logic circuits do not exist in the present embodiment shown in FIG. 1, the coding of the output of these logic circuits may be all bits 0, as described later. For this reason, it is not necessary to exist, so the description is omitted, but in the following description, it is assumed that it virtually exists.

FIG. 10 is an explanatory diagram of the output of the logic circuit and the coding of the encoder circuit 6A. First, assuming that binary coding is simply performed for each logic circuit, as shown in FIG. 10, n is a natural number (1,2,...) And (2n) and (2n + 1) ), Except for the least significant bit, the coding of the second and higher bits is exactly the same. For this reason,
In the case where the logic circuits (j) and (j-1) are simultaneously activated to convert the value (j) due to the unique connection method of the comparator row 4 and the logic circuit row 5A of the present invention. (1) In the case of j = (2n + 1) Since the (2n + 1) and (2n) th logic circuits are simultaneously active and the second and higher bits are completely overlapped, the (2n + 1) and (2n) th 2 Only one of the codings beyond the bit may be performed, and the other coding does not need to be performed.

(2) When j = 2n When the logic circuits (2n) and (2n + 1) are simultaneously activated, the coding of the second and higher bits is different, but the value of (2n) is required as the conversion value. ,
It is not necessary to code the upper bits of the output of the (2n + 1) th logic circuit, that is, the second and higher bits.

Since there is no state other than the above two cases, from the above condition, the coding of the encoder circuit 6A corresponding to the even-numbered logic circuit is performed with the binary code for the second and higher bits of the coding of the encoder circuit 6A. It is not necessary to code the outputs of the odd-numbered logic circuits.

Next, the coding of the first bit of the encoder circuit 6A will be described. Note that the coding of the upper bits of the second and higher bits has been mainly focused on the even-numbered rows of the output of the logic circuit.

The coding of the encoder circuit 6A with respect to j of the A / D converted value is represented by _Doj · _{Do (j-1)} = 1, that is, the j-th and (j-1) -th of the logic circuit row 5A from the above-described equation (2). Must be coded as specified in the output. Similarly, for the transform value (j + 1), coding that _{satisfies Do (j + 1) .Doj} = 1 is required.

Therefore, _assuming that j = 2n, the above two expressions are as _{follows: Do2n} · _{Do (2n-1)} = 1 (2-1) _{Do (2n + 1)} · _Do2n = 1 (2) -2) In these two equations, _Do2n is common, so in order to distinguish whether the converted value is 2n or (2n + 1), the coding of the first bit of (2n-1) and (2n + 1) is performed. Need to be different.

For example, in FIG. 10, if n = 1 now, (2n
The coding of the first bit (least significant bit) of -1) = 1 and (2n + 1) = 3 is different from 1 and 0. At this time, since the coding of the least significant bit of the A / D conversion value (2n + 1) = 3 is 0, the A / D conversion value 5
Is the least significant bit.

That is, generally, n = 2m + 1 (m ≧ 0) and (4m
The -1) th and (4m + 1) th least significant codings may be different. Therefore, now, the (4m + 1) th least significant bit is activated (1 in this example), and (4m−
FIG. 10 shows the rewriting of the coding of the encoder circuit 6A for making the 1) least significant bit 9 inactive (0 in this example).

FIG. 11 shows the coding of the first embodiment of the present invention obtained from the consideration of the coding of the second and higher bits of the encoder circuit 6A and the coding of the least significant bit of the first bit. Coding A is
The (4m + 1) -th logic circuit output is activated, and coding B is such that the (4m + 1) -th logic circuit output is activated and the (4m-1) -th logic circuit output is activated.

However, for any of these A and B, the least significant bit does not generate a binary code for the input voltage. Therefore, it is necessary to further logically convert the output from the encoder circuit 6A for the least significant bit.

First, in the case of the coding A, focusing on the second bit of the coding, the coding of the encoder circuit 6A for the output of the 4m + 2 (m ≧ 0) -th logic circuit is 1, and the coding for the output of the 4m-th logic circuit is 0.
It is.

Therefore, when the A / D conversion value is 4m, a normal conversion value can be generated even if the least significant bit is left as it is,
When the A / D conversion value is 4m + 2, it is necessary to invert the least significant bit. This operation is expressed by the following equation (3), where the value obtained by logically converting the value of the second bit as A and the least significant bit (the first bit) as B is C.

C = ・ B + A ・ (3) Thus, the least significant bit of the A / B conversion value is obtained from the exclusive OR of the output of the first bit of the encoder circuit 6A and the output of the second bit adjacent thereto.

Specifically, the first and second output becomes 1 in the logic circuit when the input voltage V _in is 2 (= 4m + 2, m = 0), the coding A, participating -1 and 0010 0011 words, The value of 3 is output as an A / D conversion value. Therefore, it is necessary to invert the least significant bit of the encoder circuit 6A for the first logic circuit to −0, and as for the least significant bit of the A / D conversion value, the least significant bit (1 It is necessary to take an exclusive OR of the (bit) and the second bit as in equation (3). In addition, the input voltage V _in is 3
The output of the second and third logic circuits is 1,
−0 and 0010 are added to become 0010, that is, 2. However, since the least significant bit is exclusive-ORed with the second bit of the encoder circuit 6A and the least significant bit, 1 is output,
As a result, the A / D conversion value becomes 0011 (= 3).

Next, the coding method is the following for coding B in which the 4m + 1-th is inactive and the 4m-1-th is active, contrary to the above. In this case, the value C obtained by logical conversion in the same manner as in Expression (3) is expressed by Expression (4).

C =. + A.B (4) Accordingly, the necessary code conversion circuit is 8A which is a coincidence circuit.

Next, the error suppression effect according to the first embodiment of the present invention will be described with reference to FIG. 6th error occurrence
Assuming that non-monotonicity occurs within 1 LSB as shown in FIG. 8 to FIG. 8, it is assumed that the comparison output from the comparator is exactly the same as shown in the upper part of FIG. On the other hand, as shown in FIG. 1, each logic circuit receives the (j) -th and (j + 2) -th comparison outputs as inputs, so that each logic circuit output has a logic as shown in the lower diagram of FIG. Generate output. In the figure, the states of A and C are normal, B is abnormal, and the state of B activates the outputs of the logic circuits 5 and 8, but the even and odd outputs do not overlap the upper bits. , 9 which are very close to the normal value 7 and do not cause a large conversion error as in the conventional example.

 Next, a second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
In FIG. 2, a logic circuit array 5A is the same as that of the first embodiment of the present invention shown in FIG. Encoder circuit 6B (4m
The output of the (+1) (m ≧ 0) th logic circuit activates the least significant bit (LSB) of the encoder circuit 6B, and the (2n) (n ≧) th logic output outputs the least significant bit (LSB). ) Is made inactive, and an encoder circuit 6B configured to generate the gray code corresponding to (2n) in the adjacent encoder lines of the second bit or more is the same as the conventional example.

The operation of the second embodiment will be described. FIG. 13 is an explanatory diagram of a case where the encoder circuit 6B is coded so as to obtain a conversion output corresponding to each logic circuit number using a gray code. In the case of the Gray code, similarly to the binary code, (2n) and (2n +
In 1), the coding of the upper bits of the second bit or more is exactly the same except for the least significant bit. For this reason, as described in the first embodiment, the upper bits of the second bit or more of the coding are performed by the gray code corresponding to the output of the even-numbered logic circuit, and the coding for the output of the odd-numbered logic circuit is not performed. May be.

Next, the coding of the least significant bit is performed. As described in the first embodiment, since the output of the 2n-th logic circuit is shared, the (2n + 1) -th and (2n-1) -th coding are performed. The coding of the encoder circuit 6B for the logic circuit output needs to be in a different state. Also, in the case of the Gray code, unlike the binary code, the even-numbered least significant bit is also activated, so that the A / D conversion values (2n + 1) and (2n-1) cannot be distinguished unless this is made inactive. Therefore, when the least significant bit is made inactive, the coding of the least significant bit corresponding to the (4m-1) th and (4m-1) th logic circuit outputs is 0, respectively.
And 1, and as described in the first embodiment, D
_{o (2n + 1)} and D _{o (2n-1)} can be distinguished.

The coding diagram of the second embodiment of the present invention obtained from the above consideration is shown in FIG. Next, when verifying the correctness of the least significant bit of the A / D conversion value, the least significant bit of the 4m (= 2 × 2n) -th output of the even-numbered logic circuit is 0 as described above. The (4m-1) th is also 0, and is given by the logical operation (logical sum in this case ₎ of the logical circuit outputs _{Do (4m)} and _{Do (4m-1).} Since the least significant bit of the A / D converted value 4m is 0 and the second and higher bits are output as a gray code, a correct gray code for the A / D converted value 4m is eventually generated in all bits.

As for the coding for the 4m + 2 (= 2 (2n + 1) th logic circuit output, the least significant bit of the encoder circuit 6B is coded to 0 as described above, but (4m + 2) =-1 = 4m + 1th least significant bit. Bit is 1
Logic circuit output D
The least significant bits of the A / D conversion value (4m + 2) given by the logical operation of _{o (4m + 2)} and D _{o (4m + 1)} are the first and second bits.
+2) Since the gray code remains as it is, A / D
The correct Gray code is output in all bits for the converted value (4m + 2).

Further, it is needless to say that the odd-numbered (2n-1) A / D-converted values output only the least-significant bit different from the even-numbered A / D-converted values, and output a gray code. . All codes are correct by Gray code
A / D conversion value is obtained.

 Next, a third embodiment of the present invention will be described.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.
In FIG. 3, an input signal 1, a reference voltage 2, a reference resistance string 3, and a comparator 4 are the same as those in the first embodiment of the present invention. The logic circuit row 5B is the logic circuit row of the present invention, and the connection of the logic input terminal is the same as the first and second embodiments of the present invention, but is similar to the first and second embodiments. Does not omit the (4n-1) th logic circuit, and has logic circuits of all numbers.

The encoder circuit 6C is based on the gray code shown in the second embodiment of the present invention, and has a special configuration for reducing an error rate of a parallel A / D converter described later.

FIG. 15 shows the coding in the third embodiment of the present invention. In this coding method, the coding for the output of the 2n-th logic circuit is exactly the same as that of the second embodiment of the present invention, and the coding of the second bit or more for the (2n + 1) -th odd-numbered logic circuit output is performed. Is encoded by the logical product of the coding for the (2n) th logic circuit output and the coding for the (2n + 2) th logic circuit output. Fifteenth
1 ^{* in the} figure is the dot thus formed. For example, regarding the coding of the encoder circuit 6C for the output of the third (= 2n + 1, n = 1) logic circuit, the second (-2n, n = 1) and fourth (= 2n, n = 1) logic circuits Coding for the output of (0010) and (011
0) is obtained by taking the logical product for each bit, (001 ^* 0)
Becomes

If coding is performed as described above, coding is performed using the output of the (2n) th logic circuit and the output of the (2n + 1) th logic circuit, or coding is performed using the output pair of the (2n) and (2n−1) th logic circuits. Encoder circuit
It is clear that the newly formed 1 ^* in the third embodiment of the present invention does not cause any disadvantage even in the conversion by 6C. Further according to the present embodiment, the encoder circuit
Even if one of the two inputs of 6C becomes inactive, the other input generates a value very close to the normal value by the Gray code function. It is extremely effective against data loss occurring in the converter.

In parallel A / D converters, if an error occurs, essentially Bernhard Zojer et al.
al.) to “A6-Bit / 200-MHz Full Nyquist A /
D Converter. "Iii Journal Journal Solid State Circuit (IEEE J. Solid-State Circui
ts,) vol.sc-20.No.3 pp780-786.June1985.

Since the comparator has a dead zone, the probability Pε that causes an error is represented by Pε (Va / Vq) exp (−T / γ) (5) In equation (5), Va is the input converter dead voltage of the comparator, Vq is the unit quantization voltage, T is the time of the strobe mode of the comparator, and γ is the time constant of the strobe circuit.

In FIG. 16, 16-A is an explanatory diagram showing the occurrence of an error in the conventional parallel A / D converter. In the vicinity of the threshold voltage of each comparator, there is a region of error occurrence defined by Va exp (−T / γ), which is divided by a unit quantization voltage Vq of each comparator to obtain an error. Give a late. For this reason, an error of about 10 ^-9 occurs in the ordinary parallel A / D converter, and the error rate increases as the conversion speed increases, which is a problem in high-speed conversion.

The appearance of an error is considered to cause so-called double occurrence or dropout of data. Among them, the use of a gray code is effective for the double occurrence of data, and has already been implemented. However,
Regarding data dropout, conventional parallel A / D
Since the converter inputs only one data to the encoder circuit, if this data drops out, the converted value becomes zero, a large error occurs, and the error rate is also expressed by equation (5). Such a finite value.

On the other hand, in the third embodiment of the present invention, a conversion value is generated by two adjacent inputs, and even if one of the inputs drops out, the other input remains with an error of about 4 LSB at the maximum. Since a converted value is generated, a large error is unlikely to occur.

The state of error occurrence in the third embodiment of the present invention
This is shown at 16-B in FIG. In 16-B, the upper and lower parts indicate inputs to two adjacent encoder circuits 6C. The threshold value of each input is 2Vq, which is further shifted by Vq. In such a state, two adjacent inputs drop out at the same time is due to Va exp (−
T / γ) because they overlap.
The error probability of causing an error of 4 LSB or more in the third embodiment of the present invention is expressed by the following equation (6).

From the formula (6), the normal case Is satisfied, it is considered that the occurrence rate becomes extremely small.

As described above, according to the present invention, errors are reduced by using a gray code for double occurrence of data,
For data dropout, coding is performed with two adjacent input data, and even if one of the inputs drops out, the other input alone outputs a value very close to the normal conversion value. In either mode, the error is within ± 4 LSB, and there is a great effect that the probability of generating a large error as in the conventional parallel A / D converter is extremely small.

 Next, a fourth embodiment of the present invention will be described.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.
In FIG. 4, input signal 1, reference voltage 2, reference resistance value sequence 3,
The comparator array 4 is the same as the first embodiment of the present invention, and the logic circuit array 5B is the same as the third embodiment. Encoder circuit
6D is coded as described below. 7 is an output end,
8B is a code conversion circuit.

A method of configuring an encoder according to a fourth embodiment of the present invention will be described. In the encoder circuit 6B, the encoder lines of the third bit or more are coded exactly the same as the encoder circuit 6C of the third embodiment of the present invention. That is, (2
The output of the n) th logic circuit generates a gray code corresponding to (2n) the encoder lines of the third bit or more of the encoder circuit 6C. The coding for the output of the (2n + 1) -th logic circuit is (2n) -th and (2n) -th.
(+2) The coding is performed to take the logical product of each bit of the encoder line corresponding to the output of the logic circuit. The second and subsequent bits are coded exactly the same as in the first embodiment of the present invention. That is, the coding circuit 6D is coded so as to generate a binary code by the output of the (2n) th logic circuit, and is coded to activate the least significant bit by the logic output of the (4n + 1) th logic circuit. Have been. Further, the output of the encoder circuit 6D is converted into a binary code by the code conversion circuit 8 and output to the output terminal 7.

According to the present embodiment, even if the lower bit (second bit or less) is a binary code, the upper bit (third bit or more) is a gray code. A large conversion error does not occur for multiple occurrences and dropouts, and stays at the error level of the lower bits. Further, since the lower bits are binary codes, the number of connection stages of the exclusive OR circuit of the code conversion circuit 8B can be reduced. For example, in the present embodiment, the delay of the code conversion circuit 8B is one stage of the logic circuit. However, although not shown, when all are configured by the gray code, the delay is three stages. Therefore, this embodiment is particularly effective for high-speed conversion.

In the present embodiment, the gray code is applied to the encoder line of 3 bits or more of the encoder circuit 6D, and the binary code is applied to less than 2 bits (2 bits or less). However, it is needless to say that the gray code can be applied to any bit. No.

According to the present invention, as described in each of the embodiments, only the part corresponding to the even number is coded for the upper bits of two or more bits of the encoder circuit, and the part corresponding to the odd number is coded only for the least significant bit. In this method, the number of dots of coding can be reduced by half and the number of logic circuits can be reduced by about 1/4 as compared with conventional coding, which contributes to a reduction in power consumption or an increase in speed.

Furthermore, in the above configuration, even in such a state, even-numbered and odd-numbered logic circuits are simultaneously activated for a large error caused by the non-monotonicity of the comparator output. Does not occur, and a large error does not occur.

In addition, using a gray code, it corresponds to an odd number (2n +
1) The coding of the second bit or more of the encoder circuit by the logic circuit performed by the logical product of the bits of the (2n) th coding and the (2n + 2) th coding of the logic circuit is input to the encoder circuit. If one of the two logical inputs drops out,
An error rate that generates a value almost equal to the converted value and the converted value becomes zero as in the related art is very small, and the reliability of conversion at the time of high-speed conversion is greatly improved.

Furthermore, the upper bit of the encoder circuit is configured by Gray code, and the lower bit is configured by binary code.
Although the error at the time of error is slightly larger than that in which everything is configured with Gray code, the number of stages of the exclusive OR circuit that converts Gray code to binary code can be reduced, and it has the effect of contributing to high speed conversion, This invention has many effects from various viewpoints and is a very useful invention.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a parallel A / D converter according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a parallel A / D converter according to a second embodiment of the present invention. FIG. 3 is a circuit diagram showing a parallel A / D converter according to a third embodiment of the present invention. FIG. 4 is a circuit diagram showing a parallel A / D converter according to a fourth embodiment of the present invention. FIG. 5 is a circuit diagram showing a parallel A / D converter according to a fifth embodiment of the present invention. FIG. 6 is an explanatory diagram showing a relationship between a comparator number and a reference voltage for explaining an error occurrence in a conventional example. FIG. 7 is an explanatory diagram showing an input voltage and a conversion output for explaining an error occurrence in the conventional example, FIG. 8 is an explanatory diagram showing a state of a comparator output and a logic circuit output for explaining an error occurrence in the conventional example, and FIG. FIG. 1 is an explanatory diagram showing an input voltage and a logic circuit output at zero according to a first embodiment of the present invention. FIG. 10 is a diagram showing a first embodiment of the present invention. FIG. 11 is a coding diagram for explaining, FIG. 11 is a coding diagram in the first embodiment of the present invention, FIG. 12 is an explanatory diagram of error suppression in the first embodiment of the present invention, and FIG. FIG. 14 is an explanatory diagram of coding in the second embodiment, FIG. 14 is a coding diagram of the second embodiment of the present invention, FIG. 15 is a coding diagram of the third embodiment of the present invention, and FIG. FIG. 3... Reference resistance row, 4... Comparator row, 5A... Logic circuit row, 6A... Encoder circuit, 7... Output terminal, 8A.

Claims (6)

(57) [Claims] 1. A reference voltage generating means for generating a plurality of reference voltages in which an order of (i) (i is an integer of 0 or more) is added to a monotonically increasing order, and the reference voltage of (i) And a comparison output of a comparator for comparing an input voltage with an even-numbered (2n) -th reference voltage (n is a part of an integer of 0 or more), and an even-numbered (2 (n + 1)) reference voltage. The comparison output of the comparator that compares the input voltage is input and the input voltage is (2n)
A first logic circuit row including a plurality of logic circuits whose logic outputs are active in a voltage range between the reference voltage of (i) and the reference voltage of (2 (n + 1)); The comparison output of the comparator that compares the input voltage with the odd-numbered (2n + 1) -th reference voltage and the odd-numbered (2n + 1) th reference voltage
A voltage range in which the comparison output of the comparator for comparing the reference voltage of (n + 1) +1) with the input voltage is input, and the input voltage is sandwiched between the reference voltage of (2n + 1) and the reference voltage of (2 (n + 1) +1) And a second logic circuit row including a plurality of logic circuits whose logic outputs are activated, and an output signal of the first logic circuit row and an output signal of the second logic circuit row are input, and at most two A parallel A / D converter including an encoder that activates a logical input and outputs a digital code. 2. A comparison output of the number (i) and a comparison output of the number (i + 2), and the analog input voltage is within a voltage range between the reference voltage of the number (i) and the reference voltage of the number (i + 2). When the logic circuit whose logic output becomes active is the (i) th logic circuit, and n is an integer greater than or equal to zero, the output of the (4n + 1) th logic circuit activates the minimum bit of the encoder, and (2n) ) Th logical output (2n)
And an exclusive OR circuit that inputs a minimum bit of the encoder and a second bit adjacent thereto, which are coded to generate a binary code corresponding to, and outputs the output of the exclusive OR circuit. Minimum bit output, other bits are A /
2. The parallel A / D converter according to claim 1, which outputs a binary code corresponding to the D conversion value. 3. The comparison output of the number (i) and the comparison output of the number (i + 2) are input, and the analog input voltage is within a voltage range between the reference voltage of the number (i) and the reference voltage of the number (i + 2). When the logic circuit whose logic output becomes active is the (i) th logic circuit, and n is an integer greater than or equal to zero, the output of the (4n + 3) th logic circuit activates the minimum bit of the encoder, and (2n) ) Th logical output (2n)
An encoder coded to generate a binary code corresponding to, and a matching circuit having as input a minimum bit of the encoder and a second bit adjacent thereto, and outputting the output of the exclusive OR circuit as a minimum bit output 2. The parallel A / D converter according to claim 1, wherein the other bits output a binary code corresponding to an A / D conversion value using an output of the encoder. 4. A comparison output of the number (i) and a comparison output of the number (i + 2), and the analog input voltage is within a voltage range between the reference voltage of the number (i) and the reference voltage of the number (i + 2). When the logic circuit whose logic output becomes active is the (i) th logic circuit and n is an integer equal to or greater than zero, the output of the (4n + 1) th logic circuit activates the minimum bit of the encoder, and The other bits are (2
2. The parallel A / D converter according to claim 1, further comprising an encoder coded to generate a Gray code corresponding to (2n) by an (n) th logical output. 5. A comparison output of the number (i) and a comparison output of the number (i + 2), and the analog input voltage is within a voltage range between the reference voltage of the number (i) and the reference voltage of the number (i + 2). When the logic circuit whose logic output becomes active is the (i) th logic circuit and n is an integer equal to or greater than zero, the output of the (4n + 1) th logic circuit activates the minimum bit of the encoder, and The other bits are (2
The (n) -th logical output is coded to generate a Gray code corresponding to (2n), and (2n +
The coding dot that takes the logical output of 1) as an input is (2)
2. A parallel encoder according to claim 1, further comprising an encoder formed by ANDing each dot of a dot coded by an (n) th logic circuit output and a dot coded by a (2n + 2) th logic circuit output. Type A /
D converter. 6. A comparison logic of (i) and a comparison output of (i + 2) are input, and an analog input voltage is a voltage logic sandwiched between a reference voltage of (i) and a reference voltage of (i + 2). The logic circuit in which the logic output is activated is the logic circuit (i), and the encoder which converts the logic output of the logic circuit into an M-bit digital code by using the logic output as an input, where n is an integer of 0 or more and m is M or less. When an integer greater than or equal to zero,
The coding bits of m bits or more are coded so as to generate the gray code corresponding to (2n) by the (2n) th logic output, and the coding dot having the logic output of (2n + 1) as the input is the (2n) th logic output. It is formed by the logical product of the dot coded by the circuit output and the dot coded by the (2n +) th logical output, and the coding bits of (m-1) bits or less are the output of the (4n + 1) th logical circuit. Activates the least significant bit of the encoder, and (2
2. The parallel A / D converter according to claim 1, wherein the parallel A / D converter is coded to generate a binary code corresponding to (2n) by an (n) th logical output.