JPH03250816A - Parallel comparison type a-d converter - Google Patents

Abstract

PURPOSE:To simplify the encoder constitution and to suppress generation of a sparkle by generating a low-order bit and also a complement bit with respect to the most significant bit at a 1st stage in the 1st stage encoder and allowing a next-stage encoder to use the most significant bit at the 1st stage and its complement bit thereby generating a high-order bit. CONSTITUTION:Outputs of comparator blocks 2A-2D are fed respectively to AND circuit blocks 13A-13D, outputs of the AND circuit blocks 13A-13D are fed respectively to 1st stage encoders 14A-14D and outputs of the encoders 14A-14D are fed to a next stage encoder 15. Then the 1st stage encoders generate a low-order bit and and generate a complement bit of the most significant bit D5 in the low-order bits, and the next stage encoder generate the high-order bits based on the complement bit and the most significant bit D5 in the low- order bits. Thus, the constitution of the encoders is simplified and the generation of a digital error (sparkle)is suppressed.

Description

[Detailed description of the invention] The invention will be explained in the following order.

A. Industrial field of application B0 Summary of the invention C8 Conventional technology 1 Problem to be solved by the invention E0 Means for solving the problem F9 Effect G. Example G1 Structure of an example (Figs. 1 to 1) Figure 3) G2 Operation of one embodiment (Figures 1 to 6) H0 Effects of the invention A, Industrial field of application This invention has a two-stage encoder suitable for high-speed conversion of video signals, for example. Parallel comparison (flash) type A
-Relating to a D converter.

B0 Summary of the Invention The present invention provides a flash type A-D converter having a two-stage encoder, in which the first stage encoder generates lower bits and the complement bit of the most significant bit in the first stage, and In the encoder, the most significant bit in the first stage and its complement bit are used to generate the upper bit, thereby simplifying the encoder configuration.
This makes it possible to suppress the occurrence of digital errors (sparkles).

C0 Prior Art First, a conventional parallel comparison type (flash) A-D converter will be described with reference to FIGS. 7 to 11.

Conventionally, parallel comparison type A-D converters capable of high-speed operation and suppressing digital errors have been developed, for example, in Japanese Patent Laid-Open No. 62-32.
It is described in Publication No. 724.

That is, in FIG. 7 showing the principle structure of a conventional parallel comparison type A-D converter, (1) is an equal resistance between the terminal V ra and the terminal 2, to which voltages having a predetermined potential difference are supplied, respectively. It is a reference voltage divider made by connecting resistors with different values in series. 2 reference potential points VR of this voltage divider (1),
VR to VR are connected to each of the 2n comparators of the comparator group (2), and the analog input signal supplied to the input terminal IN is compared with each voltage at the reference potential points VR to VRX. The output of the comparator group (2) is passed through the AND circuit group (3) as
The signal is supplied to two-stage encoders (4) and (5), and converted into a digital signal according to the level of the analog signal.

For example, in the case of 8 pins) A-D converter, 256 pins each
As shown in FIG. 8A, each AND circuit block (3A) to (3D) is divided into 64 AND circuits A1 to A6.
4. The outputs of comparators 01 to C64 (not shown) are supplied via input terminals #1 to #64 to parallel-phase buffers P1 to P64, which provide two outputs of positive phase and negative phase,
For example, each AND circuit Ai of the second AND circuit block (3B) has the positive phase output of the buffer Pi and the buffer Pi
+1 negative phase output is supplied. AND circuits A1 to A6
The outputs of 4 are respectively supplied to predetermined wired OR circuits (WOR) on the 7 bit lines SUP and D5 to DO of the second, first-stage encoder block (4B), for example, via distribution amplifiers 81 to B64. Ru. Each WOR is composed of, for example, a switching transistor, and is arranged as indicated by "1" in the connection table of FIG. 8B.

As shown in Fig. 8, four AND circuits each constitute one unit, and among the lower 6 bits output from each unit (3e) to (3t), bits D5 to D2 are common to the four AND circuits. . Further, as shown in FIG. 2A, the most significant bit line 5HIP of the encoder block (4B) is connected to the first bit line 5HIP of the second to fourth AND circuit blocks (3B) to (3D). Eighth units (3e), (31) each have three AND circuits A1 to A3. The output of the most significant bits of A30-A32 is provided.

Third. Fourth encoder block (4C), (4D
) is similarly constructed. In addition, in the first encoder block (4A), there is no WOR on the SUP line, and each WOR is arranged on the six bit lines D5 to Do, so in FIG. 8B, the WOR on the SUP line is It is indicated by "1°".

As shown in FIG. 9, in the next-stage encoder (5), the 6-bit outputs D5 to DO of each of the first-stage encoder blocks (4A) to (4D) are connected to an error suppression circuit (6A) consisting of an AND circuit and an inverter. ) to (6D) to the lower bit lines D5 to DO of the encoder (5), and the second to fourth encoder blocks (4B) to (4D
) outputs D5 to Do are connected to upper bit lines D7. It is supplied to D6. This upper bit line D7. D6 contains the most significant bit output S from encoder blocks (4B) to (4D).
UP is also supplied, and the top two pits) D7D6 are generated.

Note that the third encoder block (4C
) outputs SUP, D5-DO are supplied to the most significant bit line D7.

The SUP output of the first encoder block (4A) is used as an overflow signal, and the SUP output of the second to fourth encoder blocks (4B) to (4D) is used as the corresponding error suppression circuit (6B) to (6D). ) is also supplied to the adjacent error suppression circuits (6A) to (6D).

The outputs of the bit lines D7 to DO of the encoder (5) are respectively led out to corresponding output terminals via an output inverting circuit (7) consisting of an exclusive OR circuit.

In the conventional flash type A-D converter as described above, when the input voltage Vin is applied, the outputs of the i-th comparators become rH, and the outputs of the i+1-th comparators become "L". Therefore, only the output of the i-th AND circuit at the change point becomes "H".

This "H" signal is supplied to an encoder to generate a binary code corresponding to the location of the change point.

D0 Problems to be Solved by the Invention However, in the conventional flash type A-D converter as described above, when the slew rate of the input signal Vin is high, the switch of the comparator cannot follow the input, etc.
Near the boundary of the change point of H and L in the comparator pattern, H and L may be distributed in a mottled manner, for example, as in ...HHLH''LLL... Such a mottled pattern When the binary code of is fed to the AND circuit block (3), two "H"s are input to the encoder (4), so depending on where such a pattern occurs, a very large error ( sparkle) is generated. If the error pattern H1 occurs, for example, between 7F and 80 in hexadecimal notation, FF will be output.

In order to prevent such errors from occurring, the conventional A-
In the D converter, the second to fourth encoder blocks (4B
)~(4D) SUP output is error suppression circuit (6A)~
(6D).

For example, as shown in FIG. 10, a mottled pattern occurs in the vicinity where the D5 bit in the same AND circuit block changes, and the AND circuit A31. A33 output is H, H"
If so, D5 D.

The output code generated by A31 is 011110, and the output code generated by A33 is 100000, D5 is suppressed by JWOR on the SUP line, and the original output code ro11110 is output, suppressing errors of 16LSB or more.

The lower five bits D4 to DO are also inhibited in the same way.

Further, for example, as shown in FIG. 11, a mottled pattern is generated spanning between adjacent AND circuit blocks (3A) and (3B), and the AND circuit Il! A63. A
When the output of I becomes H, H''', the lower 6 bits (D5 to Do) of the upper AND circuit block (3A) are suppressed. In this case, if the mottled pattern does not exceed 32LSB, the upper bits D? and D6 are also inhibited at the same time.

However, in the conventional A-D converter as described above, all of the outputs of the lower 6 bits + 1 bit are wire-ORed to generate the upper 2 bits.

Upper bit line D7 of the next stage encoder (5). D6 W
The number of OR sources ends up being 14. Furthermore, in each of the first-stage encoder blocks (4A) to (4D), the number of WOR sources for the six bit lines D5 to Do reaches 32. The output logic amplitude on the emitter side of WOR is smaller than the input logic amplitude on the base side (so each V
There is a problem in that a large amplitude is required to drive the OR, and it takes a long time to reach the required amplitude.

In addition, each encoder block (4A) to (4D) in the first stage
Since the load capacitance of the most significant bit line SUP is significantly larger than that of other bit lines, there is a problem in that this greatly lowers the delay limit, that is, the processing speed limit.

In view of this, an object of the present invention is to provide a parallel comparison type A-D converter that can suppress the occurrence of digital errors (sparkles) while simplifying the configuration of the encoder.

E6 Means for Solving the Problem This invention includes a plurality of comparators (2A) to (2D) that compare an analog input voltage Vin with a predetermined reference voltage Vr, and a lower bit value based on the outputs of the plurality of comparators. D5~Do
first-stage encoders (14^) to (140) that generate
Based on the lower bits generated by this first-stage encoder, the upper bits D7. The next stage encoder (15
), the first-stage encoder generates the lower bits and also generates the complement bit D5N of the most significant bit among the lower bits, and the second-stage encoder generates the most significant bit among the lower bits. Parallel comparison type A that generates upper bits based on and complement bits
-D converter.

F6 Effect According to this configuration, the configuration of the encoder is simplified and the occurrence of digital errors (sparkles) is suppressed.

G. Embodiment Hereinafter, an embodiment in which the parallel comparison type AD converter according to the present invention is applied to 8-bit AD conversion will be described with reference to FIGS. 1 to 6.

G1 Construction of an Embodiment FIG. 1 shows the overall construction of an embodiment of the present invention, and FIGS. 2 and 3 show the construction of its main parts.

In FIGS. 1 to 3, parts corresponding to those in FIGS. 7 to 9 described above are given the same reference numerals with the same digits (1), and some explanations will be omitted.

In FIG. 1, (2A) to (2D) are comparator blocks, each of which has 256 cascade-connected comparators and parallel-phase buffers divided into four blocks, as shown in Part 2A. , each comparator block (2A) to (2D) has 6
4 comparators 01 to C64 and parallel phase buffer PL-P64
It consists of Each comparator block (2^) ~ (2D)
The outputs of are supplied to AND circuit blocks (13A) to (130), respectively, and each AND circuit block (13A) to
The output of (130) is the first stage encoder (14A) to (14
0) and encoders (14A) to (1
40) is supplied to the next stage encoder (15).

As shown in FIG. 2A, each AND circuit block (13A
) to (130) are 64 AND circuits A1 to A, respectively.
64. Each AND circuit block (13A) to (1
30), as in Japanese Patent Application No. 1-155846 filed by the present applicant, the 4n+1st AND circuit A4n+1 in the AND circuit includes the 4n+1st buffer P4n.
+1 positive phase output is supplied, and the negative phase output of the 4n+4th buffer P4n+4 is commonly supplied with the 40+4th AND circuit A4n+4. Also, 4n+2.
4n+3rd AND circuit A4n+2. A4n+3 has 4n+24n+3rd buffer y P4n respectively
+2. Positive phase output of P4n+3 and 4n+3.4n+
4th buffer P4n+3. The negative phase output of P4n+4 is supplied. And 4n+2nd buffer P
The negative phase output of 4n+2 is left unconnected.

In this embodiment, as shown in FIG. 2A, the first stage encoder blocks (14A) to (140) each have a bit line D5N of the complement of the most significant bit D5 among the lower bits.
, and two bit lines Dlb and DOb, which are equivalent to the lower two bit lines Dla and DOa, are newly provided. Two bit lines each Dla, DOa and Dlb, DOb
are placed on both sides of the first-stage encoder block to reduce parasitic capacitance.

The outputs of AND circuits A1 to A64 are distributed to distribution amplifiers B1 to B
64, for example, the nine bit lines D5. D5N, D4~D2
．． It is supplied to predetermined WORs on Dla, DOa, Dlb, and DOb, respectively. Each WOR is arranged as indicated by "1" in the connection table of FIG. 2B.

In this embodiment, as shown in FIG.
~ (131) each first AND circuit AL A5...
・The output of A29 is supplied to the upper bit lines D5N, D4 to D2, and the other eight units (13m) to (1
3t) of each first AND circuit A33. A37...
The output of A61 is sent to the upper bit line D5. D4 to D2, and the WOR on the upper bit lines D5D5N and D4 to D2 of the first-stage encoder block (14B) is significantly reduced.

Also, the lower 2 of the 8 units (13e) to (131)
Bit output is on one bit line Dla, D Oa
At the same time, the outputs of the lower two bits of the other eight units (13II) to (13t) are supplied to a predetermined WOR on the other focus lines Dlb and DOb, so that each bit Lines Dla, DOa, Dlb,
WOR on DOb is halved.

Then, as shown in A of the same figure, the encoder block (1
The output of the first AND circuit AI of the AND circuit block (13B) is supplied to the most significant bit line D5N of the AND circuit block (13B).

Third. Fourth encoder block (14C), (1
40) is similarly configured. Furthermore, in the first encoder block (14A), an AND circuit block (13B)
Since the output of the first AND circuit A1 is not supplied to the highest bit line D5N and is used as an overflow signal, in FIG.
is indicated by "1".

As shown in Figure 3, in the next stage encoder (15),
Two lower bit lines Dla, DOa and Dlb, D each from the first-stage encoder blocks (14A) to (140)
Ob is commonly connected to lower bit lines Di and Do of the encoder (15) via OR circuits 01 and 00, respectively. Three intermediate bit lines D4 to D2 from encoder blocks (14A) to (140) each connect to encoder (1
5) are commonly connected to middle bit lines D4 to D2.

The outputs of the most significant bit line D5 and complement bit line D5N in the first stage are transmitted from the encoder blocks (14A) to (140) to the corresponding error suppression circuits (16A) to (1), respectively.
60) of the encoder (15), the bit line D5 and the upper bit line D7 . It is supplied to D6 and also to the adjacent error suppression circuits (16A) to (160).

The output of each bit line D7 to DO of the encoder (15) is
The output signals are respectively led out to corresponding output terminals via the output inverting circuit (7).

G2 Operation of one embodiment Next, the operation of one embodiment of the present invention will be described with reference to FIGS. 4 to 6.

As shown in FIG. 4, in this embodiment, 4n+
The first AND circuit A4n+1 takes charge of the upper bits D5 to D2 of the first-stage encoder blocks (14A) to (140), and the three AND circuits A4 of 4n+2 to 4n+4
n+2 to A4n+4 are lower bits D1. In charge of DO. Therefore, as illustrated in FIG. 5, in a mottled pattern of three or less, digital errors of bits D2 or higher do not occur. That is, the encoder of this embodiment is inherently less susceptible to errors due to the mottled pattern of the comparator.

In addition, in this embodiment, the first-stage encoder block (
The bit lines D5N provided at 14A) to 140 are substantially the OR of the outputs of the AND circuits A1 to A32, and intuitively serve as the complement of the bit line D5. In the normal case, when any of the encoder blocks (14A) to (140) should output, a total of eight bit lines D5
．． At most one of D5N becomes r) (J. Therefore, in this embodiment, the WOR of D5.D5N generates the upper bits D6.D7 of the output, and the number of WOR of D6.D7 bits is calculated. This has been significantly reduced.

Furthermore, in this embodiment, for example, as shown in FIG.
A mottled pattern occurs when the input is a multiple of 32,
The D5 bit in the AND circuit block changes, and the bit line D5. of the encoder blocks (14A) to (140) changes. D
When two of 5N become H, the error suppression circuits (16A) to (160) in FIG. 3 suppress D5 or D5N in the direction in which the output code increases (to the right in FIG. 3). In this case, unlike the conventional example, there is no need to distinguish between inside and outside of the same encoder block.

In this way, in this embodiment, when up to seven discrete patterns occur, it is impossible to accurately define the true value using only the output of the comparator, but it is possible to suppress the error to about 16LSB. .

As detailed above, according to this embodiment, the complement bit D5N of the most significant bit D5 of the first-stage encoder is provided, and the upper bit is generated by ORing the two.
The number of WOR sources for the upper bits can be reduced, suppressing a decrease in logic amplitude, and the WOR for the lower bits has the same number of sources as the upper bits.
It is possible to equalize the signal level. Further, the load capacity can also be reduced, and the conversion process can be made faster.

Furthermore, by using the complement bit D5N, errors can be suppressed without distinguishing between the inside and outside of the first-stage encoder block.

H0 Effects of the Invention As detailed above, according to the present invention, the first-stage encoder generates the lower bits as well as the complement bit of the most significant bit at the first stage, and the second-stage encoder generates the most significant bit at the first stage. Since the upper bit is generated using the upper bit and its complement bit, parallel comparison type A-D conversion can suppress the occurrence of digital errors (sparkles) while simplifying the encoder configuration. A vessel is obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of a parallel comparison type A-D converter according to the present invention, FIG. 2 is a block diagram showing the configuration of main parts of an embodiment of the invention, and FIG. The figure is a block diagram showing the configuration of other main parts of an embodiment of the present invention.
4 to 6 are block diagrams for explaining the operation of an embodiment of the present invention, FIG. 7 is a block diagram showing an example of the configuration of a conventional parallel comparison type A-D converter, and FIG. 8 is a block diagram for explaining the operation of an embodiment of the present invention. FIG. 9 is a block diagram showing the configuration of other important parts of the conventional example, and FIGS. 10 and 11 are block diagrams for explaining the operation of the conventional example. be. (1) is a reference voltage divider, (2A) to (2D) are comparator groups,
(13A) to (130) are AND circuit groups, (14A) to
(140) is the first stage encoder, (15), (15A
) to (15E) are the next-stage encoders, (16A) to (16
0) is an error suppression circuit. Agent Hidemori Matsukuma H Actual precedent's operation state Figure 4 Back side Separate death movement I - Figure 5 SuP section Operation state of conventional example? 5 Figure 10 Gravity work of plate movement A+'fir) Figure 11

Claims (1)

[Claims] A plurality of comparators that compare an analog input voltage with a predetermined reference voltage, a first-stage encoder that generates lower bits based on the outputs of the plurality of comparators, and a lower-order bit generated by the first-stage encoder. In a parallel comparison type A-D converter having a next-stage encoder that generates higher-order bits based on bits, the first-stage encoder generates the lower-order bits and also generates a complement bit of the most significant bit among the lower-order bits. A parallel comparison type A-D converter, wherein the next-stage encoder generates the upper bit based on the most significant bit of the lower bits and the complement bit.