KR100202489B1 - Method for synchronizing clock of iic bus - Google Patents

Abstract

The present invention To an IC bus clock synchronization method. Especially A clock synchronization method of an IC bus includes a first step of setting a timer value corresponding to a low period of a clock to a first timer and setting a timer value corresponding to a high period of the clock to a second timer; Determining whether the clock line of the IC bus is low through the second parallel port and decreasing the value of the first timer until the value of the first timer is zero; If it is detected through the interrupt generator that the value of the first timer is 0, A third step of bringing the data line of the IC bus into a state of 1; A fourth step of reducing the value of the second timer until the value of the second timer becomes 0 after the data line is set to 1; If it is detected through the interrupt generator that the value of the second timer is 0, And a fifth step of making the clock line of the IC bus 0 state.

Description

How to Synchronize Clocks on IC Bus

The present invention The present invention relates to a clock synchronization method for an IC (Inter-IC) bus, Separate to enable communication on IC bus Devices that do not have an IC bus controller Allows communication via IC bus To an IC bus clock synchronization method.

The IC bus is a data line that can be used by various devices (microcontroller, memory, I / O, etc.) at the time of hardware development. It is a bus developed by Philips of Holland . Such The IC bus is characterized in that (1) it can communicate with only two lines, that is, a serial data line (SDA) and a clock line (SCL: Serial Clock Line) Devices connected to the IC bus can be accessed in a software way, (3) multiple masters (4) data transmission is possible from 100 Kbps to 400 Kbps, (5) the capacity is 400 Within a range not exceeding And there is no limit to the number of devices that can be connected to the IC bus.

Devices connected to the IC bus can be either a master (master) or a slave (slave). What is a master Among the devices connected to the IC bus Refers to a device that transmits data through a data line and a clock line of an IC bus and ends transmission. A slave refers to a device that is addressed by such a master and receives data. Since the control of the IC bus is determined only by the addresses and data sent by conflicting masters, There is no central master on the IC bus, and there is no priority among the individual devices.

All masters To send data (message) to slave via IC bus And generates their clocks on the clock lines of the IC bus. Data is thus valid only during periods when the clocks generated by each device are both high.

In the past, For compatibility of the IC bus, separate IC bus controller and additional circuit for it should be installed. therefore, Devices without an IC bus controller I can not communicate with other devices on the IC bus. In other words, Communication can not be performed without IC bus controller.

The present invention has been made in view of such conventional problems.

It is an object of the present invention to provide a Without an IC bus controller Using only a few devices already equipped in each device connected on the IC bus Communication on the IC bus Thereby providing a clock synchronization method of the IC bus.

FIG. Block diagram according to clock synchronization method of IC bus.

Figure 2 is a flow chart of operation of Figure 1;

DESCRIPTION OF THE REFERENCE NUMERALS

10: ROM 20: Microcontroller

30: interrupt generator 40: first timer

50: second timer 60: first parallel port

70: second parallel port SDA: data line

SCL: clock line

In order to achieve the above object, A clock synchronization method of an IC bus includes a first step of setting a timer value corresponding to a low period of a clock to a first timer and setting a timer value corresponding to a high period of the clock to a second timer; Determining whether the clock line of the IC bus is low through the second parallel port and decreasing the value of the first timer until the value of the first timer is zero; If it is detected through the interrupt generator that the value of the first timer is 0, A third step of bringing the data line of the IC bus into a state of 1; A fourth step of reducing the value of the second timer until the value of the second timer becomes 0 after the data line is set to 1; If it is detected through the interrupt generator that the value of the second timer is 0, And a fifth step of making the clock line of the IC bus 0 state.

In order to communicate via IC bus It is necessary to synchronize the clocks between the respective devices connected to the IC bus. All devices on the IC bus generate their own clocks for communication.

Clock synchronization on the IC bus is done by a wired-AND connection. this is When the clock line of the IC bus transitions from high to low, the devices begin to count their row periods, and until later the clock goes high Which means keeping the clock line of the IC bus low.

Thus, even if the clock of any device transitions from low to high, if the other devices are generating a low clock, then by the wired- The state of the clock line of the IC bus remains low. That is, it does not go high. therefore The clock line of the IC bus will be held low by the device with the lowest duration. Devices with shorter clock periods of their clocks will wait for a clock transition to high during this period.

When all the devices connected to the IC bus have finished counting the low period of their clock, that is, when a high clock is generated in all the devices, The clock line of the IC bus transitions from low to high. Since the clock line of the IC bus has transitioned to the high state, The clocks of all the devices connected to the IC bus The clock lines of the IC bus start counting the high period of their clocks. Among the devices connected to the IC bus, the device that has first counted the high period is rewritten by the aforementioned Wired-End logic It will transition the clock line of the IC bus to low.

In this way, clock synchronization of the clock line is achieved. In other words, The low period of the clock of the clock line of the IC bus Among the devices connected to the IC bus, the low period of the clock is determined by the longest device, and the high period of the clock of the clock line is determined by the device having the shortest high period of the clocks.

In Figure 1, A block diagram according to a clock synchronization method of an IC bus is shown. As shown, the microcontroller 20 is connected to the first parallel port 60 Is connected to the data line (SDA) of the IC bus, and through the second parallel port (70) It is connected to the clock line (SCL) of the IC bus. In addition, the microcontroller 20 is connected to each of the first and second timers 40 and 50 to set the timer value to a predetermined value, and to reduce the value of the timer value.

The first and second timers 40 and 50 are connected to the input side of the interrupt generating unit 30 and the output side of the interrupt generating unit 30 is connected to the microcontroller 20.

FIG. 2 shows an operational flow diagram for such a configuration.

The microcontroller 20 first sets the timer values of the first timer 40 and the second timer 50 through the 8-bit data line a at the time of initialization, A corresponding timer value is set in the first timer 40 and a timer value corresponding to a period in which the high state continues is set in the second timer 50 (ST1). With such a setting, the time for staying in the low (0) and high (1) in the clock synchronization process is determined. These timer values can be changed as needed.

After setting the timer value of each of the first timer 40 and the second timer 50 to the predetermined value as described above, the microcontroller 20 sets the timer value of each of the first timer 40 and the second timer 50 through the first parallel port 70 It senses the logic state of the clock line SCL of the IC bus and checks whether the clock line SCL is 0 (ST2). At this time, if the logic state of the clock line SCL is 0, the microcontroller 20 decreases the timer value T1 of the first timer 40 from the previously set value through the first control line a.

When the timer value T1 of the first timer 40 finally becomes 0, the interruption generation unit 30 connected to the first timer 40 detects that the timer value becomes 0, As a result, the interrupt generation unit 30 informs the microcontroller 20 that the timer value of the first timer 40 is zero.

The microcontroller 20 is connected via a first parallel port 60 The logic state of the data line (SDA) of the IC bus is set to 1 When all other devices connected to the IC bus output 1, the status of the data line (SDA) becomes 1 (ST5).

The microcontroller 20 sets the logic state of the data line SDA to 1 and then decrements the timer value T2 of the first timer 50 through the first control line C in ST6.

When the value of the second timer 50 becomes 0, the interrupt generator 30 monitors the interrupt and generates an interrupt to notify the microcontroller 20 that the timer value T2 of the second timer 50 is 0 .

The microcontroller 20 determines in ST7 whether the timer value T2 of the second timer 50 is 0 or not. If it is determined that the timer value T2 is 0, The logic state of the clock line SCL of the IC bus is set to 0 (ST8).

As such, The clock synchronization between the devices can be realized by using timers and the like provided by the devices connected to the IC bus, Communication between devices is possible without an IC bus controller.

While the present invention has been described with reference to the accompanying drawings, it is to be clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the invention. Do.

As described above in detail, conventionally, Devices without an IC bus controller I could not communicate with other devices on the IC bus. In other words, I could not communicate without IC bus controller. In the present invention, By using only some devices (parallel ports, timers) that are already equipped in each device connected to the IC bus, Without an IC bus controller Communication on the IC bus becomes possible.

Claims (2)

A first step of setting a timer value corresponding to a low period of a clock in a first timer and a timer value corresponding to a high period of a clock in a second timer; Determining whether the clock line of the IC bus is low through the second parallel port and decreasing the value of the first timer until the value of the first timer is zero; If it is detected through the interrupt generator that the value of the first timer is 0, A third step of bringing the data line of the IC bus into a state of 1; A fourth step of reducing the value of the second timer until the value of the second timer becomes 0 after the data line is set to 1; If it is detected through the interrupt generator that the value of the second timer is 0, And a fifth step of bringing the clock line of the IC bus into a state of 0 Clock synchronization method of IC bus. The method of claim 1, wherein the value of the first timer corresponding to the low period of the clock and the value of the second timer corresponding to the high period of the clock are changeable Clock synchronization method of IC bus.