KR100200229B1 - Apparatus for assigning vpi/vci in asynchronous transfer mode - Google Patents

Abstract

The present invention relates to a VPI / VCI allocating apparatus for allocating VPI and VCI when a call is requested. The present invention relates to an idle state path by sequentially searching an idle state of each path assigned to the asynchronous transmission mode. An idle path detector 401 for selecting and providing a VPI of the selected idle state path; A counting unit 402 for counting the number of channels assigned to each path; A plurality of idle paths corresponding to the number of idle paths of the idle path unit 401 and corresponding to a count value of the second count unit 402 among a plurality of channels in the idle path selected by the idle path detector 401. A plurality of idle channel detectors 403 for selecting an idle channel to be provided and providing VCIs of the selected idle channel; When a call is requested, the idle path detector 401 and the idle channel detector 403 are provided to provide the VPI / VCI to the requested call.

Description

V Pei / V Sea Eye Allocator in Asynchronous Transfer Mode

1 is a protocol model diagram of a general ATM method.

2 is a general ATM cell diagram.

3 is a block diagram showing a prior art VPI / VCI allocation apparatus in an ATM system.

4 is a detailed block diagram showing a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

401: Idle path detection unit 402, 411: Counting unit

403: idle channel detection unit 404: control unit

412: path selector 413,432: memory

414: VPI provider 431: decoder

433: VCI provider

The present invention relates to an Asynchronous Transmission Mode System (hereinafter referred to as an ATM system), particularly to a VPI / VCI allocator for allocating a VIP (Virtual Path Identifier) and a VCI (Virtual Channel Identifier) when a call is requested. It's about.

In general, the ATM system is a communication method for implementing a Broadband Integrated Service Digital Network (BISDN).

In addition, in BISDN, information is transmitted by a continuous flow of packets having a certain size. The packets of fixed size are called ATM cells. Therefore, the service information is cut to a certain size (48 bytes) in the AAL layer and mapped to the payload of the ATM.

With ATM, the capacity of the service channel is quantified by the number of ATM cells. Therefore, the excessive amount of transmission information appears as some of the number of ATM cells. The allocation of transmission capacity is determined at the time of call establishment according to the required capacity and the available capacity through negotiation with the communication network.

ATM is a connectivity method, which establishes a virtual channel to deliver service information, and an identification number is assigned every time the virtual channel is established, and the identification number is released when the connection is released. The order between ATM cells in a certain virtual channel is preserved by the function of the ATM layer, and the signal information for connection establishment is transmitted through the control plane (FIG. B).

On the other hand, the ATM method defines a layered protocol model for systematic and flexible information delivery. The protocol layer configured at this time is the physical layer 11, the ATM layer 12, the ATM adaptation layer 13 and the upper layer 14 as shown in FIG.

The size of an ATM cell is 53 bytes, which is divided into a 5-byte header 2a and a 48-byte payload space 2b, as shown in FIG. The main function of the cell header is to identify the cells coming from the same medium, determine the priority of the cells, and whether there is any information loss. Information used for identification is the Virtual Path Identifier (VPI) and the Virtual Channel Identifier (VCI) shown in FIGS. 2B and 2C. FIG. 2B shows the header structure in UNI (User Network Network Interface), and FIG. 2C shows the header structure in NNI (Netweek Network Interface).

In this case, a VP (Virtual Path) refers to a virtual channel (VC), that is, a bundle of virtual channels, that share a predetermined path, and a cell header identifies other payload types (PTs). It displays cell loss priority (CLP) and provides header error control (HEC). In addition, as shown in FIG. 2 (B), the UNI further provides a generic flow control (GFC) function in the cell header.

Referring to FIG. 3, a general block diagram for allocating VPI / VCI for a call when a call is requested in an ATM system is shown.

The VPI / VCI allocator may be present in both the terminal or the switch and is assigned by negotiation of the terminal and the switch. The VPI / VCI allocation device 302 also includes a VPI / VCI allocation control unit 31, converters 32 and 33 for separating and combining ATM cells, path switching unit 34, control bus 35, and data buses. (36).

There are two recommended VPI / VCI allocation methods: First, the terminal selects VPI / VCI in the SETUP message and requests it from the switch. If this VPI / VCI is allowed in the switch, it can be used. Second, the terminal does not require the terminal side. This is the case when used.

Therefore, when there is a call request from the terminal, this information is known to the control plane, and the control plane requests a call setup by creating a SETUP message and sending a SETUP message to the switch. In this case, if the UE wants to set a specific VPI / VCI, this information is included in the SETUP message and transmitted to the switch. Otherwise, the switch is determined by requesting to allocate the VPI / VCI. When the switch receives a SETUP message and the VPI / VCI value in the message is idle on the switch, it informs the terminal that it is allowed. If not, it sends a RELEASE message and the cause.

If the VPI / VCI value is not defined in the setup message sent from the terminal, the switch selects an available VPI / VCI value and notifies the terminal.

At this time, the VPI / VCI allocation method of the VPI / VCI allocation control unit 31 generally uses an allocation method through flag search. In this method, the logical channel for setting up a channel upon call request, i.e., assigns an idle path, and then allocates the smallest channel number in order to set the channel of the assigned idle path, and indicates that the channel is in use. After all allocations within the usage range are completed, the flag is searched from the beginning again to determine whether it is in use or not, and a logical channel number that is not being used, that is, an idle channel number, is allocated to the new call.

When the message analysis unit receives the SETUP message, it analyzes the VPI / VCI allocation method and assigns the VPI / VCI through the allocation controller. The data is applied to the path switching unit 34 via the data bus 36, and the path is assigned. The switching unit 34 identifies the VPI / VCI included in each ATM cell and outputs it to the transmission path.

CCITT Recommendations I.361 and 363, on the other hand, define the number of bits used to represent VPI and VCI in the ATM cell header. That is, as shown in FIGS. 2B and 2C, the VPI in the UNI is made of 8 bits, the VPI in the NNI is made of 12 bits, and the VCI of the UNI and the NNI is made of 16 bits. Therefore, the number of channels in UNI is limited to 28, the number of paths is 216, the number of channels in NNI is limited to 212, and the number of paths is 216.

Accordingly, when the VPI / VCI allocation control unit 31 allocates the VPI / VCI, the UNI searches for the idle path and the idle channel among 28 channels and 216 paths, and in the NNI, the idle path and the idle path among the 212 channels and the 216 paths. The idle channel is searched for, and an idle path having an idle channel is selected, and then the VPI / VCI corresponding to the selected idle path and the idle channel are allocated.

However, in the worst case, the VPI / VCI allocation scheme may allocate the VPI / VCI through search 224 in UNI and 228 in NNI. In other words, after allocating an idle path, the channel number of the assigned idle path is assigned in order from the smallest channel number, and the flag of the assigned channel is in use. Since it assigns a logical channel number, i.e., idle channel number, that is not being used to a new call by determining whether it is in use, in the worst case, both the path and the channel assigned to each path are allocated and the idle channel in the last one idle path Even if there is only one, in order to assign it to a new call, the search time can be very long by searching for the flag from the beginning and assigning idle path and idle channel after searching 224 in UNI and 228 in NNI.

In addition, when VPI / VCI is allocated as described above, a memory having a very large capacity of 224X24bit in UNI and 228X28bit in NNI is required.

Accordingly, the present invention provides an ATM VPI / VCI allocation apparatus capable of efficiently performing a search for allocating VPI / VCI in response to a call request and reducing the search time and reducing the memory capacity for VPI / VCI allocation. There is a purpose.

The present invention for achieving the above object, by sequentially searching the idle state of each path assigned to the asynchronous transmission mode to select the idle path, and to provide a VPI of the selected idle state path, assigned to the asynchronous transmission mode A first counting unit for counting the number of each route counted; a path selecting unit for selecting a route corresponding to a count value of the first counting unit; and a flag indicating an idle / use state of each of the paths; A memory that outputs an idle / usage state flag of a path corresponding to the specified address when an address corresponding to the count value of the count unit is specified, and a VPI providing a corresponding VPI when the path selected by the path selection unit is in an idle state An idle path detector configured to provide a second count unit configured to count the number of channels assigned to each path; A plurality of channels corresponding to the number of idle paths of the idle path detector, and selecting an idle state channel corresponding to a count value of the second count unit among a plurality of channels assigned in the idle path declared by the idle path detector; A plurality of idle channel detectors for providing VCIs of selected idle state channels; And a control unit 404 for controlling the idle path detector and the idle channel detector so that the VPI / VCI is provided to the requested call when the call is requested.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a detailed block diagram for explaining a preferred embodiment of the VPI / VCI allocation apparatus of the ATM of the present invention. Referring to FIG. 4, the VPI / VCI allocation apparatus includes an idle path detector 401, a count 402, a plurality of idle channel detectors 403, and a controller 404.

Here, the idle path detector 401 sequentially searches the idle state of each path assigned to the asynchronous transmission mode, selects the idle path, and provides the VPI of the selected idle path, which is assigned to the UNI or NNI. A counting unit 411 for counting the number of paths, a path selecting unit 412 for selecting a path corresponding to the count value of the counting unit 411, a flag indicating an idle / use state of each path, The memory 413 outputs an idle / usage state flag of a path corresponding to a specified address when an address corresponding to the count value of 411 is interrupted, and a corresponding path when the path selected by the path selector 412 is idle. It consists of a VPI providing unit 414 for providing a VPI.

In addition, the path selector 412 outputs a low signal of only the OR gate corresponding to the count value of the counting unit 411 which is continuously arranged in parallel with a plurality of OR gates, and the other OR gates are high. It is composed of ora gate arrays (A1 to An) for outputting a signal, and the VPI providing unit 414 is connected in a one-to-one correspondence to each ora gate of the ora gate arrays (A1 to An) to output and memory each of the ora gates (413). A plurality of OR gate arrays B1 to Bn output by ORing the path idle / use state flag of the "

The counting unit 402 counts the number of channels assigned to each path and provides it to the idle channel detecting unit 403.

Each of the idle channel detectors 403 is configured to correspond to the number of idle paths of the idle path detector 401 to select an idle state channel among a plurality of channels assigned in the idle path selected by the idle path detector 401. A decoder 431 which provides a VCI of an idle channel and selects a channel corresponding to the count value of the counting unit 402, and is enabled when the channel corresponds to an idle path selected by the idle path detecting unit 401, each path. A flag indicating an idle / use state of each channel assigned to the memory is stored, and if an address corresponding to the count value of the counting unit 402 is specified, a memory for outputting an idle / use state flag of a corresponding channel corresponding to the specified address is output. In operation 432, the channel selected by the decoder 431 is in an idle state, and includes a VCI provider 433 which provides a VCI corresponding thereto.

The VCI providing unit 433 is composed of a plurality of channels corresponding to a plurality of channels assigned to each path to logically combine the output of the decoder 431 and the channel idle / use status flags of the memory 432 to provide VCI high 8 bits. A plurality of FIFOs (F1 to Fn) that are connected in a one-to-one correspondence with each of the ora gate arrays C1 to Cn and the ora gate arrays C1 to Cn to provide VCI lower 8 bits when data is input from each ora gate. It consists of

In this case, when the VPI / VCI allocation apparatus of the ATM according to the preferred embodiment of the present invention is applied to the UNI, the counting unit 411 and the counting unit 402 are eight counters, respectively, and the above-mentioned ora gate arrays A1 to An and B1 to Bn, C1 to Cn) each consists of 256 pieces.

In addition, when the VPI / VCI allocation apparatus of the ATM according to a preferred embodiment of the present invention is applied to the NNI, the counting unit 411 is a 12-stage counter, the counting unit 402 is an 8-stage counter, the above-described OA gate array (A1) To An and B1 to Bn are each composed of 4096, and the oragate arrays C1 to Cn are each composed of 256.

The controller 404 controls the idle path detector 401 and the idle channel detector 403 to provide VPI / VCI to the requested call when the call is requested.

The operation description of the preferred embodiment of the present invention configured as described above is as follows.

First, when the call request signal is provided to the control unit 404, the control unit 404 causes the counting unit 411 of the idle path detection unit 401 to be driven, and the counting unit 411 is controlled by the control unit 404. Alternatively, a count value corresponding to each path assigned to the NNI is provided to the path selector 412 and the memory 413, respectively.

Therefore, the ora gate arrays A1 to An of the path selector 412 are provided with count values of the counting unit 411, respectively, and only the ora gate corresponding to the count value outputs a low signal, and the remaining ora gates are Output a high signal.

That is, when the count value is 0, for example, only OR gate A1 outputs a low signal. When the count value is 100, for example, only OR gate A100 outputs a low signal while all other OR gates are high. Output the signal.

On the other hand, the memory 413 stores a flag indicating whether each path is idle or in use, and when a count value is provided from the counting unit 411, a path idle / use state flag stored at the corresponding address is output. .

That is, if the count value is 100, for example, the memory 413 outputs the path idle / usage state flag stored at address 100. If the idle / use state flag is low, the memory 413 indicates that the path is idle. If the use state flag is high, it indicates that the path is in use.

The output of the path selector 412 is input to the respective oar gates B1 to Bn of the VPI providing unit 414 connected one-to-one to the respective oar gates of the oar gate arrays A1 to An, respectively, and the memory 413. ) Is simultaneously input to each ora gate B1 to Bn, and each ora gate B1 to Bn of the VPI providing unit 414 is an output of each ora gate A1 to An of the path selector 412. And the idle / use status flags of the memory 413 and the results of the decoder 431 of the decoder 431 of the idle channel detector 403 connected one-to-one to each of the oragates B1 to Bn. It is provided to each of the enable stages, and simultaneously provided to the control unit 404.

Therefore, when the counting unit 402 sequentially increases the count value, a low signal is output only at the OR gate of the path selector 412 corresponding to the count value, and the path is idle / when the count value is addressed. Since the use state flag is output, for example, when the count value is 100 and the low state flag, which is the path idle state flag, is stored at the address 100 of the memory 413, the ora gate A100 of the path selector 412 is used. ) Outputs a low signal only to the OR gate G100 of the VPI providing unit 414 to the control unit 404, and outputs a high signal from the remaining OR gates of the VPI providing unit 414. In this case, the control unit 404 can know that the 100th path is in an idle state.

On the other hand, if the count value is 100 and the high state flag, which is the path use status flag, is stored at the address 100 of the memory 413, the VPI providing unit 414 corresponding to the OR gate A100 of the path selector 412 is one-to-one. In addition to the ora gate (B100) of the VPI providing unit 414, all of the remaining ora gate outputs a high signal to provide to the control unit 404, the control unit 404 can be seen that the path is the 100th path is in use state Will be.

If the control unit 404 recognizes that the 100th path is in use, the control unit 404 controls the count unit 411 to up count, and if the up count value is 101, for example, the path selection described above. By the operation of the unit 412, the memory 413, and the VPI providing unit 414, the controller 404 detects whether the 101st path is in an idle state or a used state. Similarly, the idle path detector 401 repeatedly performs the above-described operation for detecting the idle path under the control of the controller 404, detects an idle path, and outputs a corresponding VPI.

At this time, for example, when the VPI / VCI allocation unit of ATM is adapted to UNI, the total number of outputs of the VPI provider 414 is set because 256 ora gate arrays B1 to Bn of the VPI provider 414 are configured as 256. The number of bits is 256 bits, and the output of the 256-bit VPI providing unit 414 is provided to the control unit 404. Therefore, when the output of 256 bits of the VPI provider 414 is, for example, the 100th path is idle, only the 100th bit of the VPI provider 414 is a low signal, and the remaining 255 bits are a high signal. However, when each path corresponding to each count value of the counting unit 411 is in a busy state, all 256-bit outputs of the VPI providing unit 414 are signaled high.

When the VPI / VCI allocation device of the ATM is applied to the UNI, the output gradation number of the VPI provider 414 is 256, which can be represented by 8 bits. When the controller 404 receives the 256-bit output of the VPI provider 414, the controller 404 outputs an 8-bit VPI corresponding thereto.

In addition, when the VPI / VCI allocation device of ATM is applied to the NNI, the total number of output bits of the VPI provider 414 is 4096 bits because the OR gate arrays B1 to Bn of the VPI provider 414 are configured as 4096. The output of the 4096-bit VPI providing unit 414 is provided to the control unit 404. Therefore, if the output of the 4096 bits of the VPI provider 414, for example, the 1000th path is idle, only the 1000th bit of the VPI provider 414 will be a low signal, and the remaining 4096 bits will be a high signal. In addition, when each path corresponding to each count value of the counting unit 411 is in a busy state, all of the 4096-bit outputs of the VPI providing unit 414 will be high signals.

Therefore, when the VPI / VCI allocation device of ATM is applied to the NNI, the output gray level of the VPI provider 414 is 4096, which can be represented by 12 bits. When the controller 404 receives the 4096-bit output of the VPI provider 414, the controller 404 outputs a 12-bit VPI corresponding thereto.

On the other hand, each output of the VPI providing unit 414 is respectively input to an enable end of the decoder 431 in the idle channel detector 403 connected one-to-one corresponding to the respective OR gate arrays B1 to Bn. Is enabled when the low signal is input to the enable end. Therefore, when the outputs of the respective OR gate arrays B1 to Bn of the VPI providing unit 414 are all high signals, that is, when the paths detected by the idle path detection unit 401 are in use, the respective OR gate arrays ( Each decoder 431 connected to B1 to Bn in one-to-one correspondence is in a disabled state, and the VPI providing unit 414 corresponding to the detected path when the path detected by the idle path detector 401 is idle. Only the decoder 431 of is enabled and all the remaining decoders 431 are disabled.

The controller 404 stops driving the counting unit 411 when the idle state path is detected by the output of the idle path detecting unit 401 and then controls the counting unit 402 to be driven. The counting unit 402 provides the count value corresponding to the address of each channel assigned to the UNI or NNI to the decoder 431 and the memory 432 of each idle channel detector 403 under the control of the control unit 404. do.

The enabled decoder 431 selects a channel corresponding to the count value of the counting unit 402, and decodes the 8-bit count value of the counting unit 402 to decode the 8-bit count value. The bits are output in parallel, but only 1 bit corresponding to the count value of 256 bits outputs a low signal, and the remaining 255 bits output a high signal.

That is, when the count value is 0, only the most significant bit of the 256-bit output of the decoder 431 is a low signal. When the count value is 100, only the 100th bit of the decoder 431 is a low signal. The remaining 255 bits are high signals.

In addition, the memory 432 stores a flag indicating whether each channel assigned to the corresponding path is idle or in use. When an address corresponding to the count value of the counting unit 402 is designated, the memory 432 is idle / Print the usage flag.

For example, if the count value is 100, the memory 432 outputs the idle / usage status flag of the channel stored at the address 100. If the count value specifies the address 100, the channel 100 is assigned to the address 100 of the memory 432. The memory 432 outputs the low state flag indicating the idle state, and outputs the high state flag indicating the channel 100 in the use state.

On the other hand, each of the ora gates of the ora gate arrays C1 to Cn receives one-to-one correspondence of each bit of the 256-bit parallel output of the decoder 431 to output the decoder 431 and the channel idle / use state of the memory 432. The flags are ORed together and provided to the control unit 404, while the OR gates of the OR gate arrays C1 to Cn are provided to FIFOs F1 to Fn that are connected in a one-to-one correspondence.

For example, when the count value of the counting unit 402 is 100 and the channel idle state flag is stored at the address 100 of the memory 432, the OR gate C100 corresponding one-to-one to the 100th output terminal of the decoder 431 is provided. Only outputs a low signal to the control unit 404, and the rest of the ora gates C1 to C99 and C101 to Cn except the ora gate C100 output a high signal to the control unit 404. In this case, it can be seen that the 100th channel is idle.

On the other hand, if the count value of the counting unit 402 is 100 and the channel use state flag is stored at the address 100 of the memory 432, the rest of the OR gate C100 corresponding to the one-to-one output terminal of the decoder 431 is not only remaining. Since the OR gates C1 to C99 and C101 to Cn output high signals to the control unit 404, the control unit 404 can know that the 100th channel, which is the corresponding channel, is in use.

If the control unit 404 recognizes that the 100th channel is in use, the control unit 404 controls the count unit 402 to up count, and the counted value of the count unit 402 is an example. For example, if it is 101, the controller 404 detects whether the 101st channel is idle or in use by the decoder 431, the memory 432, and the OR gate arrays C1 to Cn. The detector 403 repeatedly performs the above-described operation for detecting an idle channel to detect an idle channel.

At this time, for example, when the VPI / VCI allocation apparatus of ATM is applied to the UNI or NNI, the above-mentioned OR gate arrays C1 to Cn are configured with 256, so the total number of parallel output bits of OR gate arrays C1 to Cn. Is 256 bits, and 256 bits of OR gate outputs C1 to Cn output are provided to the controller 404, which can be represented by 8 bits. Therefore, when there is an idle channel, the control unit 404 receives the 256-bit output of the OR gate arrays C1 to Cn among the total 16-bit VCI, and outputs the upper 8-bit VC1 corresponding thereto.

On the other hand, the outputs of the OR gate arrays C1 to Cn are FIFOs F1 to Fn connected in a one-to-one correspondence with each of the OR gate arrays C1 to Cn. The stored data is output to the control unit 404. In addition, when the VPI / VCI allocation unit of ATM is applied to UNI or NNI, the total number of FIFOs (F1 to Fn) is 256 (F1 to F256), and one low signal output from the OR gate arrays (C1 to Cn) is obtained. The 256 bits included are input to the FIFOs (F1 to F256), and the FIFOs (F1F to 256) provide the controller 404 with 256 bits including one row signal previously stored.

Therefore, when the control unit 404 receives the 256-bit output of the FIFOs (F1 to F256) of the total 16-bit VCI, the control unit 404 outputs the lower 8-bit VCI.

According to a preferred embodiment of the present invention, the control unit 404 first searches for an idle path by the above-described operation when a call request signal is received, and if there is an idle path, an idle channel among idle channels among a plurality of channels assigned to the idle path. If we search again, we can see that when an idle channel is detected, we assign the corresponding VPI / VCI to the requested call.

When the idle channel is allocated among the plurality of channels assigned to the idle path by the above process, the controller 404 controls the corresponding memory 432 so that the idle state flag corresponding to the allocated channel is switched to the use state flag. In addition, when the last remaining idle channel among the plurality of channels assigned to the idle path is allocated and used, the controller 404 causes the idle state flag corresponding to the channel to be switched to the use state flag, and the path to which the channel belongs. The memory 413 is controlled to switch the idle state flag corresponding to the use state flag.

If a call request signal is provided to the controller 404 while all the flags stored in the memory 413 become the use state flag, the controller 404 notifies the congestion state.

As described above, the present invention has the effect of efficiently performing a search for allocating VPI / VCI to shorten the search time and reducing the memory capacity for VPI / VCI allocation.

Claims (13)

A first count that sequentially searches an idle state of each path assigned to the asynchronous transmission mode, selects an idle path, and provides a VPI of the selected idle path, and counts the number of each path assigned to the asynchronous transmission mode A section 411, a path selecting section 412 for selecting a path corresponding to a count value of the first counting section 411, and a flag indicating an idle / use state of each of the paths, and storing the first If an address corresponding to the count value of the counting unit 411 is designated, the memory 413 outputting an idle / usage state flag of a path corresponding to the specified address and the path selected by the path selecting unit 412 are idle. In one case, an idle path detector 401 including a VPI provider 414 for providing a corresponding VPI; A second count unit 402 for counting the number of channels assigned to each path; A count value of the second count unit 402, which is composed of a plurality of idle paths corresponding to the number of idle paths of the idle path detector 401, and is assigned to an idle path selected by the idle path detector 401. A plurality of idle channel detectors 403 for selecting an idle state channel corresponding to and providing VCI of the selected idle state channel; And a control unit (404) for controlling the idle path detector (401) and the idle channel detector (403) to provide the VPI / VCI to the requested call when a call is requested. The method of claim 1, wherein the path selector 412: A plurality of OR gates are arranged in parallel to output only the OR gate corresponding to the count value of the first count unit 411, and the other OR A gate is a VPI / VCI allocating apparatus of the asynchronous transmission mode consisting of an ora gate array (A1 to An) for outputting a high signal. 3. The VPI providing unit 414 is connected to the respective OR gates of the OR gate arrays A1 to An in a one-to-one correspondence to output the output of each OR gate and a path idle / use state of the memory 413. An apparatus for allocating a VPI / VCI in an asynchronous transmission mode composed of a plurality of OR gate arrays B1 to Bn for outputting a logical sum of flags. 5. The apparatus of claim 2 or 4, wherein the first count (411) comprises: an eight-speed counter. 5. The apparatus of claim 4, wherein the ora gate arrays (A1 to An) are: 256 asynchronous transmission modes. 5. The apparatus of claim 4, wherein the OR gate arrays (B1 through Bn) are: 256 in asynchronous transmission mode. 4. The apparatus of claim 2 or 3, wherein the first count unit (411) comprises: a 12-stage counter. 8. The apparatus of claim 7, wherein the OR gate arrays (A1 to An) are: 4096 in asynchronous transmission mode. 8. The apparatus of claim 7, wherein the ora gate arrays (B1 through Bn) comprise: 4096 asynchronous transmission modes. The idle channel detection unit 403 is configured to: select a channel corresponding to a count value of the second count unit 402, when the idle channel detection unit 401 corresponds to an idle path selected by the idle path detection unit 401. A decoder 431 enabled; A flag indicating an idle / use state of each channel assigned to each path is stored, and if an address corresponding to a counter value of the second count unit 402 is specified, an idle / use state flag of a channel corresponding to the specified address. A memory 432 for outputting the same; The VPI / VCI allocation apparatus of the asynchronous transmission mode configured by the VCI providing unit (433) for providing a VCI corresponding to the channel selected by the decoder (431) in the idle state. The VCI providing unit 433 according to claim 10, wherein the VCI providing unit 433 comprises: a plurality of channels corresponding to a plurality of channels assigned to each path to output the decoder 431 and the channel idle / use state of the memory 432. OR gates (C1 to Cn) for ORing flags to provide VCI high 8 bits; A plurality of FIFOs (FI to FI) that are connected in a one-to-one correspondence with the respective oar gates of the oar gate arrays C1 to Cn to provide VCI lower 8 bits when data is input from each oar gate of the oar gate arrays C1 to Cn. VPI / VCI allocation unit in asynchronous transmission mode configured with Fn). 12. The apparatus of claim 11, wherein the second count unit (402) comprises: an eight-speed counter. 13. The apparatus of claim 12, wherein the ora gate arrays (C1 to Cn) are configured in 256 asynchronous transmission modes.