JPH06276209A - Traffic shaping device for atm network - Google Patents

Abstract

PURPOSE:To provide a traffic shaping device of a simple constitution which can perform the traffic shaping operation with high efficiency in an ATM network where plural VPs or VCs are handled. CONSTITUTION:An ATM cell memory 1 is provided to temporarily store the cell to be supplied to an input line 5 until it is ready to be sent, together with an output timing deciding part 2 which decides the time when the input cell is sent out of a VP or VC, a read control memory 3 which stores the cells that are sent at each time, and a clock part 4 which shows the present time. Then the input cell is written in the memory 1 and at the same time the part 2 decides the time when the cell is sent out from the present time that is decided by the characteristic or the history set in response to the VP or VC. Then the cell read-out information is written in the memory 3 to read out the cell corresponding to the decided time. A readable cell is detected out of the memory 3 based on the present time information of the part 4. Then the detected cell is read out of the memory 1.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an ATM (Asynchronous T
ransfer Mode) A traffic shaping device in a network.

In recent years, BISDN (Broadband ISDN: Broad
-Ban ISDN) has been actively studied as a network compatible with ATM technology. In this ATM network, all digital information is converted into fixed length data called cells and transmitted. Each cell consists of a 5-byte header and a 48-byte information field, and the header has a predetermined number before communication starts.
VPI (Virtual Path Identifier)
And VCI (Virtual Channel Identifier) are included in the ATM network.
Control of switching of transmission paths in switching devices and transmission devices is performed by identifying PI / VCI, and statistical multiplexing of a plurality of VPs or VCs is performed for one line based on the traffic characteristics of each VP or VC. ing. Therefore, if the traffic characteristics (average used bandwidth, maximum bandwidth, etc.) determined for each VP or VC and the traffic characteristics actually transmitted are different, an abnormal buffer overflow occurs in the ATM switch, resulting in a quality of service. Can be very bad.

Therefore, it is necessary to perform traffic shaping (smoothing) by the ATM switch so that the actual traffic characteristics satisfy the predetermined traffic characteristics.

[0004]

2. Description of the Related Art FIG. 6 shows a conventional configuration example. In the figure, 60 is an input line, 61 is a discriminating device which discriminates the VPI (or VCI) of the ATM cell header and generates a write signal corresponding to the discrimination result, and 62 is each VPI (or VCI)
Cell FIFOs (corresponding to cell FIFOs # 0, # 1 ...) that sequentially store ATM cells having respective VPIs (or VCIs) and read out in the order of storage,
63 is provided in each cell FIFO and each VPI
(Or VCI) is an output enable determination device that controls the output of ATM cells at a frequency corresponding to the use band previously declared by the user, and 64 is one cell FIFO in response to a read request from a plurality of cell FIFOs. , A contention adjusting device for generating a read signal for permitting reading, and 65 is an output line for generating ATM cells read from a plurality of cell FIFOs.

To explain the operation of the conventional example, the input line 6
ATM cells containing a plurality of VPIs and VCIs in the header are multiplexed and input to 0. These ATM cells are V
The frequency and distribution that occur depending on the usage status of communication corresponding to PI and VCI are not constant, and do not necessarily fall within the usage band previously declared by the user.

The discriminating device 61 discriminates the VPI in the header of each ATM cell to be input, and determines each VPI (or VCI).
Corresponding to the cell FIFO # 0, FIFO # 1, ... Generate a corresponding write signal w. In the following description, each cell FIFO is associated with each VPI (VP0, VP1, ...
An example of writing an ATM cell corresponding to

Each of the cell FIFOs # 0, # 1 ... Is provided with an output enable determination device 63, and each output enable determination device 63 has a use band previously declared by the user corresponding to each VPI. The read cycle (time) corresponding to is set, the read request signal q is generated when the read cycle is reached after the previous read is judged. This read request signal q is input to the competition adjustment device 64, and is adjusted when competing with the read request signal q from the other output enable determination device 63, and at the same time outputs only one read signal r. Cell FIFO to which read signal r is input
62 reads the ATM cell stored at the head and outputs it to the output line 65. The read signal r is also supplied to the output feasibility discriminating device 63 corresponding to the cell FIFO 62 that has read out, and starts the timing of the next read cycle.

In this way, the AT input from the input line
The M cells are output by adjusting the cycle (interval) of the ATM cells of each VPI so that the V cells (or VCI) fit into the band declared by the user in advance, and traffic shaping (smoothing) is realized. It

[0009]

In the above-mentioned conventional system, it is necessary to provide a discriminating device for discriminating whether or not transmission is possible at the present time from the past transmission history for each VP or VC. When a large number of VPs or VCs are used, there is a problem that a large processing capacity is required for this discriminating device and the amount of hardware becomes large.
When the number of VPs or VCs increases, the cell FIFO
There is a high possibility that requests for reading from O will occur at the same time, and the load on the contention adjustment device will increase.

An object of the present invention is to provide a traffic shaping device in an ATM network which can efficiently perform shaping with a simple structure.

[0011]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 1 is an ATM cell memory for temporarily storing an input cell until it can be transmitted, and 2 is an input A.
An output timing discriminating unit for discriminating and outputting the time when the TM cell can be output, 3 is a read control memory for storing the read information for reading the cell from the ATM cell memory 1 in correspondence with the time when the cell can be outputted, and 4 is a current control memory. Clock part that generates time,
5 is an input line to which an input ATM cell is input, 6 is an output A
This is an output line output by the TM cell.

According to the present invention, the cell input to the line of the ATM network is written in the ATM cell memory and, at the same time, the V
The time at which the cell should be read is determined based on P or VC and stored in the read control memory in association with the read information of the ATM cell memory. At the corresponding time, the read control memory is read and the output information is stored. It is used to read the corresponding cell from the ATM cell memory.

[0013]

The cell input from the input line 5 is stored in the ATM cell memory 1 and, at the same time, the VP or VC of the input cell in the output pair discrimination VP2 and the current time given from the clock unit 4 are used. On the other hand, the band which is set in advance by the declaration or the like and the outputable time corresponding to the past history (previous outputable time) are discriminated and output to the read control memory 3. At this time, the cell read information necessary for reading the cells stored in the ATM cell memory 1 is supplied to the read control memory 3. In response to this, the read control memory 3 stores cell read information corresponding to the time when the cell can be output. The read control memory 3 uses the information on the current time generated from the clock unit 4 to determine the cell whose output time is the current time, reads the read information, and supplies it to the ATM cell memory 1. Based on this read information, the corresponding cell is read from the ATM cell memory 1 and output to the output line 6.

[0014]

FIG. 2 is a block diagram of the first embodiment. In the first embodiment, the ATM cell memory of FIG.
It is configured by a divided cell FIFO having an O (First In First Out type memory), and is characterized in that VP (or VC) is stored in a read control memory with time as an address.

In FIG. 2, reference numeral 20 denotes a divided cell FIF.
O and 200 are cell FIFOs individually provided corresponding to each VP (or VC), 201 is a first decoder that generates a write signal, and 202 is a second decoder that generates a read signal. Reference numerals 21 to 25 correspond to 2 to 6 in FIG. 1, 21 is an output timing discriminating unit, 22 is a read control memory, 23 is a clock unit, 24 is an input line, and 25 is an output line.

The operation of the first embodiment will be described. For the cell input from the input line 24, the first decoder 201 identifies the VP (or VC) in the header, and the identified V
One cell FIFO 200 corresponding to P (or VC)
A write signal is output to and written in. Cell FIFO2
In 00, the same VP (or VC) is sequentially written.

Simultaneously with writing, the output timing discriminating unit 21 responds to the VP (or VC) of the input cell by the following band corresponding to the band previously set by the declaration or the past history (previous output possible time). The cell output available time is discriminated and output to the read control memory 22. Read control memory 22
Finds a received available output time or, if the available output time is closed, a vacant time close to that time and stores it as an address and stores VP (or VC) as data.

On the other hand, the read control memory 22 is a memory that performs a read operation simultaneously with writing, and the current time information from the clock unit 23 is always input, and when this current time information is read as an address, the read address is stored in that address. The stored VP (or VC) is read. This VP (or VC) is decoded in the second decoder 202,
One corresponding read signal is generated. The cell FIFO 200 receiving the read signal reads the head of the stored cell and outputs it to the output line 25. In this way, the respective cell FIFOs 200 are output to the output line 25 at a frequency corresponding to the determined band without overlapping each other.

FIG. 3 is a block diagram of the second embodiment. In the case of the second embodiment, a random access type cell memory is used, the write address sequence is written in the address management memory for each VP (or VC), and the address management memory is set to each VP (or VC) at the time of reading. The feature is that the corresponding start address is extracted.

In FIG. 3, reference numeral 30 is a shared cell buffer, 300 is a cell memory, 301 is a write address for writing an input cell into the cell memory 300, and the VP (or VC) is stored in the cell memory 300. The write control unit for writing the write addresses of the above into the address management memory in the order of the input cells, the write address corresponding to the VP (or VC) generated by the write control unit 301 is written in the write control unit 301, and the VP (or The address management memory 303 reads out the top address corresponding to VC) and the read control unit 303 reads the top address corresponding to the VP (or VC) from the address management memory 302 and supplies it to the cell memory 300. Further, 31 is an output timing discrimination unit, 32 is a read control memory, 33 is a clock unit, 34 is an input line, and 35 is an output line.

The operation of the second embodiment will be described. The cell input from the input line 34 is written in the cell memory 300 according to the write address generated from the write control unit 301 of the shared cell buffer 30 and is written. Control unit 30
1 identifies the VP (or VC) of the input cell and sets the write address to the cell memory 300 to the address management memory 30.
2 is sequentially written for each VP (or VC). In this case, the address management memory 302 stores each VP (or V
An area corresponding to C) is determined, a function of performing reading in the order of writing is provided, and a FIFO type memory can be used.

In parallel with the write operation to the shared cell buffer 30, the output timing discriminator 31 operates in the same manner as the output timing discriminator (21 in FIG. 2) of the first embodiment so that the VP (or VC) of the input cell is ), The available output time is determined and output to the read control memory 32. The read control memory 32 operates in the same manner as in the first embodiment (22 in FIG. 2), finds the received available output time or, if the available output time is closed, finds a vacant time close to that time and sets it as an address. When VP (or VC) is stored as data and the current time information from the clock unit 33 is read as an address, the corresponding VP (or VC) is read.

VP read from the read control memory 32
When (or VC) is input to the read control unit 303 of the shared cell buffer 30, when the VP (or VC) is used to read from the address management memory 302, the VP (stored in the address management memory 302 is read. Or V
The head of the column of write addresses corresponding to C) is read. The read control unit 303 uses the address management memory 302
The address obtained from is input to the cell memory 300 as a read address. As a result, the cell memory 300
From, the leading cell of the corresponding VP (or VC) is read and output to the output line 35.

FIG. 4 is a block diagram of the third embodiment. In the third embodiment, an address FIFO is provided as a means for simplifying the configurations of the write control unit, the read control unit and the address management memory in the configuration of the second embodiment (FIG. 3), and the read control memory writes the cell memory. The embedded address is stored.

In FIG. 4, 40 is a shared cell buffer, 400 is a cell memory, and 401 is an address FIF in which read addresses output from the read control memory are sequentially stored.
It is O. 41 is an output timing discriminating unit, 42 is a read control memory in which a cell memory address is stored with time as an address, 43 is a clock unit, 44 is an input line, and 45 is an output line.

The operation of the third embodiment will be described focusing on the points different from the second embodiment. The cells input from the input line 44 are the cells of the shared cell buffer 40.
00 and is written to the write address output from the address FIFO 401, and at the same time, this write address (referred to as a cell memory address) is supplied to the read control memory 42.

On the other hand, the output timing discriminating section 41 discriminates the output available time of the cell corresponding to the VP (or VC) at this time and outputs it. The read control memory 42 stores the cell memory address with the output available time or a vacant time close to the output available time as an address. When reading is performed using the time output from the read control memory 42 from the clock unit 43, the cell memory address is read from the corresponding address. This cell memory address is the cell memory 4
The cell supplied as the read address for 00 is read and output to the output line 45.

On the other hand, the cell memory address output from the read control memory 42 is also supplied to the address FIFO 401 and stored in order at each address. Since this cell memory address is the address of the cell for which reading has been completed, when the address FIFO 401 is read next time, the input cell can be used as the address for writing.

FIG. 5 shows a concrete example of the configuration of the third embodiment shown in FIG. In FIG. 5, parts 50 to 55 correspond to the parts indicated by the reference numerals 40 to 45 in FIG. 4 and have the same names. However, the output timing determination unit 51, the read control memory 52, and the clock unit 53 are different from those in FIG. 4 in that internal configuration examples are shown, and the output timing determination unit 51 corresponds to VCI (VC identifier). The memory 511 stores therein the read interval set by the above, the memory 512 in which the output available time corresponding to each VCI is stored, and the output timing discriminating unit controller 510. The read control memory 52 includes a memory 520 and a read memory control unit 521. The clock unit 53 includes a cell unit counter 530 that counts a signal generated in a cell unit (time length of one cell).

In the configuration example of FIG. 5, shaping is performed so that the rate falls within a rate corresponding to the peak rate (maximum communication speed declared by the user) for each VC, and the operation will be described below.

When a valid cell is input to the shared cell buffer 50 from the input line, the empty address of the cell memory 500 output from the address FIFO 501 is taken out, and the cell is written in the cell memory 500 using this as a write address. The VCI (VC identifier) of the input cell is
It is supplied to the output timing determination unit control unit 510 of the output timing determination unit 51. Output timing determination unit control unit 5
Reference numeral 10 designates the memory 5 using the input VCI as an address.
The outputable time set to 12 is taken out, and the outputable time and the cell unit counter 53 generated from the clock unit 53 are taken out.
The current time, which is an output of 0, is compared, and the larger time is output to the read control memory 52 as the output available time.

The read memory control section 5 of the read control memory 52
Reference numeral 21 sequentially searches the memory 520 using the input available output time as an address, and writes the write address (cell memory address) output from the shared cell buffer 50 to the vacant address (corresponding to the time). . Also,
The time corresponding to the written address is supplied to the output timing discriminating unit 51 as the read set time.

The output timing discriminating section 51 includes a memory 51.
The read interval corresponding to the VCI is taken out from 1, and the read set time received from the read control memory 52 is added to obtain the next output available time. The output available time is set at the position of the VCI in the memory 512.

When the cell is read, the read control memory 52
When the read memory control unit 521 of FIG. 2 uses the current time output from the clock unit 53 as an address and reads the memory 520, the corresponding cell memory address is extracted and supplied to the shared cell buffer 50 as a read address. Cells are read out and output to the output line 55. This cell memory address is the address FIFO5
It is also input to 01 and written as a free address.

Although the example of FIG. 5 has been described as a VC shaper that performs shaping for VCI, it may be configured as a VP shaper that performs VPI. Further, although the configuration for inputting / outputting the cell memory address is used as the shared cell buffer, as in the second embodiment shown in FIG.
As a configuration for handling VCI or VPI as data of the read control memory, a shared cell buffer for inputting / outputting cells using VPI or VCI as a key may be used.

Further, the output timing discriminating section 51 of FIG.
Has a configuration for calculating the next available output time from the minimum read interval for each VP or VC, but a known algorithm such as a leaky bucket, a jumping window or a sliding window can be applied.

Further, when writing to the read control memory 52, a method of searching for an available time is adopted, but if the available output time received is not available, the previously secured one is shifted to make an available time. , A method of storing the newly input cell memory address there may be adopted.

[0038]

According to the present invention, a plurality of Vs can be obtained by previously determining the output time when a cell is input in an ATM network.
It is not necessary to determine whether or not P or VC can be simultaneously sent, the structure of the traffic shaping device can be simplified, and the competition control in the output line can be eliminated.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a first embodiment.

FIG. 3 is a configuration diagram of a second embodiment.

FIG. 4 is a configuration diagram of a third embodiment.

FIG. 5 is a specific configuration example of the third embodiment.

FIG. 6 is a conventional configuration example.

[Explanation of symbols]

 1 ATM cell memory 2 output timing determination unit 3 read control memory 4 clock unit 5 input line 6 output line

Claims (4)

[Claims] 1. In an ATM network that handles a plurality of VPs or VCs, an ATM cell memory that temporarily stores a cell input to a line until it can be sent out, and a time of output based on the VP or VC of the input cell. An output timing discriminating section for discriminating between, a read control memory for storing cells output at each time,
When a cell is input, the cell is written into the ATM cell memory and at the same time, the cell is read from the current time determined by the characteristics and history set corresponding to the VP or VC of the cell. The output timing determination unit determines the time to be output, the cell read information for reading the cell corresponding to the determined time is written in the read control memory, and the current time information generated from the clock unit can be used for reading. A traffic shaping device in an ATM network, wherein read information of a cell is detected by the read control memory, and a cell is read from the ATM cell memory based on the detected cell read information. 2. The ATM cell memory according to claim 1, wherein the ATM cell memory is configured by using a plurality of cell FIFOs for individually storing cells for each VP or VC, and the time output from the output timing discrimination unit is addressed. As the VP or VC of the input cell is written in the read control memory, the VP or VC written in the read control memory is read using the current time as an address, and the VP or VC read from the corresponding FIFO A traffic shaping device in an ATM network characterized by reading one cell. 3. The ATM cell memory according to claim 1, wherein the ATM cell memory is configured by using a shared ATM cell buffer shared by all VPs or VCs, and the time output from the output timing determination unit is input as an address. The VP or VC of the read cell to the ATM, and one cell corresponding to the VP or VC written in the read control memory with the current time as an address
A traffic shaping device in an ATM network characterized by reading from a cell buffer. 4. The ATM cell memory according to claim 1, wherein the shared cell buffer is shared by all VPs or VCs, and the shared cell buffer is a cell memory and a write operation of the cell memory. An address FIFO for outputting an address is provided, and a write address of the cell buffer in which the input cell is written is written in the read control memory with the time output from the output timing determination unit as an address, and the current time is The ATM is characterized in that a write address written in the read control memory is read as an address, and the read write address is used as a read address for reading one cell from the cell memory and inputting it to the address FIFO. Traffic shaping device in network.