KR100236605B1 - Cell multiplexer for connecting atm net of atm card - Google Patents

Abstract

In particular, the present invention relates to a device for connecting a terminal equipped with a low-speed ATM (Asynchronous Transfer Mode) connection card and a high-speed ATM network, And more particularly, to a cell multiplexing apparatus for ATM connection of an ATM connection card capable of transmission through a network transmission line.

It is an object of the present invention to provide a method and apparatus for multiplexing ATM cells from an ATM connection card installed in each terminal and effectively connecting to an ATM network while maintaining a bandwidth that is used when a service using only a part of a given bandwidth is performed or not used So that the connection of the terminal equipped with the ATM connection card to the ATM network can be effectively performed and the bandwidth allocated to each terminal can be efficiently used.

According to the present invention, in order to efficiently apply a desktop ATM card configured at 25 Mbps to an ATM exchange, a multiplexing board can be configured in the middle to efficiently aggregate cells, thereby effectively using a bandwidth that is not sufficiently used in a desktop The number of subscribers accommodated in the multiplexing board is increased so that network configuration, maintenance, and desktops can be easily and cost effectively used in ATMs.

Description

A cell multiplexing apparatus for connecting an ATM connection card to an ATM network

In particular, the present invention relates to a device for connecting a terminal equipped with a low-speed ATM (Asynchronous Transfer Mode) connection card and a high-speed ATM network, And more particularly, to a cell multiplexing apparatus for ATM connection of an ATM connection card capable of transmission through a network transmission line.

Generally, each terminal operates in accordance with a communication protocol for a non-BISDN (Broadband Integrated Services Digital Network), and each terminal is connected to an ATM network through a BISDN matching device.

Nowadays, each terminal is directly connected to the ATM network without using a BISDN matching device.

That is, an ATM connection card for connecting data generated by each terminal to an ATM network by converting it into an ATM cell has been developed.

This ATM connection card is mounted directly to the terminal and tries to access the ATM network at a transmission rate of 25.6 Mbps while making the data of the terminal into 53-byte ATM cells. At this time, each of the terminals does not use all of the bandwidth of 25.6 Mbps allocated to the transmission path to the ATM network.

However, since the transmission rate of the ATM network is 155.52 Mbps, at least six data having a transmission rate of 25.6 Mbps are required.

That is, when signals from at least six subscribers are simultaneously multiplexed and transmitted to the ATM network, data can be sent at a transmission rate required by the ATM network.

In view of the above, the present invention provides a service that uses only a part of the bandwidth given to each connection card while effectively connecting the ATM cells from the ATM connection card installed in each terminal to the ATM network, It is possible to effectively connect a terminal equipped with an ATM connection card to an ATM network and to efficiently use a bandwidth given to each terminal by providing a device that makes it easy to expand the number of subscribers by using the remaining bandwidth To be able to do so.

In order to achieve the above object, the present invention provides a cell multiplexing apparatus for connecting an ATM network of an ATM connection card to an ATM network of each terminal, in order to connect an ATM connection card for generating data of a terminal to a low- A cell matching unit configured to connect a plurality of terminals with respect to a bandwidth of a high-speed ATM cell while performing a low-speed physical layer connection with an ATM connection card of each terminal; A multiplexing module for multiplexing the ATM cells extracted by the cell matching units; A framer for configuring an STM-1 class to transmit ATM cells multiplexed in the multiplexing module at a high speed; And a physical layer connection matching unit for inputting cells from the ATM network while transmitting cells configured in the framer to the ATM network over a long distance.

1 is a block diagram of a configuration of a cell multiplexing apparatus according to the present invention;

FIG. 2 is a detailed block diagram of the multiplexing module in FIG.

3 (a) to 3 (b) are diagrams showing a structure of a memory constituting a weight setting unit in FIG. 2,

4 (a) to (b) are operational flowcharts for cell multiplexing according to the present invention,

Description of the Related Art

1-1 to 1-N: terminals 10-1 to 10-N:

20: multiplexing module 21: network side signal cell controller

22: CPU signal control unit 23: Weight setting unit

24: port control signal management unit 25: input port determination unit

26-1 to 26-N: Input Phosphor 27: Output Phosphor

28: FIFO control unit 29: input cell control unit

30: framer 40: physical layer connection matching unit

Hereinafter, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a cell multiplexing apparatus according to the present invention. FIG. 2 is a detailed block diagram of a multiplexing module in FIG. 1. FIG. (a to b) are operation flowcharts for cell multiplexing according to the present invention.

The configuration of the present invention according to Fig. 1 includes cell matching sections 10-1 to 10-N, a multiplexing module 20, a framer 30, and a physical layer connection registration section 40. [

The cell matching units 10-1 to 10-N perform a low-speed physical layer connection with the ATM connection card of each of the terminals 1-1 to 1-N, so that more terminals than the bandwidth of the high- To be connected.

That is, this means that the calculated value (155.52 Mbps≈25.6 Mbps *) is calculated by using the property that various application programs performed by each of the terminals 1-1 to 1-N do not actually use the bandwidth (25.6 Mbps) 6) to accommodate as many users as possible in a given bandwidth.

The multiplexing module 20 multiplexes the ATM cells extracted from the cell matching units 10-1 to 10-N so that the ATM cells can be loaded in the transmission path of the high-speed ATM network.

The framer 30 is configured as an STM-1 class in order to transmit ATM cells multiplexed by the multiplexing module 20 at a high speed.

The physical layer connection matching unit 40 is for inputting ATM cells from the ATM network while transmitting cells configured in the framer 30 to the ATM network over a long distance.

The configuration of the multiplexing module 20 will be described in detail with reference to FIG.

This configuration includes a network side signal cell control unit 21, a CPU (Central Processing Unit) signal control unit 22, a weight setting unit 23, a port control signal management unit 24, an input port determination unit 25, Input ports 26-1 to 26-N, an output port 27, a forward control unit 28, and an input cell control unit 29. [

The network side signal cell controller 21 detects signal cells among cells transmitted from the network.

The CPU signal controller 22 transmits the signal cell from the network signal cell controller 21 to a CPU (not shown) provided in the system, and stores information on the signal cell, that is, the bandwidth requested by the specific port, And the like.

The weight setting unit 23 sets the weight of the input port from each terminal by the signal cell analysis by the CPU interfaced by the CPU signal control unit 22. [

In this case, when a call setup is requested for each input port for the first time, a weight is set in the signal cell to be transmitted to the network side, and a bandwidth to be used among the allocated paths is set. .

At this time, the weight setting unit 23 is composed of two memories as shown in FIG. 3 (a) to (b).

That is, the first memory according to FIG. 3A stores a weight value for the input port being operated. The memory stores a flag bit for each memory area corresponding to each VC (Virtual Connection), and a comparator And a second weight value bit set to a weight value set by the CPU signal controller 22, wherein the first weight value bit is incremented by 1 every time the cell is read out once at the input port of the path, The virtual path identifier (VPI) and the virtual channel identifier (VCI) of the ATM cell are 4 bits (2 ⁴ ), 6 bits (2 ⁶ ), and 4 bits (2 ⁶ ) respectively in the second memory of FIG. The number of VCs is 2 ¹⁰ (VCI * VPI = 2 ¹⁰ ), so that the size is 1 byte per VC, and the whole is 1 KByte.

The second memory according to FIG. 3B includes a call setup bit indicating that a call setup related signal cell is input from a network side for each memory area allocated to each input port, a 4-bit VPI bit for informing a virtual path number used by the corresponding input port, And a 6-bit VCI bit for indicating a virtual channel number used in the corresponding input port. At this time, the sizes of VPI and VCI are designated as 1 bit and 2 bytes by 4 bits and 6 bits, respectively, because the number of subscribers to be subscribed to the system is not so large.

The port control signal management unit 24 analyzes the signal from each terminal given by the cell matching units 10-1 to 10-N of FIG. 1 to analyze which input port currently has a cell to transmit.

The input port determination unit 25 analyzes signals from the weight setting unit 23 and the port control signal management unit 24 to determine which input port cell should be preferentially read.

The input ports 26-1 to 26-N temporarily store cells transmitted from the cell matching units 10-1 to 10-N of FIG. 1, and the cell matching units 10-1 to 10- N are configured.

The output fiber 27 records cells stored in the input ports 26-1 to 26-N and outputs the cells to the framer 30.

The fire control unit 28 analyzes a signal given to the framer 30 shown in FIG. 1, and causes a cell written in the output fiber 27 to be output to the framer 30.

The input cell control unit 29 reads cells from the input ports 26-1 to 26-N of the input ports determined by the input port determination unit 25 and writes them to the output port 27. [

Hereinafter, the operation of the present invention will be described.

If a specific input port is configured to transmit a signal cell requesting call setup to the network, the network analyzes the signal cell and transmits the signal cell to the multiplexing module 20 through the physical layer connection matching unit 40 and the framer 30, .

The signal cell controller 21 of the multiplexing module 20 extracts the signal cell from the network and transmits the signal cell to the CPU through the CPU signal controller 22 to analyze the bandwidth requested by the specific port and the type of the service do.

When the analysis by the CPU is completed, the VPI and the VCI are recorded in the second memory of the weight setting unit 23 through the CPU signal control unit 22, and the weight value is recorded in the VC of the first memory according to the VPI and VCI .

On the other hand, the port control signal management unit 24 analyzes the port control signal given by the cell matching units 10-1 to 10-N that interface the ATM cells sent from the ATM connection card installed in each terminal, And transmits the data to the input port determination unit 25. The input port determination unit 25 determines whether the cell has a cell to transmit.

The input port determination unit 25 determines which port cell is to be preferentially read based on the signal given by the weight setting unit 23 and the port control signal management unit 24 and informs the input cell control unit 29 At this time, the input cell controller 29 reads the cells recorded in the input ports 26-1 to 26-N corresponding to the specific port determined by the input port determination unit 25, As shown in Fig. The data recorded in the output FIFO 27 is then output to the framer 30 by the FIFO control unit 28 which controls the output of the output FIFO 27 in accordance with the control signal from the framer 30.

Here, if the operation of the input port determination unit 25 is examined in detail, the internal operation operates according to the type of the state signal, and the operation to be performed is determined for each state.

That is, the number of the status signals is about 82, which is derived in the following calculation process.

The transmission rate 155.52Mbps indicates that the amount of data that can be processed per second is 19.44MB, so the time required to process one byte is 51.44ns. As a result, the time required to process the 53-byte ATM cell is 2.73 s.

Thus, when the input ports 26-1 to 26-N having data processing units of bytes are driven at 33 MHz, the time required for processing one byte is required to be 30.3 ns. However, since the time required for the entire processing of the ATM cell at the transmission rate of 155.52 Mbps is 2.73 占 퐏, the status signal becomes about 82 for the 30.3ns.

Thus, 29 status signals can be used for determination of the input port in the input port determination unit 25, except for 53 status signals required for processing the cell among the 82 status signals.

In response to the generation of the status signal, the input port determination unit 25 determines the input port by referring to the stored value of each memory configured in the weight setting unit 23. [

These operations will be described in more detail with reference to the multiplexing operation flowchart of Fig. 4 (a) to (b).

4A, various bits used in each memory of the weight setting unit 23 are cleared (step S1).

If the call setup cell is transmitted from the network, the call setup bit of the corresponding input port is set to '1' in the second memory of FIG. 3B, and the VPI / VCI value used in the port is recorded. And writes the weight value in the second weight bit of the VC of the first memory in Fig. 3A according to the VPI / VCI (steps S3 to S4).

At this time, when an SOC (Start Of Cell) signal that operates at an active low is generated every 2.75 ㎲ s, the state signal generator (FSM) in the input port determination unit 25 is operated (steps S5 to S6).

The operation according to the signal generated by the state signal generator in the input port determination unit 25 operating in accordance with the SOC is as shown in FIG. 4B.

The status signal generated from the status signal generator is composed of a total of 82 status signals. The FSM1 to FSM29 are provided with a weight setting unit 23, a port control signal management unit 24, an input port determination unit 25, an input cell control unit 29, And the input cells of the input ports determined above are read from the input ports 26-1 to 26-N and written to the output port 27 .

FIG. 4B shows the operating states from FSM1 to FSM29.

That is, the input port determination unit 25 designates the memory address of the specific input port X based on the signals from the weight setting unit 23 and the port control signal management unit 24 (step T1).

Then, it is checked from the second memory of the weight setting unit 23 whether the call set bit of the selected input port X is '1' (step T2). If it is confirmed that the call is set, the VPI / VCI is read and used Reads the flag bit and the first and second weight bits of the first memory of the weight setting unit 23, and searches for the comparator bit of the first memory indicating that there is an input cell (steps T4 to T6). At this time, if the call setup bit of the selected input port X is not '1', it is checked whether there is an input cell in the input ports 26-1 to 26-N of the corresponding port X (step T3) The seventh step T7 is executed (a). If there is no input cell in the step T3, the port X is excluded from the current access procedure. Therefore, the port number is increased by '1' to search for the next input port (step T11).

If it is determined in step T6 that the comparator bit is '0', it is determined to be a port to output the port X, and the first weight bit of the port X is incremented by '1' (step T7) ).

Then, the port determination part is informed to the input cell controller 29 to process the cells contained in the corresponding input ports 26-1 to 26-N (step T8). That is, after the input cells of the input ports 26-1 to 26-N are read from the input cell control unit 29 and recorded in the output FIFO 27, the FIFO control unit 28 controls the framer 30 ).

At this time, if the comparator bit is not '0' in the step (T6), even though the call setup bit is set for the corresponding input port (X), since there is no input cell, The port number X is incremented by one (step T11).

If the size of the first and second weighting bits recorded in the first memory of the weight setting unit 23 after the cell is processed in step T8 is equal to the size of the second weighting bit, The comparator bit in the first memory indicating that the input cell is present is set to '1' and the first weight bit is cleared to '0' (steps T9 to T10). If the values of the first and second weighting bits are not equal to each other in step T9, the port number of the input port X is increased by '1' to search for the next input port (step T11).

According to the above operation, every port to which a call is set is incremented by '1' every time the port is accessed, and a port to which a cell is accessed by a weight assigned to the port is changed to another Access will be aborted until the port's weight is exhausted

For example, when three input ports are set as a call, when the weight of the first port is set to '4', the weight of the second port is set to '3', and the weight of the third port is set to '1' The structure of the first memory of FIG.

Flag comparator first weight second weight

0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 1

0 0 0 0 0 0 0 1

In this case, since the port set to be accessed is accessed in a cyclic manner, cells of each port are processed in the first access, and only cells in the first and second ports are processed in the second and third accesses. In the fourth access, Only one port cell is processed.

If the comparator value of the currently set port is '1', the weight setting unit 23 changes the setting to '0' so that the cell can be processed at the next access.

As described above, according to the present invention, in order to efficiently apply the desktop ATM card configured at 25 Mbps to the ATM exchange, the multiplexing board can be configured in the middle to efficiently aggregate the cells, thereby effectively using the bandwidth The number of subscribers accommodated in the multiplexing board is increased so that network configuration, maintenance and desktops can be easily and cost effectively used in ATMs.

Claims (2)

A cell matching unit for performing a low-speed physical layer connection with an ATM connection card of each terminal; A multiplexing module for multiplexing the ATM cells extracted by the cell matching units; A framer configured to transmit STM-1 level to transmit ATM cells multiplexed in the multiplexing at a high speed; And a physical layer connection matching unit for inputting cells from an ATM network while transmitting cells configured in the framer over an ATM network over a long distance, the ATM multiplexing apparatus comprising: The multiplexing module includes: a network side signal cell controller for detecting a signal cell among cells transmitted from the network; A CPU signal control unit for receiving a signal cell from the network side signal cell control unit and receiving information about the signal cell while transmitting the signal cell from the network side signal cell control unit to a CPU configured in the system; A weight setting unit configured to set a weight of an input port from each terminal by a signal cell analysis by a CPU interfaced by the CPU signal control unit; A port control signal management unit for analyzing a signal from each terminal given by the cell matching unit and analyzing which input port has a cell to transmit; An input port determination unit for analyzing signals from the weight setting unit and the port control signal management unit to determine which input port cell is preferentially read; An input pie for temporarily storing cells transmitted from each of the cell matching units, the number of which is equal to the number of the cell matching units; An output pipeline for recording a cell stored in each input pipeline and outputting the cell to the framer; A phase control unit for analyzing a signal given from the framer and outputting a cell recorded in the output phase to a framer; And an input cell controller for reading the cell from the input port of the input port determined by the input port determination unit and writing the cell to the output port. A cell matching unit configured to connect a plurality of terminals with respect to a bandwidth of a high-speed ATM cell while performing a low-speed physical layer connection with an ATM connection card of each terminal; A multiplexing module for multiplexing the ATM cells extracted by the cell matching units; The method according to claim 1, The weight setting unit stores a weight value for the input port being operated, and includes a flag bit for each memory area corresponding to each VC (Virtual Connection), a comparator bit indicating that an input cell is present in the input port, A first memory for storing a first weighting bit which is incremented by 1 each time the cell is read out from the input port and a second weighting bit which is set to a weighting value set by the CPU signal control unit; A call setup bit indicating that a call setup related signal cell is input from the network side for each memory area allocated to each input port, a 4-bit VPI bit for indicating a virtual path number used by each input port, And a second memory for storing 6-bit VCI bits for indicating a virtual channel number.