JP3080787B2 - ATM switch circuit having broadcast function and broadcast output method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for implementing a broadcast function in a switch used in an ATM transmission apparatus and an ATM exchange.

[0002]

2. Description of the Related Art As a prior art in a broadcast system of an ATM transmission apparatus and an ATM exchange, Proceedings of t
he IEEE, Vol. 78, No. 1, January 1990, `` Fast Packet Swi
tch Architecture For Broadband Integrated Services
Digital Networks ”p145-146. According to the above conventional example, a buffer dedicated to broadcast cells is provided separately from a buffer storing received cells, and a broadcast cell is written into the broadcast cell dedicated buffer. Broadcasting is performed by reading.

[0003]

In order to realize the broadcast function shown in the above conventional example, it is necessary to provide a dedicated buffer for a broadcast cell as described above. Also, depending on the traffic volume of the broadcast cell, a large amount of cells must be accumulated, and the buffer size for the broadcast cell becomes very large. For this reason, there is a problem that hardware increases.

An object of the present invention is to provide an ATM switch circuit which realizes a broadcast function without providing a special buffer for a broadcast cell, and a broadcast output method thereof.

[0005]

According to the present invention, an ATM switch circuit connected to a plurality of input highways and output highways and switching a fixed-length cell arriving via the input highway to an output highway detects an arriving cell. A buffer memory for storing, an address memory provided corresponding to the output highway, for storing and outputting the cell storage address values of the buffer memory in the order of arrival, and an output highway for outputting the arriving cells, and analyzing the output highway. A write control unit that controls writing, a read control unit that instructs reading of the buffer memory, and a free address management unit that manages free addresses of the buffer memory; the write control unit is included in the arriving cell The routing information is analyzed and the address information corresponding to the output highway is analyzed. Li to instruct the storage of the address value,
A cell is written to the address by instructing the vacant address management means to output an address value, and it is determined whether or not a broadcast is to be performed. To the free address management means,
The vacant address management means outputs information and an address value indicating whether or not a vacant address becomes a vacant address when reading from the buffer memory when there is an instruction from the write control unit.
Referring to the information as to whether or not the address value output from the address memory becomes a free address, if the address is a free address, the address value is stored, and the read control unit outputs the address value to the address memory. By instructing, the cell of the buffer memory corresponding to the address value is read and output to the output highway corresponding to the address memory.

[0006] Further, there is further provided an address memory management means for managing the capacity of each address memory, and the write control section refers to the address memory management means in the case of a broadcast to output the address of the broadcast cell. Can detect a slower address memory.

The address memory management means is a counter provided for the address memory, monitors the input and output of the address value of each address memory, and counts the capacity of the address memory. The address memory is a FIFO.
It may be a memory.

All address memories have the same capacity, and the address memory management means is provided corresponding to the address memories, monitors the storage and output of the address values of each address memory, and stores the address values in the address memories. It may be a counter that counts the use area.

The vacant address management means refers to an address memory that outputs the address of the broadcast cell later,
At the time of reading, information as to whether or not the address becomes a free address is added to the address value and output. At the time of reading, the free address management means refers to the information of the address value and stores the address value in the case of a free address. I do.

The vacant address management means adds a flag to the address value when it is not a broadcast, and outputs the address value in the case of a broadcast. In the case of a broadcast, the address output of the broadcast cell is stored in an address memory which is slower. A flag is added to the address value to be output, and the other address values are output without a flag. At the time of reading, the vacant address management means refers to the address value and adds the flag. If there is, the address value may be stored.

Further, in the case of a broadcast, the free address management means adds a flag to an address value other than the address value stored in the address memory in which the address output of the broadcast cell is slower, and outputs the address. The address values other than are output without adding a flag, and at the time of reading, the empty address management means may refer to the address value and store the address value when the flag is not added. Good.

[0012]

The write controller analyzes the routing information contained in the arriving cell, determines whether or not it is a broadcast, and instructs the vacant address management means to output an address value, writes the cell to the address, and outputs the cell. Instruct the address memory corresponding to the highway to store the address value.

The vacant address management means indicates a vacant address. The specified address memory stores the address value. The counter provided corresponding to the address memory indicates the capacity of the address memory by counting up when the address value is stored and counting down when outputting the address value. In the case of the broadcast, the read / write control unit notifies the free address management means of the address memory having the largest capacity of the address memory as the address memory from which the address output of the broadcast cell is slower than the count value of each counter. .

The vacant address management means refers to an address memory in which the address output of the broadcast cell is slower and adds information to the address value as to whether or not the address becomes a vacant address at the time of reading, and outputs it.

At the time of reading, the read control unit causes an address memory to output an address value, reads a cell in a buffer memory corresponding to the address value, and outputs the cell to an output highway corresponding to the address memory. The vacant address management means refers to the information as to whether or not the output address value of the address memory becomes a vacant address,
If the address is a free address, the address value is stored.

According to the above means, the broadcast can be performed without providing a special buffer for the broadcast cell and without using the address value repeatedly.

[0017]

An embodiment of the present invention will be described with reference to FIG.
FIG. 1 shows that cells input from N input highways are N cells.
1 illustrates a common buffer switch type switch system that outputs after switching to a book output highway.

In FIG. 1, a multiplexing unit 3 is connected to a plurality of highways of input highways 1-1, 1-2,..., 1-N, cells arrive from each highway, and multiplex the cells. Output. The buffer memory 4 stores the arrival cell from the multiplexing unit 3. The write control unit 6 determines a cell routing information unit 31 based on the cell from the multiplexing unit 3.
To determine an output highway, and instruct the empty address management memory 9 to output an address value. The free address management memory 9 manages a write address, a read address, and a free address of the buffer memory 4. The vacant address management memory 9 is instructed from the write control unit 6 for the output highway, instructs the vacant address to the buffer memory 4 as a write address, and, at the time of reading, information as to whether or not the vacant address becomes an empty address and an address value. To the corresponding address memory. This information is obtained by attaching a flag to the address value. When there is an output of the address value with the flag of each address memory at the time of reading, it is determined that the address is a free address. At the time of broadcasting, the write control unit 6 instructs the output highway to broadcast and the address memory having a large capacity of the address memory,
Buffer memory with free address as write address
4 and the corresponding address memory are instructed, and an address memory having a large internal capacity is instructed by attaching a flag to the address value. That is, when detecting the flag, the free address management memory 9 determines that the address is a free address. The address memories are provided corresponding to the output highways, respectively, and store and output the address values of the buffer memory. The counter is address memory management means, and is provided corresponding to the address memory, and indicates the internal capacity of the address memory (the length of the queue). The read control unit 7 sequentially instructs each address memory to read cells in the buffer memory 4 in order to read cells in output highway units. The separation unit 5 outputs the output highways 2-1, 2-2,.
2-N, and outputs the cell to the corresponding output highway in synchronization with the reading of the cell from the buffer memory 4.

FIG. 2 shows the structure of a cell used in the description of this embodiment. In FIG. 2, routing information 31 is added to a cell defined in CCITT recommendation I.361, and the number of an output highway is described in the routing information section 31.
With this routing information, the write control unit 6 can perform switching.

Next, the operation in the configuration shown in FIG.
This will be described with reference to the processing flow in the write control unit 6 shown in FIG. In FIG. 1, arriving cells input from each input highway are multiplexed by the multiplexing unit 3 on a cell-by-cell basis, and then stored in the buffer memory 4 under the instruction of the write control unit 6. At this time, the output from the free address management memory 9 is used for the address value given to the buffer memory 4.

When a cell arrives (step 101), the write controller 6 determines whether or not the cell is a valid cell (step 102). If the cell is not a valid cell, the cell is discarded (step 107). In the case of a valid cell, it is determined whether the input highway and the output highway are 1: 1 (step 103). That is, it is determined whether it is a broadcast. 1: 1
In other words, if it is not a broadcast, as a normal process, the routing information section 31 of the cell is examined to analyze the output highway (step 104), determine the output highway, and instruct the corresponding address memory.

The write controller 6 stores the address value in an address memory corresponding to all output highways that output the cell. One counter is provided for each address memory. When one address value is stored in the corresponding address memory, 1 is added to the counter value, and when one address value is output, the counter value is reduced by one.
The internal capacity of each address memory is counted. Thus, the address queue can be registered (step 10).
5). The cell is written in the area of the buffer memory 4 corresponding to the address value stored in the address memory (Step 106). In the case of a non-broadcast cell, a flag signal is always added to an address value and then stored in an address memory.

The input highway and the output highway are 1:
At the time of the broadcast of n, the routing information section 31 of the cell is examined, the output highway is analyzed, and the broadcast location is specified (step 1).
08) The output highway is determined and instructed to all corresponding address memories. The address value specified by the free address management memory 9 is written to a plurality of address memories.
At this time, the write control unit 6 checks the output of the counter indicating the internal capacity of each address memory that stores the address value, specifies the address memory having the largest internal capacity, and instructs the free address management memory 9 (step 109). ). That is, the output of the address of the broadcast cell from the address memory having the largest content is the slowest since the reading is performed sequentially. The empty address management memory 9 adds a flag signal to the address value stored in the address memory having the largest content. If there are two or more address memories with the largest contents, select one of them,
A flag signal is added (step 110). For example, when reading cells from the buffer memory 4 in ascending order of the output highway number on the reading side of the buffer memory 4, the address memory corresponding to the highway with the largest output highway number is selected. Similarly, the counter adds one to the counter value when one address value is stored in the corresponding address memory, and decrements the counter value by one when one address value is output, thereby counting the internal capacity of each address memory. . The vacant address management memory 9 indicates the address value of the vacant address, and the cell is written in the area of the buffer memory 4 corresponding to the address value stored in the address memory (step 106).

On the output side of the buffer memory 4, the read control unit 7 instructs each address memory to read a cell in units of output highways. That is, one address value is sequentially read from the address memory uniquely corresponding to each output highway, and the value is supplied to the buffer memory 4 to output a cell. For example, the read control unit 7 instructs to read cells from the buffer memory 4 in ascending order of the output highway number. Furthermore, when the flag value appears at the same time when the address value is read, the free address management memory 9 stores the address value as a free address. When the flag signal does not appear, an operation of only outputting the cell from the buffer memory 4 is performed, and the address value is not stored in the free address management memory.

That is, in the case of a broadcast, the same address value is written to a plurality of address memories, so that in the uncontrolled state, a plurality of the same address values exist in the free address management memory. Therefore, the reading order of the output highway is determined in advance, and the flag signal is written in the address memory having the largest content. Then, only when the flag signal appears on the output side, if the address value is written in the free address management memory, the same address value does not exist in the free address management memory.
By this operation, it becomes possible to use the address value of the buffer memory in a circular manner and to realize the broadcast function.

As described above, in the above-described embodiment, the free address management memory determines whether the end of the broadcast output is available.
The longest queue in the address memory is instructed by the write control unit, and a flag is added to the address to be recorded in the longest address memory. Conversely, the free address management memory attaches a flag to an address that does not become a free address (an address other than the last output address at the time of broadcasting), and detects an address without a flag as a free address. You may. Thus, at normal times,
By adding identification information as to whether or not the address becomes a free address, and at the time of broadcasting, the write control unit instructs the longest queue of the address memory to determine whether or not the address in the address memory becomes a free address. It is determined whether or not the free address management memory is a free address.

In the above description of the embodiment of the present invention,
By measuring the amount of the address value in the address memory, the internal capacity of each address memory was counted, but by measuring the capacity of the unused area of the address memory,
It is also possible to identify the address memory that stores the most address values.

Further, the free address management memory or the write control unit may detect an address memory from which the output of the broadcast cell from each address memory is slower and detect that the free address has been reached. For example, the write control unit detects the number of times of broadcast from the routing information, stores the address value of the broadcast cell and the number of times of broadcast, and monitors the output of the address value of the broadcast cell at the time of reading. When the number of reports is output, the address may be an empty address.

Next, a detailed description of the above embodiment will be described with reference to FIG. FIG. 3 shows a switch system of a common buffer switch type that outputs cells input from N input highways after switching to N output highways. FIG. 3 further includes, in addition to the configuration shown in FIG. 1, a counter 22 and a selector 21 for instructing the first address at the time of startup into the free address management memory 9, and the other configurations have the same configuration. ing. In this case, the instruction of the trajectory of the counter and the selection of the selector 21
Instructed by the read control unit 7.

The cells input from each input highway are:
After being multiplexed in cell units by the multiplexing unit 3, the write control unit 6
Are stored in the buffer memory 4. The address value of the buffer memory 4 is used by taking out one address value from the free address management memory 9. The read control unit 7
At the initial setting stage (buffer memory 4 is empty)
The counter 20 is counted up by the capacity of the buffer memory 4 and the output thereof is used for the free address management memory.
In 9, all the address values of the buffer memory 4 are written.
At this stage of the initial setting, the selector 21 has selected the output of the counter 20, and after the initial setting, the output from each address memory is selected.

Next, the write controller 6 checks the routing information section 31 of the cell and determines an output highway. The structure of the cell used in the description of this embodiment is the same as that of the above embodiment, as shown in FIG. 2, except that a routing information section 31 is added to a cell defined in CCITT Recommendation I.361. Indicates the number of the output highway.

In FIG. 3, the write control unit 6 stores the address value of the buffer memory 4 in the address memory corresponding to all output highways that output cells at the time of broadcasting. That is, when outputting to the output highway 2-1, the address value is written to the address memory 8-1.

Each address memory is provided with counters 15-1 to 15-N for counting its capacity. One of the counters is provided in each address memory. When one address value is stored in the corresponding address memory, 1 is added to the counter value, and when one address value is output, the counter value is decreased by one to obtain one counter. The capacity of the address memory is counted.

When the cell is a broadcast cell, when writing an address value in the address memory, the write control unit 6 checks the output of a counter indicating the internal capacity of each address memory for storing the address value, and A flag signal is added to the address value stored in the address memory having a large internal capacity (the flag signal is a logical value of 1 and the flag signal is 0 if it is 0). If two or more components have the largest contents, one of them is selected and a flag signal is added. For example, when reading cells from the buffer memory 4 in ascending order of the output highway number, the flag signal is written to the address memory corresponding to the output highway having the largest output highway number. As an example, output to highways 2-1 and 2-2, and address memory
If the contents of 8-1 and 8-2 are the same and cells are read from the buffer memory 4 in ascending order of the output highway number, an address value and a flag signal are written to the address memory 8-2 (the flag signal 17). -2 is set to the logical value 1), and only the address value (the flag signal 17-1 is set to the logical value 0) is written into the address memory 8-1.

Alternatively, when reading cells from the buffer memory 4 in descending order of the output highway number, the flag signal is written to the address memory corresponding to the output highway having the smallest output highway number. To give an example,
When outputting to the output highways 2-1 and 2-2, and when the contents of the address memories 8-1 and 8-2 are the same, and when reading cells from the buffer memory 4 in descending order of the output highway numbers. Writes the address value and the flag signal to the address memory 8-1 (sets the flag signal 17-1 to the logical value 1),
Only the address value (flag signal 1
7-2 is set to logical value 0).

In the case of a non-broadcast cell, a flag signal is always added to the address value, and the address value is stored in the address memory.

On the output side of the buffer memory 4, cells are read in units of output highways. That is, one address value is sequentially read from the address memory uniquely corresponding to each output highway, the value is given to the buffer memory 4, and the cell is output. Further, when a flag signal appears at the same time when the address value is read, the address value is stored in the free address management memory 9. When the flag signal does not appear, an operation of only outputting the cell from the buffer memory 4 is performed, and the address value is not stored in the empty address management memory.

In the above embodiment, the address memory may be constituted by a FIFO memory.

In the above embodiment, one counter is provided in each address memory. When one address value is stored in the corresponding address memory, 1 is added to the counter value, and when one address value is output, the counter value is output. By reducing by one, the capacity of each address memory was counted.
In addition to this method, the amount of the address value contained in each address memory can be measured by the following method. First, the capacities of all address memories are made equal. The value of the counter indicates the capacity of the buffer memory (that is, the maximum value) when there are no cells in the buffer memory, and indicates the value of 0 (that is, the minimum value) when the buffer memory is full of cells. Further, when each counter stores one address value in the corresponding address memory, the counter value is reduced by one, and when one address value is output, the counter value is increased by one. That is, by measuring the capacity of the unused area, it is possible to identify the address memory that stores the most address values.

As described above, in the above embodiment, the vacant address stored in the vacant address management memory first uses the output value of the counter 20, and thereafter, the vacant address management memory uses the output value of the broadcast output. To know the end, the longest queue in the address memory is instructed by the write control unit, and a flag is added to the address to be recorded in the longest address memory.

[0041]

According to the present invention, it is possible to realize an ATM switch having a broadcast function in an ATM switch.

[Brief description of the drawings]

FIG. 1 is a switch configuration diagram showing the principle of the present invention.

FIG. 2 is a diagram showing a configuration of a cell.

FIG. 3 is a switch configuration diagram showing an embodiment of the present invention.

FIG. 4 is a processing flow in a writing control unit.

[Explanation of symbols]

1-1 ・ 1-2 ・ ・ ・ 1-N ・ ・ ・ Input highway 、 2-1 ・ 2-2 ・ ・ ・ 2
-N: output highway, 3: multiplexing unit, 4: buffer memory, 5: demultiplexing unit, 6: write control unit, 7: read control unit, 8-1 / 8-2 ... 8-N: address memory , 9 ... free address management memory, 10 ... routing header signal, 11-1 ・ 11
-2 ··· 11-N ··· Write permission signal and count-up command, 12-1 · 12-2 ··· 12-N ··· Read permission signal and countdown command, 13 ··· Write address value given to buffer memory 4, 14 ... Read address value given to buffer memory 4, 15-1 ・ 15-2 ・ ・ ・ 15-N… Counter, 16
-1 ・ 16-2 ・ ・ ・ 16-N ・ ・ ・ Counter output, 17-1 ・ 17-2 ・ ・ ・
17-N: Flag signal, 18: Empty address management memory read instruction signal, 19: Empty address management memory write instruction signal, 20: Counter, 21: Selector, 22: Operation start instruction, 23: Selector control signal, 31: Routing Information, 32 ...
VPI (Virtual Path Identifier), 33… VCI (Virtual Chan)
nel Identifier), 34 ... control information, 35 ... HEC (Header Erro)
r Control), 36 ... User information area.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yukio Nakano 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Takashi Nakajima 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone (56) References JP-A-4-175034 (JP, A) JP-A-3-231539 (JP, A) JP-A-4-35336 (JP, A) (58) Fields surveyed (Int .Cl. ⁷ , DB name) H04L 12/28 H04L 12/56 H04L 12/18 H04Q 3/52

Claims (7)

(57) [Claims] An ATM connected to a plurality of input highways and output highways for switching fixed length cells arriving via the input highway to an output highway.
In (Asynchronous Transfer Mode) switch circuit, and a buffer memory for storing the arrived cell was provided in a plurality corresponding to each output highway, and an address memory for storing and outputting a cell storage address value of the buffer memory in the order of arrival a write control unit for controlling the writing of the buffer memory by analyzing the output highway arriving cell is outputted, the reading of the buffer memory control
A read control unit for control and idle address managing means for managing a free address of the buffer memory, the output Haiu
Manages the capacity of each address memory provided for each way
Has an address memory management means for, wherein the write control unit, the analyzes routing information included in the arriving cell
Identify the output highway from which the cell will be output and
Corresponds to the specified output highway in the dress management means
Value of free address for address memory to be used
Is output, and the corresponding address value is stored in the corresponding address memory.
And store the relevant address in the buffer memory.
The cell is written to the address value, and it is determined whether or not the arriving cell is a broadcast.
Refer to the capacity of each address memory managed by the
Address memory with the slowest cell address output
Detects, it notifies the idle address managing means, the read control unit can direct the output of the address value to said address memory
And reads out the cell from the address value of the buffer memory, is outputted to the output highway corresponding to the address memory, said idle address managing means, when there is an instruction from the write control unit, the writing
For the output highway of the cell analyzed by the control unit,
The address value of the empty address in the corresponding address memory
Whether the address becomes an empty address when reading
Output with the information of whether the
Address output from the address memory according to the instruction of
The address value is monitored, and the address is
If information indicating that it is a free address is attached,
This address value is managed as an empty address.
And when there is an instruction from the writing control unit.
If the arriving cell is broadcast,
The address notified by the
Refers to the memory of
Free space to output for each of the corresponding multiple address memories
The empty address to be added to the address value of the address
An ATM switch circuit having a broadcast function, which determines information as to whether or not the ATM switch is present. 2. A method according to claim 1, wherein the address memory management unit, provided with a plurality to correspond to each of the address memory <br/>, monitors the input and output address value of the corresponding address memory, the A counter for counting the capacity of the address memory, wherein the address memory is a FIFO (First In First Ou)
t) A having a broadcast function characterized by being a memory
TM switch circuit. 3. The method of claim 1, all of the address memory capacity are identical, the address memory management unit, each of the address memory
Corresponding to the provided in plurality, and monitoring the output and storage address value of the corresponding address memory, ATM switch circuit having a multicast function, which is a counter for counting the unused area of the address memory . 4. The arriving cell according to claim 1, 2 or 3 , wherein said empty address management means receives an instruction from said write control unit.
If is not a broadcast, corresponds to the output highway of the cell
To address memory, the address value of the empty address,
Information that the address becomes an empty address when reading
And output it, if it is a broadcast,
Multiple address memories corresponding to the output highway
That is, the address notified from the write control unit.
A free address is added to the address memory with the slowest output.
Address, when reading, the address
Output with the information that the
In addition, when reading, the address becomes an empty address.
An ATM switch circuit having a broadcast function, characterized in that the ATM switch circuit outputs the information with the information of the broadcast. 5. A method according to claim 1, 2 or 3, wherein the idle address managing means, when there is an instruction from the write control unit, when arriving cell is not a broadcast, the address value of the empty address, flag the added output, whereas, if it is broadcast, the cell
Of multiple address memories corresponding to the output highway of
Of these, a flag is added to an address value stored in the address memory having the slowest address output of the cell and a flag is output, and an address value stored in the other address memories is output . is for outputting without adding a flag
The address according to the instruction of the read control unit.
Monitor the address value output from the
Address is flagged, the address value
An ATM switch circuit having a broadcast function, wherein the ATM switch circuit manages an address as an empty address . 6. The arriving cell according to claim 1, 2 or 3 , wherein said empty address management means receives an instruction from said write control unit.
Is not a broadcast, the address value of the vacant address is
Output without adding a lag.
Multiple address memories corresponding to cell output highways
Of the cells whose address output is the slowest
A flag is added to the address value stored in memory
Output without being stored in other address memory
For address values, output with a flag added
, And the addition, the in accordance with an instruction of the read control unit address
Monitor the address value output from the
Address is not flagged, the address
An ATM switch circuit having a broadcast function, wherein a value is managed as an empty address . 7. An ATM connected to a plurality of input highways and output highways for switching fixed-length cells arriving via the input highway to an output highway.
(Asynchronous Transfer Mode) A broadcast output method in a switch circuit , wherein the ATM switch circuit stores a arriving cell.
Buffer memory and output highway
In addition, the cell storage address values of the buffer memory are arranged in the order of arrival.
Address memory for storing and outputting to the
Free address management means for managing free addresses of memory
And address memories provided for each of the output highways.
Address memory management means for managing various capacities, and when writing cells to the buffer memory, analyze routing information contained in the arriving cells, and
The address corresponding to the output highway from which the cell is output.
Specify the address memory and store the
Instruct storage of the storage address value, and
The above address is stored in a free address managed by the dress management means.
If the arriving cell is a broadcast cell,
Each address managed by the address memory management means.
By referring to the capacity of the
The address memory with the slowest address output is detected and
And instructs the address memory to output an address value when reading cells from the buffer memory.
And stored in the address value of the buffer memory.
Read out the cell that corresponds to the address memory
Output to the output highway, and the arriving cell is broadcast
If it is a cell, the address output of the broadcast cell
As a slow address memory to the free address management means
The address of the broadcast cell from the notified address memory
Is output to the vacant address management means.
Broadcast output method characterized in that to manage the address as free addresses.