KR100364420B1 - Dribble bit remove apparatus - Google Patents

Abstract

The present invention relates to a dribble bit removing apparatus. In the related art, a method of using a buffer for removing a dribble bit is complicated, and a large number of buffers are used to remove a dribble bit. there was. Accordingly, the present invention provides a PHY chip, comprising: a demultiplexer for receiving a data packet including a dribble bit at an end thereof, demuxing and outputting the data packet; First and second buffers sequentially storing the data packets output from the demultiplexer in predetermined bit units, and outputting only data of the opposite buffers in parallel when the dribbling bits are stored; It consists of a multiplexer that receives the data output from the first and second buffers in an alternating operation and multi-transmits the data in predetermined bit units, thereby eliminating dribble bits, thereby reducing the complexity of the circuit and reducing power consumption. There is.

Description

DRIBBLE BIT REMOVE APPARATUS}

The present invention relates to a dribble bit removing device, and more particularly, to a dribbling bit removing device which can reduce the area of a circuit by drastically reducing the complexity of a circuit for removing a dribbling bit.

In general, in the 1394 protocol, all packets are sent with a dribble bit in order to operate the data / strobe coding circuit normally. Accordingly, all PHY chips receive the packet, store the result in a buffer, and then transmit the packet. The dribble bits of 1, 3, and 7 bits are removed according to the speed, which will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a conventional dribble bit removing apparatus. As shown in FIG. 1, when the end of the packet data is detected, the dribble bit removing unit 11 removes and outputs a dribble bit. And a deserializer 10 that receives the output signal of the dribble bit removing unit 11 and buffers the output signal to output parallel data. The operation of the conventional apparatus will be described.

First, the dribble bit remover 11 receives the received packet data, and when the end of the packet data is detected, removes and outputs the dribble bit, and the deserializer 10 outputs the output signal of the dribble bit remover 11. It receives the input and buffers it to output parallel data.

More specifically, the dribble bit removing unit 11 stores the packet in a buffer when the packet is received, and then removes the dribble bit through a complicated buffering process when the dribble bit removal unit 11 finds that the packet is completed.

In this case, the deserializer 10 is implemented as a kind of buffer circuit, and performs buffering to convert the high speed serial data into the low speed parallel data from the dribble bit remover 10.

However, such a conventional apparatus has a problem in that a method of using a buffer to remove dribble bits is complicated, and a large number of buffers are used to remove dribble bits, thereby increasing a circuit area and increasing power consumption.

Accordingly, an object of the present invention is to provide a dribble bit removal device capable of reducing the area of a circuit by greatly reducing the complexity of a circuit for removing a dribble bit.

1 is a block diagram showing a configuration of a conventional dribble bit removing apparatus.

Figure 2 is a block diagram showing the configuration of the dribble bit removal apparatus of the present invention.

***** Description of the symbols for the main parts of the drawings *****

100: demultiplexer 200, 300: buffer

400: multiplexer

According to an aspect of the present invention, there is provided a PHY chip, comprising: a demultiplexer that receives a data packet including a dribble bit at an end thereof, demuxes it, and outputs the data packet; First and second buffers sequentially storing the data packets output from the demultiplexer in predetermined bit units, and outputting only data of the opposite buffers in parallel when the dribbling bits are stored; And a multiplexer which receives data output from the first and second buffers in an alternating operation and multi-transmits the data in predetermined bit units.

Hereinafter, operations and effects on the dribble bit removing apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing an embodiment of the apparatus for removing a dribble bit of the present invention, as shown in FIG. First and second buffers 200 and 300 which sequentially store output data of the demultiplexer 100 in predetermined bit units; The multiplexer 400 receives the data stored in the first and second buffers 200 and 300 in an alternating operation and transmits the data multiplexed by a predetermined bit unit and outputs the parallel data according to the present invention. Describe the operation.

First, the demultiplexer 100 receives a received data packet, demuxes it, and outputs data according to the first and second buffers 200 and 300. The demultiplexer 100 outputs the output data of the demultiplexer 100 by a predetermined bit. Store sequentially in units.

Thereafter, the multiplexer 400 receives the data stored in the first and second buffers 200 and 300 in an alternating operation, multi-transmits the data in predetermined bit units and outputs the parallel data accordingly.

For example, the received data bits are stored in bit0 to bit1 in case of S100 packet, bit0 to bit3 in case of S200 packet, and bit0 to bit7 in case of S400 packet.

First, after writing the data bits in the first buffer 200, and then writes the next data bits in the second buffer 300, the received data packet is stored in the second buffer 300 at high speed in bits The parallel data bits of 2, 4, and 8 bits (S100 Packet: 2 bits, S200 Packet: 4 bits, and S400 Packet: 8 bits) stored in the first buffer 200 are transmitted through the multiplexer 400 at the speed of S50.

At the end of the data packet, one bit in the case of S100, three bits in the case of S200, and seven bits in the case of S400 follow the dribbling bits, and the packet is finished after one clock cycle.

In addition, all of the characteristics of the IEE1394 packet has a multiple length of 8, thereby storing 1, 3, 7 bits of dribble bits smaller than 8 in the first buffer 200 or the second buffer 300. 200, 300 it can be seen that the packet is finished before completing the storage.

That is, when the last bit is recorded in the first buffer 200 and the dribble bit is recorded in the second buffer 300, it can be seen that the packet is finished before the storing is finished in the second buffer 300. If only data of one buffer 200 is passed as parallel data, dribbling bits are naturally removed.

As described in detail above, the present invention has the effect of reducing the complexity of the circuit and reducing power consumption by simply removing the dribble bit by using one buffer as the ping-pong buffer structure to remove the dribble bit.

Claims (7)

In the PHY chip, A demultiplexer which receives a data packet including a dribble bit at an end thereof, demuxes it and outputs the data packet; First and second buffers sequentially storing the data packets output from the demultiplexer in predetermined bit units, and outputting only data of the opposite buffers in parallel when the dribbling bits are stored; And a multiplexer configured to receive the data output from the first and second buffers in an alternating operation and to multiplex the data in predetermined bit units. The apparatus of claim 1, wherein the received data packet is one of an S100 (2 bit) packet, an S200 (4 bit) packet, and an S400 (8 bit) packet. 3. The apparatus of claim 2, wherein the S100 (2-bit) packet indicates that the packet is finished after one clock cycle after a 1-bit dribble bit follows the end of the packet. The apparatus of claim 2, wherein the S200 (4-bit) packet indicates that the packet is finished after one clock cycle after a 3-bit dribble bit follows the end of the packet. 3. The apparatus of claim 2, wherein the S400 (8-bit) packet indicates that the packet is finished after one clock cycle after a 7-bit dribble bit follows the end of the packet. delete 7. The dribble bit removing apparatus according to claim 1 or 6, wherein the size of the first and second buffers is set to 8 bits.