JP3492861B2 - Traffic smoothing device in ATM switching system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a traffic smoothing device in a communication network based on an asynchronous transfer mode switching system.

[0002]

2. Description of the Related Art As is well known, an asynchronous transfer mode (ATM:
In an ATM switching apparatus that transmits and switches, for example, data by multiplexing according to Asynchronous Transfer Mode, the data is transferred in the form of fixed length packets called ATM cells or simply cells. Each cell is composed of, for example, an information part of 48 bytes and a header part of 5 bytes. The header portion includes respective identifiers for identifying a virtual path (logical path) or a virtual channel (logical char path) that is a logical line. In the ATM network,
Switching is performed according to these identifiers to switch the transmission path. The ATM switching apparatus multiplexes a plurality of virtual paths or virtual channels on, for example, one physical transmission line to transfer a cell.

Traffic characteristics according to a user's declaration are predetermined for the virtual path or the virtual channel. According to these traffic characteristics, the ATM switching apparatus statistically multiplexes cells on a plurality of transmission lines and transfers them to the transmission line on the output side. In this way, the traffic characteristics that statistically multiplex cells are smoothed (shaping) according to the traffic characteristics permitted by the device in the network or the user device in the subsequent stage connected to the transmission path on the output side. As a result, cell discard caused by multiplexing a large number of cells beyond the band of the transmission path on the output side is prevented.

In the conventional ATM switching apparatus, the smoothing of traffic has been performed as follows. When a cell arrives from the incoming line, it is written in the cell buffer. The write address to the cell buffer is managed in the cell arrival order for each virtual path or virtual channel of the input cell. Cells are read from the cell buffer at a read cycle corresponding to the band used by the virtual path or virtual channel. These readings are also managed for each virtual path or virtual channel.
More specifically, each time a cell is input, its virtual path or virtual channel is written to the address of the read control memory corresponding to the transmittable time. For a virtual path or virtual channel, when the time corresponding to the read cycle has elapsed from the previous transmission time, the virtual path or virtual channel is read from the read control memory, and the cell corresponding to this virtual path or virtual channel is read from the cell buffer. read out. As a result, the cells are statistically multiplexed so as not to exceed the band of the transmission path on the output side and transmitted.

[0005]

As described above, the conventional AT
In the M switching apparatus, cells of a plurality of transmission lines are multiplexed and then the multiplexed cells are input to the apparatus. Therefore, the speed of the cells arriving at the input side of the exchange may be higher than the speed of the cells output from the output side. As mentioned above, in the conventional ATM switching device,
Since the virtual path or virtual channel is written to the read control memory each time a cell is input, when the multiplexed cells on the input side are high speed, the read control memory has no free storage area. A condition can occur. In such a case, a state occurs in which no input cell is written in the cell buffer, and such an input cell is discarded. As described above, there is a problem that the writing speed of the memory cannot follow the transfer rate of the cell, or the limit of the memory capacity is exceeded, and the cells that cannot be written in the memory are discarded.

Further, in such an ATM switching apparatus, when a series of cells of virtual paths or virtual channels set in a high band is input in a burst state, other virtual paths or virtual channels are controlled by a read control memory. In some cases, it was not possible to set the readable time. In such a case, the probability that the outputtable time of the cell will be changed to another free time becomes high,
Therefore, the cell output failure, that is, the cell output fluctuation becomes large. As a result, the accuracy of the traffic characteristics (output traffic accuracy) of the virtual path or virtual channel in which the band is set low decreases. That is, there is a problem that the service of the low band user becomes worse than the service of the high band user, and the user service between the low band and the high band cannot be equalized.

It is an object of the present invention to provide a traffic smoothing device in an ATM switching system which can uniformly provide a user service without causing cell discard due to traffic smoothing.

[0008]

According to the present invention, in order to solve the above-mentioned problems, a traffic smoothing apparatus for smoothing and transferring a used band of a cell transferred in an ATM network over a plurality of logical lines. When a cell is input, the cell temporarily stores it in the first memory means, and the counting means counts the number of the stored input cells in correspondence with the logic line. The output timing generation means responds to the increase / decrease in the count value and calculates the output available time corresponding to the used band of the cell corresponding to the logical line. First according to the output available time
The cell is read from the memory means and transmitted. As a result, cells can be transmitted in a uniform band in accordance with the traffic characteristics permitted by the device on the other end that is transmitted on any logical line.

According to the present invention, an input cell connected to a communication network by an asynchronous transfer mode switching system and arriving at the input side in relation to a logical line is output from the output side in a band according to its traffic characteristic, The traffic smoothing apparatus for smoothing the traffic characteristics on the output side by this means is provided with the first memory means for temporarily storing the input cell in association with the logic line and the temporary connection in relation to the logic line in the first memory means. The counting means for counting the number of accumulated cells, the time counting means for counting the time, and the time counting means are connected, and each time the count value in the counting means steps up or down, the output possible time corresponding to the logical line is set. Output timing generating means for calculating, second memory means for storing logical line data indicating a logical line corresponding to the calculated available output time, and a timekeeping means Read-out control means for reading out the logical line data corresponding to the clocking time from the second memory means and reading out the cell from the corresponding memory location of the first memory means, the read-out control means comprising the output timing. By reading the logical line data corresponding to the time measured by the time measuring means from the second memory means based on the output possible time from the generating means, and reading the cell from the corresponding memory location of the first memory means, Cells are uniformly transmitted according to the traffic characteristics allowed on the output side regardless of the logical line.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a traffic smoothing device in an ATM switching system according to the present invention will be described below with reference to the accompanying drawings. Referring to FIG. 1, an embodiment of a traffic smoothing device 10 according to the present invention is generally applied to an ATM transfer device such as an Asynchronous Transfer Mode (ATM) switching device, which routes an incoming ATM cell 102 arriving at an input 100 to its traffic. This is a device that outputs from the output 106 in a band according to the characteristics and smoothes (shaping) the traffic characteristics at the output 106. Cell 102 entered in input 100
Are generally statistically multiplexed in this embodiment. Of course, the present invention is not limited to this,
The input cells do not have to be multiplexed. Further, the output line 106 is connected to a user device (not shown) such as an in-network device in the ATM network or a subscriber terminal device.

The traffic smoothing apparatus 10 as a whole is a shared cell buffer that temporarily stores the input cells 102 from the input line 100 in the order of input and outputs this to the output line 106.
18, a clock unit 16 that measures the time and outputs the current time data 114, an output timing generation unit 12 that responds to the current time data 114 to generate the available output time data described below, and a read unit that manages the read time. And a control memory 14.

The shared cell buffer 18 includes a cell memory 20 functioning as a cell buffer for temporarily storing the input cell 102, a write controller 22 for controlling writing in the cell memory 20,
An address management memory 24 that stores and manages write addresses and read addresses of the cell memory 20, a read control unit 26 that controls reading of the cell memory 20, and the cell memory 20.
An in-buffer cell number counter 28 for counting the number of cells 102 stored in the memory is connected as shown in the figure.

When a statistically multiplexed cell (input ATM cell) 102 arrives from the input line 100, the cell 102 is input to the cell memory 20 in the shared cell buffer 18. The ATM cell 102 is a fixed-length packet of 53 bytes in this embodiment, and is composed of, for example, a header section 202 of 5 bytes and an information section 204 of 48 bytes as illustrated in FIG.
The header part 202 contains a predetermined virtual path VP.
Virtual path identifier VPI (Virtual Path Identifier) for identifying (Virtual Path: Logical Path) and / or virtual channel identifier VCI (Virtual Channel Identifier) for identifying virtual channel VC (Virtual Channel: Logical Channel) It is included.
The virtual path identifier VPI and / or the virtual channel identifier VCI included in the input cell 102 are also input to the write controller 22 and the in-buffer cell number counter 28.

When the identifier VPI or VCI is input, the write control unit 22 identifies this, and through the connection line 108,
Virtual path VP corresponding to its identifier VPI or VCI
Alternatively, the virtual channel VC is written to the address management memory 24, and the cell memory from the address management memory 24 is also written.
Cell 10 in cell memory 20 based on 20 addresses
A memory control unit that controls the writing of the cell memory 20 by giving a write address designating a storage area for writing 2 to the cell memory 20. When the write control unit 22 receives the write address 108 from the address management memory 24, the write control unit 22 also gives a notification 112 to that effect to the in-buffer cell number counter 28. As will be described later, the counter 28 responds to this by incrementing the number of cells of the corresponding virtual path VP or virtual channel VC by one.

The address management memory 24 has a storage area corresponding to, for example, a virtual path VP or a virtual channel VC, that is, a logical line, and an address in the cell memory indicating a storage location of the virtual path VP or the virtual channel VC in the cell memory 20. Is a storage device in which is stored. The writing of the address of the cell memory 20 from the writing control unit 22 to the address management memory 24 is performed by the cells corresponding to each virtual path VP or virtual channel VC.
The steps 102 are performed in the same order as they are stored in the cell memory 20. These addresses are read out to each via the connection line 108 or 118 under the control of the write control unit 22 or the read control unit 26.

Cell memory 20 stores input cell 102 in a storage location designated by write address 104 provided from write control section 22 and is designated by read address 114 output from read control section 26. It is a temporary storage device that reads out the storage cell from the storage location and outputs it to the output line 106 as an output ATM cell. The cell memory 20 may be composed of, for example, a hierarchical memory that stores cells for each hierarchy corresponding to each virtual path VP or virtual channel VC.

The in-buffer cell number counter 28 has a storage area corresponding to the virtual path VP or virtual channel VC, and counts the number of cells 102 stored in the cell memory 20 for each virtual path VP or virtual channel VC. It is a counter function unit that does. The count value for each virtual path VP or virtual channel VC in the counter 28 is the increment notification 112 from the write control unit 22 or the decrement notification 120 from the read control unit 26 described later.
Is incremented or decremented in response to. When the number of cells in the virtual path VP or virtual channel VC advances from “0” to “1” or when the number of cells in the buffer decreases to a value other than “0”, the number of cells in the buffer 28 Data showing the virtual path VP or virtual channel VC that has changed 1
24 is output to the output timing generation unit 12.

By the way, the present apparatus 10 has a clock section 16 for measuring the current time and outputting current time data 114 representing the time. The clock unit 16 inputs the current time data 114 into the output timing generation unit 12 and the read control memory 14 each time the current time value is incremented.

The output timing generation unit 12 includes an output timing determination unit 12a that determines the time when the cell 102 of a certain virtual path VP or virtual channel VC is permitted to be output from the output line 106, that is, the output available time. There is. In the output timing discriminating unit 12a, a traffic characteristic previously declared by the user, for example, a read cycle (time) from the cell memory 20 according to a used band is set in correspondence with the virtual path VP or the virtual channel VC. The output timing determination unit 12a identifies the data 124 indicating the virtual path VP or the virtual channel VC output from the in-buffer cell number counter 28, and the output possible time data 1 indicating the corresponding output available time 1
26 is calculated, and the virtual path VP or virtual channel VC is output to the read control memory 14 from the connection line 128 and the output available time data from the connection line 126. This output available time is equal to, for example, the last read time, that is, the value obtained by adding the above-mentioned read cycle to the previous output possible time output to the read control memory 14. This is output to the read control memory 14 as the next available output time data 126.
In summary, the output timing determination unit 12a identifies the virtual path VP or virtual channel VC received from the in-buffer cell number counter 28, that is, the number of cells has changed, and corresponds to the identified virtual path VP or virtual channel VC. The output possible time is determined and the data 128 and 126 are output to the read control memory 14.

The read control memory 14 has a storage area having an address corresponding to the time, and the output timing discriminating unit 12
The storage device stores the virtual path VP or virtual channel VC also received from the output timing determination unit 12a at the address corresponding to the output available time data 126 received from a. When data has already been written in the storage area of the address to be written, the free address closest to that time is found and the virtual path VP or virtual channel VC is stored there. The read control memory 14 also receives the current time data 114 when the current time is incremented by the clock unit 16, and the data, that is, the virtual path VP or the virtual channel VC, is stored in the storage location of the address corresponding to this time data 114. If so, read it at output 116.

In the read control memory 14, the band that can be set as the traffic smoothing device 10 is determined by the time, that is, the number of addresses accommodated as a memory as described above. For example, assuming that the maximum band of the output line 106 is a and the number of storage location addresses in the read control memory 14, that is, the storage capacity is b (natural number), the band of axn / b (n is a natural number from 1 to b) is set. can do. It is advantageous to secure in the read control memory 14 a memory area in which all low-bandwidth cells can be written even when they are input in bursts. This enables output time data of the cell without causing the cell to be discarded.
126 can be managed smoothly.

The read control unit 26 of the shared cell buffer 18 is
It is a control unit for giving the address 122 corresponding to the virtual path VP or the virtual channel VC read from the read control memory 14 to the cell memory 20 to read the cell 102 from the cell memory 20.
More specifically, as described above, when the virtual path VP or the virtual channel VC is read from the read control memory 14 in response to the current time data 114 from the clock unit 16, the read control unit 26 is based on this. The address 118 of the corresponding cell memory 20 is read from the address management memory 24, is given to the cell memory 20 from the address line 122, and the cell 102 is controlled to be read out to the output 106 from the storage position corresponding to this address. At the same time, the read control unit 26
A notification 120 indicating that such read control has been performed is output to the in-buffer cell number counter 28.

In operation, when the statistically multiplexed input cell 102 arrives on the input line 100, the cell 102 is input to the cell memory 20 and contains the virtual path identifier VPI or virtual channel identifier VCI contained therein.
Is also input to the write control unit 22 and the in-buffer cell number counter 28. The write control unit 22 generates a write address of the cell memory 20 and supplies the write address to the cell memory 20, whereby the input cell 102 is written in the cell memory 20 at a storage position corresponding to the address. Along with this, the write controller
22 also identifies the identifier VPI or VCI and their corresponding virtual path VP or virtual channel VC.
Is sent to the address management memory 24. Address management memory 24
Stores the received write address of the cell memory 20 in the storage area corresponding to the virtual path VP or virtual channel VC in the same order as the storage order of the cell 102 in the cell memory 20. When this write control is performed, the write control unit 22 outputs a notification 112 indicating this to the in-buffer cell number counter 28.

In response to the notification 112, the in-buffer cell number counter 28 increments the cell count value of the corresponding virtual path VP or virtual channel VC by one.
When the number of cells in the virtual path VP or virtual channel VC advances from “0” to “1” at this time, the in-buffer cell number counter 28 changes the virtual path VP or virtual channel in which the number of cells has changed.
The data 124 indicating VC is output to the output timing unit 12.

On the other hand, the clock unit 16 outputs the current time data 114 to the output timing generation unit 12 and the read control memory 14 every time the value of the current time is incremented. The output timing generation unit 12 identifies the data 124 indicating the virtual path VP or the virtual channel VC output from the in-buffer cell number counter 28, and calculates the output available time data 126 indicating the corresponding output available time. This output possible time data is output to the read control memory 14 from the connection lines 126 and 126 together with the virtual path VP or the virtual channel VC.

The read control memory 14 stores the received virtual path VP or virtual channel VC at the address corresponding to the output available time data 126 received from the output timing discrimination section 12a. When data has already been written in the storage area of the address to be written, the free address closest to that time is searched and the virtual path VP or virtual channel VC is stored there.

When the clock unit 16 increments the current time, the current time data 114 is input to the read control memory 14. Therefore, the read control memory 14 stores the time data 1
Only if the data, that is, the virtual path VP or the virtual channel VC, has been written in the storage location of the address corresponding to 14, this is read out to the output 116.

The read control unit 26 uses the virtual path VP or the virtual channel VC from the read control memory 14 to read from the address management memory 24 and the corresponding cell memory.
Read address 118 of 20. This address 118 is input to the cell memory 20 through the address line 122 and
The 20 reads the cell 102 at the output 106 from the storage location corresponding to this address. The read output ATM cell is sent from the output line 106 to a user device (not shown) such as an in-network device in the ATM network or a subscriber terminal device.

In this way, the cells 102 written in the cell memory 20 are read out at the time corresponding to the user's declared band associated with the virtual path VP or the virtual channel VC in the order of input, and the cells 102 are read from the output line 106 in the network. Sent to the device. Therefore, the traffic smoothing apparatus 10 of the present embodiment transfers the statistically multiplexed cell 102 to the output 106 according to the traffic characteristic determined according to the user's declaration on the virtual path or virtual channel. In this way, the statistical multiplex cells are output in a use band that matches the traffic characteristics permitted by the device in the network or the user device at the subsequent stage connected to the output 106, and the traffic characteristics are smoothed. This prevents the discarding of cells caused by the multiplexing of a large number of cells beyond the band of the device in the subsequent stage of the output 106.

At the same time when the read control unit 26 performs the read control as described above, the read control unit 26 outputs a notification 120 to the effect that the read control has been performed to the in-buffer cell number counter 28. In response to the decrement notification 120, the in-buffer cell number counter 28 decrements the cell count value of the corresponding virtual path VP or virtual channel VC by one. The number of cells in the buffer counter 28 also indicates that the virtual path VP or the virtual channel is decremented.
When the cell count value in VC gradually decreases to a value other than “0”, the data 124 indicating the virtual path VP or virtual channel VC in which the number of cells has changed is output to the output timing unit 12.

As described above, in this embodiment, the virtual path
The number of cells 102 stored in the cell memory 20 for each VP or virtual channel VC is grasped by the in-buffer cell number counter 28. At the same time the write control unit 26 controls writing of the input cell 102 into the cell memory 20, the in-buffer cell number counter 28 increments the cell count value of the corresponding virtual path VP or virtual channel VC by one. In addition, the read control unit 26 stores cells from the cell memory 20.
At the same time as controlling the reading of 102, the in-buffer cell number counter 28 decrements the cell count value of the corresponding virtual path VP or virtual channel VC by one.

In the present embodiment, when the in-buffer cell number counter 28 receives the increment notification 112 and the decrement notification 120 at the same time, this embodiment gives priority to the increment and the data 124 of the virtual path VP or virtual channel VC related to the increment. Is sent to the output timing generation unit 12. As a result, the output timing determination unit 12a need only make one determination at all times. Also, since there is at least one free space in the output control memory 14, the output available time can be written without fail.

In this embodiment, each time the current time data 114 of the clock section 16 is incremented, the read control memory 14 is also read.
Receives the current time data 114 from the clock unit 16 and operates the read control unit 26 to store the current time data 114 in the cell memory 20 when the virtual path VP or the virtual channel VC is written in the storage location having this address. The read cell. If data is already written in the storage location of that address, it is possible to find an empty address near the time and write the data there.

Further, according to the present embodiment, since only one virtual path VP or virtual channel VC is written to the read control memory 14, the input line 100
Even if the cell 102 input from exceeds the maximum bandwidth of the output line 106, or when the read control memory 14 is full,
As long as there is sufficient cell buffer area in cell memory 20, cells 102 will be stored therein. Therefore, the transmission can be performed while setting the transmission timing for each cell. This prevents the cell from being discarded. In addition, even if the virtual path VP or virtual channel VC set in the high band is input in bursts, the probability that the output available time cannot be set and the output will turn to a vacant space is
Since it is possible to make uniform for any virtual path VP or virtual channel VC, output traffic accuracy with uniform fluctuation is obtained regardless of the set bandwidth. Therefore, it is possible to provide services that are not biased even to users who use different bandwidths.

Further, the read control memory 14 can have time data (address data) as many as the resolution of the minimum band. That way, regardless of the bandwidth of the virtual path VP or virtual channel VC used,
By using a memory having a capacity suitable for the multiplexed traffic characteristics of the input line 100 for the cell memory 20 with the same hardware configuration, the traffic smoothing device 10 can be realized as a general-purpose integrated circuit. Of course, the traffic on input line 100 need not be multiplexed.

The above-described embodiment is an example of the traffic smoothing device in the ATM network that handles a plurality of virtual paths VP or virtual channels VC. However, the present invention
The present invention is not limited to this, and can be applied to, for example, a band control device that changes the used band from any user device when the user device transmits data into the ATM network.

Further, the state of the address management memory 24 is monitored, and when the vacancy becomes small to some extent, it is detected that the device (not shown) in the preceding stage of the input line 100 is interrupted in the transmission of cells. You may add the structure which outputs the request | requirement instruction | indication. By doing so, it is possible to prevent the cell from being lost or discarded at all.

[0038]

As described above, according to the present invention, only one read control memory is read for one virtual path VP or virtual channel VC. Therefore, if the traffic from the input line exceeds the maximum bandwidth of the output line, even if the read control memory is full, as long as there is sufficient cell buffer in the cell memory, the cells are accumulated in it and are stored cell by cell. It is possible to transmit while setting the transmission timing to. Therefore, there is no cell loss due to traffic smoothing, and which virtual path
Even for VP or virtual channel VC, uniform fluctuation output traffic accuracy can be obtained regardless of the band. Therefore, it is possible to provide a service that is not biased to the user.

The read control memory may be provided with as many time storage areas as the resolution of the minimum bandwidth. Thus, regardless of the band of the virtual path VP or virtual channel VC to be used, a traffic smoothing device can be realized if there is a cell memory having a capacity that matches the traffic characteristics, and thus can be used for general purposes.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an embodiment of a traffic smoothing device according to the present invention.

FIG. 2 is a diagram showing a configuration example of an ATM cell applied to the smoothing device shown in FIG.

[Explanation of symbols]

10 Traffic smoothing device 12 Output timing generator 14 Read control memory 16 Clock section 18 Shared cell buffer 20 cell memory 22 Write controller 24 address management memory 26 Read controller 100 input lines 102 cells 104 Write address 112 increment notification 120 Decrement notification 122 Read address 126 Outputtable time data

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasushi Endo 1-7-12 Toranomon, Minato-ku, Tokyo Inside Oki Electric Industry Co., Ltd. (72) Inventor Shigehiko Ushijima 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo No. Japan Nippon Telegraph and Telephone Corporation (72) Inventor Katsura Noritake 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Japan Nippon Telegraph and Telephone Corporation (56) Reference JP-A-6-276209 (JP, A) ) JP-A 8-125668 (JP, A) JP-A 5-14388 (JP, A) JP-A 5-219114 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 12/28 H04Q 3/00

Claims (4)

(57) [Claims] 1. An input cell connected to an asynchronous transfer mode switching communication network and arriving at the input side in relation to a logical line is output from the output side in a band according to its traffic characteristics, and thereby the output side. In the traffic smoothing device that smoothes the traffic characteristics in
The apparatus comprises first memory means for temporarily storing an input cell in relation to its logic line, and counting means for counting the number of cells temporarily stored in relation to the logic line in the first memory means, Time measuring means for measuring time, output timing generating means connected to the time measuring means, and calculating output possible time corresponding to the logical line each time the count value in the counting means steps up or down, The second memory means for storing the logical line data indicating the logical line corresponding to the output possible time, and the logical line data corresponding to the time measured by the time measuring means are read out from the second memory means and stored therein. Read control means for reading a cell from the corresponding memory location of the first memory means, wherein the read control means is based on the output possible time from the output timing generation means. The logical line data corresponding to the time measured by the time measuring unit is read from the second memory unit, and the cell is read from the corresponding memory location of the first memory unit, so that the output side of the output side is independent of the logical line. A traffic smoothing device characterized in that cells are transmitted uniformly according to allowable traffic characteristics. 2. The smoothing device according to claim 1, wherein
The traffic smoothing device, wherein the logical line is a virtual path or a virtual channel. 3. The smoothing device according to claim 1, wherein
The logical line is identified by an identifier included in the header of the ATM cell, the output timing generation means outputs an available output time based on the identifier, and the read control means is provided in the second memory means. Traffic characterized by writing logical line data to a storage location of an address corresponding to the output available time, and when data has already been written to the address, writing the logical line data to an address close to the output available time Smoothing device. 4. The smoothing device according to claim 1, wherein
The traffic smoothing device is characterized in that the device includes input instruction means for outputting an instruction requesting the input side not to input the input cell.