KR100192524B1 - Control circuit for sense amplifier - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit of a sense amplifier, and more particularly to a control circuit of a sense amplifier adapted to be suitable for high frequency access.

The control circuit of the sense amplifier according to the present invention includes a coding unit for receiving a signal of a clock and an address multiplexer and coding, a Y signal selecting unit for receiving an output signal from the coding unit and selecting a Y signal, and the coding unit. An enable generator that receives an output signal coded by and generates a sense amplifier enable signal, and a sense amplifier that senses a data signal having a small voltage difference by receiving the enable signal of the enable generator and sufficiently amplifies it to be suitable for digital logic And a chip selector configured to receive a signal of the sense amplifier and the Y signal and select a memory cell storing corresponding data.

Description

Sense Amp Control Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit of a sense amplifier, and more particularly, to a control circuit of a sense amplifier adapted to high frequency access.

In general, a semiconductor memory device has a structure that largely stores information (memory cells), a selection portion (decoder, etc.) for selectively storing or reading information at a designated place, and detects a signal state of input / output information. Part (sense amplifier) and information passing part (data bus), which has recently occupied a small area and has a large amount of information storage function, while improving reliability of operation and reducing unnecessary leakage current of the memory cell. Problem is becoming a concern of development.

In particular, the information sensing part, that is, the sense amplifier has a function of sufficiently amplifying the information read in the selected memory cell with the voltage difference and sending it to the data output buffer.

Hereinafter, a control circuit of a sense amplifier of the prior art will be described with reference to the accompanying drawings.

1 is a block diagram showing a control circuit of a sense amplifier of the prior art.

The control circuit of the prior art sense amplifier receives the read enable signals RD1, RD2, RD3 and the clock signals CLK1, CLk2, CLK3, as shown in FIG. And gates 11 to be combined, a first inverter 12 for inverting the signals of the AND gates 11, and a signal delayed for a predetermined time by receiving the inverted signal from the first inverter 12. A delay unit 13, a second inverter 14 that inverts the delayed signal to the delay unit 13 to output an enable signal, and an signal enabled by the second inverter 14. A sense amplifier 15 that receives signals of SAEAN1, SAEAN2, and SAEAN3, and sufficiently amplifies them to be suitable for digital logic, a memory cell 16 for storing data, and amplified signals from the sense amplifier 15; Call selected by the Y signal selector (not shown) via the data line A chip selector 17 for receiving the enabled signals Ysel1, Ysel2, and Ysel3, which are coding (Columm Coding), as an input, and selecting a memory cell 16 storing corresponding data; The memory cell 16 selected in 17) outputs word line signals W / L1, W / L2, and W / L3 through a bit line.

The control circuit operation of the sense amplifier of the prior art uses the CLK1, CLK2, and CLK3 signals, which are generated by an internal clock generator, by receiving an externally generated core clock signal (Cord CLK), as shown in FIG. After synthesizing RD1, RD2, and RD3, which are lead enable signals, STENA1, STENA2, and SEENA3, which are sense amplifier enable signals, are sequentially generated. In this case, if the word lines W / L1, W / L2, and W / L3, which are low coding, and Ysel1, Ysel2, and Ysel3, which are Column coding, are enabled, a bit line memory cell is used. The data in 16 is loaded on the bit line.

As a result, the potential difference of the bit line is further increased by the enabled sense amplifier enable signal.

However, the control circuit of the sense amplifier of the prior art as described above has the following problems.

That is, as shown in FIG. 2, the word line signal, the colon coded signal, and the sense amplifier enable signal are simultaneously enabled, so that a potential difference between the bit lines is caused by the sense amplifier to the ground (GND) and power supply (Vdd) voltages. Therefore, the equalization time takes as much as A, and therefore, high access operation is difficult because a large amount of equalization time is required for continuous access.

The present invention has been made to solve the above problems, and an object thereof is to provide a control circuit of a sense amplifier suitable for high frequency operation.

1 is a block diagram showing a control circuit of a sense amplifier of the prior art.

2 is an operation timing diagram showing the operation of the control circuit of the sense amplifier of the prior art.

3 is a block diagram showing a control circuit of a sense amplifier according to the present invention.

4 is a detailed view showing the multiplexer, Y signal selector, and sense amplifier driver of FIG.

5 is an operation timing diagram showing the operation of the control circuit of the sense amplifier of the present invention.

* Explanation of symbols for main parts of the drawings

21 coding unit 22 Y signal selection unit

23: enable generator 24: sense amplifier

25 chip selector 26 memory cell

27a, 27b, 27c, 27d, 27e, 27f, 27g, 27h: Inverter

28a, 28b: And Gate 29a, 29b: Or Gate

30: delay unit

The control circuit of the sense amplifier according to the present invention for achieving the above object is a coding unit for receiving the signal of the clock and the address multiplexer and coding, and Y for receiving the output signal coded by the coding unit as input Y A digital signal is detected by a signal selector, an enable generator that receives an output signal coded by the coding unit and generates a sense amplifier enable signal, and detects a data signal having a small voltage difference by receiving an enable signal of the enable generator. And a chip selector configured to select a memory cell that receives a signal of the sense amplifier and the Y signal and stores corresponding data.

Hereinafter, the control circuit of the sense amplifier according to the present invention with reference to the accompanying drawings in detail as follows.

3 is a block diagram showing a control circuit of the sense amplifier according to the present invention.

In the control circuit of the sense amplifier according to the present invention, as shown in FIG. 3, the sense amplifier driver 20 receives a signal from a clock and a multiplexer, and codes a coding unit 21 for coding. A Y signal selector 22 which receives an output signal coded by the input unit 21 and selects a Y signal, and generates a sense amplifier enable signal by receiving the output signal coded by the coding unit 21. A sense amplifier 24 which receives the enable signal of the enable generator 23 and the enable signal from the enable generator 23, senses a data signal having a small voltage difference, and sufficiently amplifies the signal to be suitable for digital logic; And a chip selector 25 which receives the signal of the amplifier 24 and the Y signal and selects a memory cell 26 storing corresponding data.

4 is a detailed diagram illustrating a coding unit, a Y signal selection unit, and an enable generation unit of FIG. 3.

As shown in FIG. 4, first, the coding unit 21 receives an externally generated core clock signal Core CLK and receives a PHI1 signal from among PHI1, PHI2, and PHI3, which are signals generated by an internal clock generator. A first end gate 28a (node 1) which is delayed through the first and second inverters 27a and 27b, receives and codes the delayed signal and the signal A through the address multiplexer, and the first end A first-or-gate (NOR) 29a (node 2) for receiving and combining the signal coded at the gate 28a and the next clock signal PHI2 by being inverted through the third inverter 27c and the second signal; And a fourth inverter 27d (node 3) which inverts the signal of the one-or gate 29a.

Subsequently, the Y signal selector 22 includes a second OR gate 29b that combines a signal inverted by the fourth inverter 27d and a signal in which the address multiplexer signal is inverted through the fifth inverter 27e. And a sixth inverter 27f that selects the Y signal by inverting the signal of the second or gate 29b (node 4).

The enable generator 23 receives the inverted output signal of the fourth inverter 27d and includes a delay unit 30 (node 5) including a plurality of inverters for generating an enable signal, and the delay unit. A second end gate 28b (node 6) for receiving and combining the signal delayed at 30 and the output signal of the fourth inverter 27d, and the seventh and eighth inverters for driving the respective output signals ( 27g, 27h).

Referring to the operation of the control circuit of the sense amplifier made as described above is as follows.

As shown in FIG. 5, PHI1 and the address multiplexer A signal are received from the internal clock signals outputted through the oscillator and coded at the first end gate 28a (node 1) to generate a reversed PHI1 signal. Done.

Subsequently, the delayed opposite PHI1 signal and the PHI2 signal, which is inverted by the third inverter 27c, are received and coded at the first or gate 29a. (Node 2) In addition, the first or gate is coded. The signal coded at 29a receives a signal inverted by the fourth inverter 27d (node 3) and a signal inverted by the fifth inverter 27e at the second or gate 29c. Code (node 4)

Subsequently, the signal coded by the second OR gate 29c is output as an inverted signal through the sixth inverter 27f and used as a Y selection signal. The output signal inverted by the fourth inverter 27d is delayed by the delay unit 30 of the enable generator 23 for a predetermined time (node 5).

Subsequently, the signal delayed by the delay unit 30 and the signal inverted by the fourth inverter 27d are received as an input and coded by the second end gate 28b. (Node 6)

Subsequently, the coded signal from the second and gate 28b is driven by the seventh and eighth inverters 27g and 27h to output an enable signal of the sense amplifier.

Accordingly, the Y selection signal is enabled only in its own pulse region PHI1, and the sense amplifier enable signal is enabled in a pulse form in the next clock region after the Y selection signal is disabled.

Here, even when the Y selection signal is in a disabled state, the potential difference is maintained by the capacitance of the data line, so that the data line potential difference becomes a power supply voltage Vdd and a ground voltage GND value by the sense amplifier.

As a result, the bit line potential difference does not go to the power supply voltage and the ground voltage, so that the same continuous read is possible.

As described above, in the sense amplifier control circuit according to the present invention, since the bit line potential difference does not correspond to the power supply voltage and the ground voltage value, the same continuous read is possible, and thus, it is effective to use at high frequency.

Claims (4)

A coding unit which receives and codes a signal of a clock and an address multiplexer, a Y signal selecting unit which receives an output signal coded by the coding unit as an input, and selects a Y signal, and receives an output signal coded by the coding unit as a sense amplifier An enable generator that generates an enable signal, a sense amplifier that receives the enable signal of the enable generator and senses a data signal having a small voltage difference and sufficiently amplifies the signal to be suitable for digital logic; the signal of the sense amplifier and the Y And a chip selector configured to receive a signal and select a memory cell storing corresponding data. The inverter of claim 1, wherein the coding unit receives and codes a clock and an address multiplexer signal as an input, an or gate that receives and codes the AND gate and a next clock signal, and a plurality of inverters that invert and output the clock signals. Control circuit of the sense amplifier, characterized in that consisting of. The control circuit of claim 1, wherein the Y signal selector comprises an or gate for selecting a Y signal and an inverter for inverting an output of the or gate to output a Y signal. The method of claim 1, wherein the enable generation unit receives a output of the coding unit, and a delay unit for delaying a predetermined time to generate a pulse, an AND gate for generating an enable signal by calculating a delayed signal in the delay unit, and the signals. A control circuit for a sense amplifier, comprising a plurality of inverters to drive.