KR19980049913A - Sense Amp Control Circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit of a sense amplifier, and more particularly, to a control circuit of a sense amplifier adapted for high frequency access.

The control circuit of the sense amplifier according to the present invention includes a coding unit for receiving and coding signals of a clock and an address multiplexer, a Y signal selecting unit for receiving an output signal coded by the coding unit as an input, and selecting a Y signal; An enable generator that receives an output signal coded by a coding unit and generates a sense amplifier enable signal, and receives an enable signal of the enable generator and detects a data signal having a small voltage difference and sufficiently amplifies it to be suitable for digital logic And a chip selector which selects a sense amplifier, a memory cell which receives the signal of the sense amplifier and the Y signal and stores corresponding data.

Description

Sense Amp Control Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit of a sense amplifier, and more particularly, to a control circuit of a sense amplifier adapted to be suitable for high frequency access.

In general, a semiconductor memory device has a structure that largely stores information (memory cells), a selection portion (decoder, etc.) for selectively storing or reading information at a designated place, and detects a signal state of input / output information. Part (sense amplifier) and information passing part (data bus), which has recently occupied a small area and has a large amount of information storage function, while improving reliability of operation and reducing unnecessary leakage current of the memory cell. Problem is becoming a concern of development.

In particular, the information sensing part, that is, the sense amplifier has a function of sufficiently amplifying the information read in the selected memory cell with the voltage difference and sending it to the data output buffer.

Hereinafter, a control circuit of a sense amplifier of the prior art will be described with reference to the accompanying drawings.

1 is a block diagram showing a control circuit of a sense amplifier of the prior art.

The control circuit of the conventional sense amplifier receives the read enable signals RD1, RD2 and RD3 and the clock signals CLK1, CLK2 and CLK3 as shown in FIG. And Gates (11), the first inverter 12 for inverting the signals of the And gate 11 and the inverted signal from the first inverter 12 to receive a delay for a predetermined time A delay unit 13, a second inverter 14 which inverts the delayed signal to the delay unit 13 again and outputs an enable signal, and a signal enabled by the second inverter 14. A sense amplifier 15 that receives signals from SAEAN1, SAEAN2, and SEAN3 and amplifies them sufficiently to be suitable for digital logic, a memory cell 16 that stores data, and signals and data amplified by the sense amplifier 15. Selected by the Y signal selector (not shown) via a data line A chip selector 17 that receives the enabled signals Ysel1, Ysel2, Ysel3, which are column coding, and selects a memory cell 16 storing corresponding data, and the chip selector The memory cell 16 selected in step 17 outputs the word line signals W / L1, W / L2, and W / L3 through the bit line.

The control circuit operation of the sense amplifier of the prior art uses a CLK1, CLK2, CLK3, which are signals generated by an internal clock generator as an input from an externally generated core clock signal Core CLK, as shown in FIG. After synthesizing RD1, RD2, and RD3, which are lead enable signals, STENA1, STENA2, and SEENA3, which are sense amplifier enable signals, are sequentially generated.

In this case, if the word lines W / L1, W / L2, and W / L3, which are row coding, and Ysel1, Ysel2, and Ysel3, which are column coding, are enabled, The data in 16 is loaded on the bit line.

As a result, the potential difference of the bit line is further increased by the enabled sense amplifier enable signal.

However, the control circuit of the sense amplifier of the prior art as described above has the following problems.

That is, as shown in FIG. 2, the word line signal, the colombian coded signal, and the sense amplifier enable signal are simultaneously enabled, so that a potential difference between the bit lines is caused by the sense amplifier to ground (GND) and power (Vdd) voltages. Therefore, the equalization time is required as much as A, and therefore, the high frequency operation is difficult because a large amount of equalization time is required for continuous access.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a control signal of a sense amplifier suitable for high frequency operation.

1 is a block diagram showing a control circuit of a conventional sense amplifier.

2 is an operation timing diagram showing the operation of the control circuit of the conventional sense amplifier.

3 is a block diagram showing a control circuit of the sense amplifier according to the present invention.

4 is a detailed view illustrating a multiplexer, a Y signal selector, and a sense amplifier driver of FIG. 3;

5 is an operation timing diagram showing the operation of the control circuit of the sense amplifier of the present invention.

* Explanation of symbols for the main parts of the drawings

21 coding unit, 22 Y signal selection unit, 23 enable generation unit, 24 sense amplifier, 25 chip selection unit, 26 memory cell, 27a, 27b, 27c, 27d, 27e, 27f, 27g, 27h : Inverter, 28a, 28b: End gate, 29a, 29b: Or gate, 30: Delay part

The control circuit of the sense amplifier according to the present invention for achieving the above object is a coding unit for receiving the signal of the clock and the address multiplexer and coding, and Y for receiving the output signal coded by the coding unit as input Y A digital signal is detected by a signal selector, an enable generator that receives an output signal coded by the coding unit and generates a sense amplifier enable signal, and detects a data signal having a small voltage difference by receiving an enable signal of the enable generator. And a chip selector configured to select a memory cell that receives a signal of the sense amplifier and the Y signal and stores corresponding data.

Aha, the control circuit of the sense amplifier according to the present invention with reference to the accompanying drawings in detail as follows.

3 is a block diagram illustrating a control signal of a sense amplifier according to the present invention.

In the control circuit of the sense amplifier according to the present invention, as shown in FIG. 3, the sense amplifier driver 20 receives a signal from a clock and a multiplexer and codes the coding unit 21 and the coding unit. A Y signal selector 22 which receives the output signal coded at 21 and selects a Y signal, and generates a sense amplifier enable signal by receiving the output signal coded at the coding unit 21; A sense amplifier 24 that receives the enable signal from the enable generator 23 and the enable generator 23, senses a data signal having a small voltage difference, and sufficiently amplifies the signal to be suitable for digital logic; And a chip selector 25 which receives the signal of 24 and the Y signal and selects a memory cell 26 storing corresponding data.

4 is a detailed diagram illustrating a coding unit, a Y signal selection unit, and an enable generation unit of FIG. 3.

As shown in FIG. 4, first, the coding unit 21 receives an externally generated core clock signal Core CLK as an input, and PHI1 signals among PHI1, PHI2, and PHI3 generated by an internal clock generator are generated. First and second delays through the second inverters 27a and 27b, the first and gate 28a (node 1) for receiving and coding the delayed signal and the signal A through the address multiplexer, and the first and gate A first or gate (NOR) 29a (node 2) for receiving and combining the signal coded at 28a and the next clock signal PHI2 by being inverted through the third inverter 27c and the first signal; 4th inverter 27d (node 3) which inverts the signal of the OR gate 29a.

Subsequently, the Y signal selector 22 includes a second or gate 29b that combines a signal inverted by the fourth inverter 27d and a signal in which the address multiplexer signal is inverted through the fifth inverter 27e. And a sixth inverter 27f that inverts the signal of the second or gate 29b (node 4) and selects the Y signal.

The enable generator 23 receives the inverted output signal of the fourth inverter 27d and includes a delay unit 30 (node 5) composed of a plurality of inverters for generating an enable signal, and the delay unit. A second and gate 28b (node 6) for receiving and combining the signal delayed at 30 and the output signal of the fourth inverter 27d, and the seventh and eighth inverters 27g for driving the respective output signals. , 27h).

Referring to the operation of the control circuit of the sense amplifier made as described above is as follows.

As shown in FIG. 5, the PHI1 and the address multiplexer A signals are received from the internal clock signals output through the oscillator and coded at the first AND gate 28a (node 1) to generate an opposite delayed PHI1 signal. do.

Subsequently, the delayed opposite PHI1 signal and the PHI2 signal, which is inverted by the third inverter 27c and then the clock signal, are coded by the first or gate 29a. (Node 2)

In addition, the signal coded by the first or gate 29a may receive a signal inverted by the fourth inverter 27d (node 3) and a signal in which the address multiplexer signal is inverted by the fifth inverter 27e. Code at 2 OR gates 29c. (Node 4)

Subsequently, the signal coded by the second or gate 29c is output as an inverted signal through the sixth inverter 27f and used as a Y selection signal.

The output signal inverted by the fourth inverter 27d is delayed by the delay unit 30 of the enable generator 23 for a predetermined time. (Node 5)

Subsequently, the signal delayed by the delay unit 30 and the signal inverted by the fourth inverter 27d are received and coded by the second AND gate 28b. (Node 6)

Subsequently, the signal coded by the second and gate 28b is driven by the seventh and eighth inverters 27g and 27h to output an enable signal of the sense amplifier.

Accordingly, the Y selection signal is enabled only in its own pulse region PHI1, and the sense amplifier enable signal is enabled in a pulse form in the next clock region after the Y selection signal is disabled.

Here, even when the Y selection signal is disabled, the potential difference is maintained by the capacitance of the data line, so that the data line potential difference becomes the power supply voltage Vdd and ground voltage GND by the sense amplifier.

As a result, the bit line potential difference does not go to the supply voltage and the ground voltage, so that the same continuous read is possible.

As described above, in the sense amplifier control circuit according to the present invention, since the bit line potential difference does not correspond to the power supply voltage and the ground voltage value, the same continuous read is possible, and thus it is effective to use at high frequency.

Claims (4)

A coding unit which receives and codes a signal of a clock and an address multiplexer, a Y signal selecting unit which receives an output signal coded by the coding unit as an input, and selects a Y signal, and receives an output signal coded by the coding unit as a sense amplifier An enable generator that generates an enable signal, a sense amplifier that receives the enable signal of the enable generator and senses a data signal having a small voltage difference and sufficiently amplifies the signal to be suitable for digital logic; the signal of the sense amplifier and the Y And a chip selector configured to receive a signal and select a memory cell storing corresponding data. The clock circuit of claim 1, wherein the coding unit comprises an AND gate receiving an address multiplexer signal, an OR gate receiving and encoding the AND gate and the next clock signal, and a plurality of inverters inverting and outputting the clock signals. Sense amplifier control circuit. The control circuit of claim 1, wherein the Y signal selector comprises an OR gate for selecting a Y signal, and an inverter for inverting an output of the OR gate and outputting a Y signal. The method of claim 1, wherein the enable generation unit receives the output of the coding unit delayed for a predetermined time to make a pulse, an AND gate for generating an enable signal by calculating the delayed signal in the delay unit, and the signals A control circuit for a sense amplifier, comprising a plurality of inverters to drive.