KR100191461B1 - Data interface device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a data interface device having a compatibility for receiving data of various formats to be serially transmitted in parallel for a DSP for CDP, and transmitting the scribing signal, the L channel transmission signal, and the clock signal to L as input. An effective channel start signal generator for outputting a valid channel start signal and a channel strobe signal to output a channel and an R channel region, a transmitted edge signal, a clock signal (DBCK), a 16 offset selection signal, and a 16 clock selection signal. And a data reception completion signal for generating a first and second byte reception completion signal and a latch clock to indicate completion of data reception by inputting a valid channel start signal and a channel strobe signal output from the valid channel start signal generator. A transmission sequence signal transmitted from the data reception completion signal generator Most Significant Bit / Least Significant Bit (MSB / LSB) discrimination unit for generating the most significant byte discrimination signal for determining whether the data inputted as the first and second byte reception completion signals is the most significant byte or least significant byte, The highest value at each time point of input of the second byte reception completion signal inputted from the data reception completion signal generation unit as the input and the highest byte determination signal output from the MSB / LSB determination unit is completed. A descrambler that receives the input by byte discrimination and calculates the highest descrambling factor and the lowest descrambling factor according to the least significant byte and the latched clock output from the data reception completion signal generator. Receive the data received Serial / parallel conversion which buffers according to the first and second byte reception completion signals output from the completion signal generator, descrambles according to the highest and lowest descrambling patterns output from the descrambler, and outputs the data as 8-bit parallel data. It consists of wealth.

Description

Data interface device

1 is a configuration diagram of a data interface device according to the present invention.

2 is a waveform diagram of an L-channel transmission signal.

3, 4, and 5 are waveform diagrams of the 16 offset selection signal and the 16 clock selection signal.

6A and 6B are transmission sequence signal waveform diagrams.

7 and 8 are signal waveform diagrams of an effective channel generator.

9 is a signal waveform diagram of the other reception completion signal generator.

10 is a signal waveform diagram of a serial / parallel converter.

* Explanation of symbols for main parts of the drawings

1: Effective channel start signal generator 2: Data reception completion signal generator

3: MSB / LSB discrimination unit 4: Descrambler

5: Serial / parallel conversion unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data interface device of a DSP for CDP, and more particularly, to a data interface device having compatibility in which data of various formats to be serially transmitted is received and processed in parallel.

In general, in the process of receiving serial data and processing it in parallel, the format of the data transmitted in serial may be different for each company. Therefore, the compatibility problem of the product may occur because the data cannot be accessed in response to different formats. There is a case.

In other words, the CDP DSPs produced by each company include serial data (DSPADTA), a strobe signal (Lrck) indicating the channel of the data, and a clock signal (DBCK) for data transmission. Depending on the company, the followings output the signals (DSDATA, LRCK, DBCK) in different formats.

First, when the serial data (DSDATA) and the strobe signal (LRCK) is latched to the rising edge (Rising Edge) of the clock (DBCK) and output when latched to the falling edge (Falling Edge),

Second, when the data for the L channel (Left Channel) of the audio data is transmitted in the interval of the logical value 1 of the strobe signal (LRCK) and in the interval of the logical value 0.

Third, when data is transmitted with the start point and the time when the logic value of the strobe signal LRCK is switched,

Fourthly, when there are audio data and 16 clock signals DBCK per channel and when 16 or more clock signals DBCK exist,

Fifth, when data is transmitted starting from the point in time at which the logic value of the scrobe signal LRCK is switched, the data is transmitted with an offset of one clock of the clock signal DBCK and when the data is transmitted without an offset.

Sixth, the transmission order of the data to be transmitted is when the most significant byte (MSB) comes first and the least significant byte (LSB) comes first.

Outputs each signal (DSDATA, LRCK, DBCK) in different formats.

Due to the different transmission formats, various processors that receive CDP output and process data must be able to accept various output formats.

Accordingly, an object of the present invention is to provide a data interface device to enable various types of data interfaces by inputting information on an output format of a CDP.

In order to achieve the above object, the data interface device according to the present invention inputs a scribing signal, an L channel transmission signal, and a clock signal to transmit an effective channel start signal and a channel strobe signal to output an L channel and an R channel region. An effective channel start signal outputting an effective channel start signal outputting from the effective channel start signal outputting section from the effective channel start signal outputting section; A data reception completion signal generator for generating first and second byte reception completion signals and a latch clock to indicate completion of data reception as an input; first and output signals transmitted from the transmission sequence signal and the data reception completion signal generator; Lowest bar indicating whether the data input as the second byte reception completion signal is the most significant byte. A Most Significant Bit / Least Significant Bit (MSB / LSB) discrimination unit for generating a most significant byte discrimination signal for determining whether a signal is detected, and a second byte reception completion signal output from the data reception completion signal generator as When the input of the most significant byte power signal output from the MSB / LSB discrimination unit is input, the most significant byte discrimination signal is received as the input of the most significant byte discrimination signal every time the input of the second byte reception completion signal per channel is completed, and the most significant byte and the least significant bit are received. A descrambler that calculates the highest descrambling factor and the lowest descrambling factor according to the bytes, and the received serial data as a latch clock output from the data reception completion signal generator, from the data reception completion signal generator Latch output Receives a block and buffers the signal according to the first and second byte reception completion signals output from the data reception completion signal generator and descrambles the output according to the highest and lowest descrambling factors output from the descrambler and outputs the data as 8-bit parallel data. It characterized in that it comprises a serial / parallel conversion unit.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a data interface device according to the present invention, and FIGS. 2A and 2B are waveform diagrams of L channel transmission signals, and FIGS. 3, 4, and 5 are 16 offset selection signals. And (a) and (b) are transmission sequence signal waveforms, and FIGS. 7 and 8 are signal waveforms of an effective channel generator, and FIG. FIG. 10 is a signal waveform diagram of a negative / parallel converter.

As shown in FIG. 1, a data interface device according to the present invention includes an effective channel start signal generator 1, a data reception completion signal generator 2, an MSB / LSB discriminator 3, a descrambler 4, and It consists of a serial / parallel conversion part 5.

The effective channel start signal generator 1 may output the region of the L channel and the R channel (Right Channel) by inputting the transmitted scrobe signal LRCK, the L channel transmission signal LCHL, and the clock signal DBCK. The effective channel start signal CHST and the channel strobe signal CHSB are output.

The data reception completion signal generator 2 generates the transmitted edge signal EDGE, the clock signal DBCK, the 16 offset selection signal SEL16-OFFSET, the 16 clock selection signal SEL16-CLOCK, and the effective channel start signal. First and second byte reception completion signals (1st-Byte-End, 2nd-) to indicate completion of data reception by inputting the effective channel start signal CHST and channel strobe signal CHSB outputted from the sub-1. Byte-End) and latch clock (LATCK).

Most Significant Bit / Least Significant Bit (MSB / LSB) discrimination unit (1st-Byte-) is the first and second byte reception completion signal (1st-Byte-) output from the transmission order signal (DIR) to be transmitted and the data reception completion signal generator (2) End, 2nd-Byte-End) is inputted to generate the most significant byte discrimination signal MSBH that determines whether it is the most significant byte MSB or least significant byte LSB.

The descrambler 4 receives the second byte reception completion signal 2nd-Byte-End outputted from the data reception completion signal generator 2 as the input clock signal DBCK and the MSB / LSB determination unit ( 3) When the input of the second byte reception completion signal (2nd-Byte-End) per channel is completed by inputting the most significant byte discrimination signal MSBH outputted from 3), the most significant byte discrimination signal MSBH is received as an input. The highest descrambling factor and the lowest descrambling factor MSBF and LSBF are calculated according to the MSB) byte and the least significant (LSB) byte.

The serial / parallel converter 5 receives the serial data DSDATA to be transmitted to the latch clock LATCK output from the data reception completion signal generator 2 and outputs the data from the data reception completion signal generator 2. Buffering according to the first and second byte reception completion signals (1st-Byte-End, 2nd-Byte-End) and descrambling according to the highest and lowest descrambling factors (MSBF, LSBF) output from the descrambler 4 Outputs 8-bit parallel data.

Here, the effective channel signal CHST is used as an enable signal of the data reception completion signal generator 2 to transmit invalid data, and the first and second byte reception completion signals 1st-Byte-End, 2nd. Byte-End has a latch clock (LATCK) and one clock for stable data transmission.

The operation of the data interface device according to the present invention configured as described above will be described.

First, in the present invention, an information signal that satisfies a necessary condition will be described.

When the edge signal EDGE is '1', the serial data DSDATA transmitted is latched at the rising edge of the clock signal DBCK, and when the edge signal EDGE is '0', the serial data DSDATA is transmitted. Is latched on the fling edge of the clock signal DBCK.

That is, when the serial signal and the strobe signal LRCK are transmitted by latching the rising edge of the clock signal DBCK in the CDP DSP, the edge signal EDGE must be '0', and vice versa. When the serial data and the strobe signal LRCK are transmitted by latching on the falling edge of the signal DBCK, the edge signal EDGE should be '1'.

As shown in FIG. 2A, when the L-channel transmission signal LCHL is '1', the L-channel Lieg Chnnel of the audio data is transmitted in a section where the strobe signal LRCK is a logic value '1'. Since the logical value is '0', the R channel of the audio data is activated.

In addition, as shown in FIG. 2 (b), when the L channel transmission signal LCHL is '0', the L channel of the audio data in the section where the strobe signal LRCK is a logic value '0' Is transmitted, and an R channel of audio data is transmitted in a section having a logic value of '1'.

When the 16 offset selection signal SEL16-OFFSET is the logic value '1' and the 16 clock selection signal SEL16-CLOCK is the logic value '0', as shown in FIG. 3, the logic value of the strobe signal LRCK. Data for each audio channel is transmitted starting from the switching point of, and data is transmitted with an offset of one clock of the clock signal DBCK based on the starting point.

When the 16 offset selection signal SEL16-OFFSET is the logic value '0' and the 16 clock selection signal SEL16-CLOSCK is the logic value '1', as shown in FIG. 4, the logic value of the strobe signal LRCK is Data corresponding to each audio channel is transmitted starting from the time of switching, without offset of one clock, where the number of clock signals DBCK is 16 per channel.

When the 16 offset selection signal SEL16-OFFSET is the logic value '0' and the 16 clock selection signal SEL16-CLOCK is the logic value '0', the logic value of the strobe signal LRCK as shown in FIG. At the time of this transition, the data transfer ends and there is no offset of one clock. Here, the number of clocks per channel is 16 or more.

When the transmission order signal DIR is' 1 ', as shown in FIG. 6A, the most significant byte MSB is transmitted first among the 16 bits of data during data transmission, and the transmission order signal DIR is' In the case of 0 ', as shown in Fig. 6 (b), the least significant byte (LSB) of the 16 bytes of data is transmitted first during data transmission.

The data interface device according to the present invention is performed with the information signals, the serial data DSDATA, the clock signal DBCK, and the strobe signal LRCK described above.

First, the effective channel start signal generator 1 receives the strobe signal LRCK, the L channel transmission signal LCHL, and the clock signal DBCK, and according to the value of the L channel transmission signal LCHL, the L channel transmission signal. When the value of LCHL is '1', the R and L channel regions are repeatedly output from the falling edge of the strobe signal LRCK as shown in FIGS. 7 and 8.

That is, when the value of the L-channel transmission signal LCHL is '1', the value of the channel strobe signal CHSB becomes '0' at the falling edge of the strobe signal LRCK, as shown in FIG. The signal is output, and the value of the channel strobe signal CHSB becomes '1' at the rising edge of the strobe signal LRCK to output the L channel signal.

In addition, when the value of the L-channel transmission signal LCHL is '0', the value of the channel strobe signal CHSB becomes '1' at the rising edge of the strobe signal LRCK, as shown in FIG. The signal is output, and the L-channel signal is output when the value of the channel strobe signal CHSB becomes '0' at the falling edge of the strobe signal LRCK.

On the other hand, when the value of the L-channel transmission signal LCHL is '0', the effective channel start signal CHST is set to '1' at the falling edge of the strobe signal LRCK, as shown in FIG. When the value of the L-channel transmission signal LCHL is '1', the effective channel start signal CHST becomes '1' at the rising edge of the strobe signal LRCK, as shown in FIG.

The operation of the data reception completion signal generator 2 will be described with reference to FIG.

The data reception completion signal generator 2 has a counter which is reset at each switching point of the value of the channel strobe signal CHSB, and the counter is driven by the latch clock LATCK.

The latch clock LATCK is equal to the clock signal DBCK when the value of the edge signal EDGE is '1', and the inverted clock signal DBCK when the value of the edge signal EGE is '0'. same.

In addition, the first and second byte reception completion signals 1st-byte-end and 2nd-Byte-End output from the data reception completion signal generator 2 have a latch clock that is valid channel start signal CHST. After being multiplied by), it is latched and output by the inverted clock.

The data reception completion signal generator 2 uses the combination of the 16 offset selection signal SEL16-FFSET and the 16 clock selection signal SEL16-CLOCK to set 7 (1st-byte-End) and 15 ( 2nd-Byte-End), 8 (1st-byte-End) and 16 (2nd-Byte-End), and 15 (1st-byte-End) and 23 (2nd-Byte-End) for the latch clock (LATCK). The pulse is output in one cycle.

16 Offset Selection Signal (SEL16-OFFSET) Or First Combination of 16 Clock Selection Signal (SEL16-CLOCK) and First and Second Byte Receive Completion Signals (1st-byte-End) Output of the Data Receive Completion Signal Generator 2 , 2nd-Byte-End) is as follows.

When the 16 offset selection signal SEL16-OFFSET is '1' and the 16 clock selection signal SEL16-CLOCK is '0', the first byte reception completion signal 1st-byte-End becomes '8' and the second The byte reception completion signal (2nd-Byte-End) is 16. In addition, when the 16 offset selection signal SEL16-OFFSET is '0' and the 16 clock selection signal SEL16-CLOCK is '1', the first byte reception completion signal 1st-byte-End becomes '7'. The second byte reception completion signal (2nd-Byte-End) is 15. In addition, when the 16 offset selection signal SEL16-OFFSET is '0' and the 16 clock selection signal SETL16-CLOCK is '0', the first byte reception completion signal 1st-byte-End becomes '15'. The second byte reception completion signal (2nd-Byte-End) is 23.

As for the signal of each part of the data reception completion signal generator 2 described above, the edge signal EDGE is '1', the 16 offset selection signal SEL16-OFFSET is '1', and the 16 clock selection signal SEL16-CLOCK. Is 0, it may be represented as a timing diagram as shown in FIG.

16 input by the MSB / LSB determination unit 3 using the first and second byte reception completion signals 1st-byte-End and 2nd-Byte-End generated in FIG. 9 and the transmission order signal DIR. When the most significant byte (MSB) of the bit data is outputted, the logical value '1' is outputted, and when the least significant byte (LSB) is outputted, the most significant byte discrimination signal MSBH is outputted.

The descrambler 4 recalculates the scrambling factor every time the input of the second byte reception completion signal (2nd-Byte-end) per channel is completed, and receives the input of the most significant byte discrimination signal msbh to receive the most significant byte msb. ) And the different descrambling factors are supplied to the serial / parallel conversion unit 5 according to < RTI ID = 0.0 >

Referring to FIG. 10, the operation of the serial / parallel conversion unit 5 will be described below.

The serial / parallel conversion unit 5 receives the input serial data DSDATA as the latch clock LATCK, and when the first 1 byte of the 16 bits of one channel is completed, the first byte reception completion signal (1st-byte- End) and descrambled by the descrambling factor supplied from the descrambler 4 at that time.

That is, since the transmission order signal DIR determines whether the first input byte is the most significant byte (MSB) or least significant byte (LSB) among the data input per channel, the highest descrambling factor (MSBF) is decoded if the most significant byte is used. The scrambler 4 is supplied to the serial / parallel converter 5, and if it is the least significant byte, the lowest descrambling factor LSBF is supplied from the descrambler 4 to the serial / parallel converter 5.

When the next second byte reception completion signal (2nd-Byte-End) is input, data is transferred in parallel to the parallel buffer by the second byte reception completion signal (2nd-Byte-End), and then the descrambler 4 Descrambling by the descrambling factor supplied from the.

That is, it is determined whether the first byte of the data input per channel is the most significant byte (MSB) or the least significant byte (LSB) by the transmission order signal DIR, so if the most significant byte, the highest descrambling factor MSBF is decoded. The scrambler 4 is supplied to the serial / parallel converter 5, and if it is the least significant byte, the lowest descrambling factor LSBF is supplied from the descrambler 4 to the serial / parallel converter 5.

It is descrambled by the scrambling factor supplied in this way.

The latch clock LATCK is a clock signal DBCK passed or inverted by the edge signal EDGE.

However, if the data output DSDATA of the CDP DSP is latched and output by the rising edge of the clock signal DBCK, the inverted clock signal DBCK as the edge signal EDGE is '0' is output. Becomes the latch clock LATCK, and according to the present invention, the serial data DSDATA is latched and received by the falling edge of the clock signal DBCK.

Also, if the data output DSDATA of the CDP DSP interfaced with the present invention is latched and output by the falling edge of the clock signal DBCK, the clock signal passed as it is as the edge signal EDGE is '1' The DBCK becomes the latch clock LATCK, and according to the present invention, the serial data DADATA is received and received at the rising edge of the clock signal DBCK.

Thus, 16 bits of data per channel are output in parallel in 8 bits, that is, 1 byte unit.

When the signal of each part of the serial / parallel converter 5 described above has a transmission order signal DIR of '0', an L channel transmission signal LCHL of '0', and an edge signal EDGE of '0', The timing diagram as shown in FIG. 10 can also be represented.

As shown in FIG. 10, even if the data inputted to the interface device according to the present invention is from the middle of one channel, the data received by the interface device according to the present invention always starts from the R channel to the L channel again. The order of the R channels is followed.

Since the start of the channel accepted by the interface device according to the present invention is represented by a section of logical value '1' of the effective channel start signal CHST, it is invalid in a section of which the logical value of the effective channel start signal CHST is '0'. Since the data is output and the logical value of the effective channel start signal (CHST) is '1', the pulse is not generated when the first and second byte reception completion signals (1st-Byte-end, 2st-Byte-end) are valid. 8-bit parallel data is output only when the logical value of the effective channel start signal CHST is '1'.

As described above, the data interface device according to the present invention enables various types of data interfaces to improve compatibility of products.

Claims (3)

Effective channel start signal (CHST) and channel for outputting the L channel and the R channel (Right Channel) by inputting the scrck signal (LRCK), the L channel transmission signal (LCHL), and the clock signal (DBCK). An effective channel start signal generator 1 for outputting the strobe signal CHSB, The edge signal EDGE, the clock signal DBCK, the 16 offset selection signal SEL16-OFFSET, the 16 clock selection signal SEL16-CLOCK, and the effective channel start signal generator 1 are outputted. First and second byte reception completion signals (1st-Byte-End, 2nd-Byte-End) and latch clock (LATCK) to indicate completion of data reception by inputting channel start signal CHST and channel strobe signal CHSB. ) Is a data reception completion signal generator 2 generating a transmission transmission repair signal DIR and a first and second byte reception completion signals 1st-Byte outputted from the data reception completion signal generator 2. Most Significat Bit / Least Significant that generates the most significant byte discrimination signal (MSBH) that determines whether the data inputted as -End, 2nd-Byte-End) is the most significant byte (MSB) or least significant byte (LSB) Bit) discriminating unit 3, the data is inputted by the transmitted clock signal (DBCK) The second byte reception completion signal (2nd-Byte-End) output from the new completion signal generation unit 2 and the most significant byte determination signal MSBH output from the MSB / LSB determination unit 3 are input. The highest descrambling factor (Descrambling) is received according to the most significant (MSB) byte and the least significant (LSB) byte by receiving the most significant byte discrimination signal (MSBH) as an input every time the input of the second byte reception completion signal (2nd-Byte-End) per channel is completed. The descrambler 4 for calculating the factor and the lowest descrambling factors MSBF and LSBF, and the latch clock LATCK D for outputting the serial data DSDATA transmitted from the data reception completion signal generator 2. Received and buffered according to the first and second byte reception completion signals (1st-yte-End, 2nd-Byte-End) output from the data reception completion signal generator 2, and from the descrambler 4 Top and bottom D output And a serial / parallel converter (5) for descrambling according to the scrambling factors (MSBF, LSBF) and outputting the data as 8-bit parallel data. The device of claim 1, wherein the effective channel start signal (CHST) is used as an enable signal of the data reception completion signal generator (2) for transmitting invalid data. The method of claim 1, wherein the first and second byte reception completion signals 1st-yte-End and 2nd-Byte-End have a margin between the latch clock LATCK and a half clock for stable data transmission. Data interface device.