KR100190302B1 - Double cylinder capacitor fabrication method of semiconductor device - Google Patents
Double cylinder capacitor fabrication method of semiconductor device Download PDFInfo
- Publication number
- KR100190302B1 KR100190302B1 KR1019950019160A KR19950019160A KR100190302B1 KR 100190302 B1 KR100190302 B1 KR 100190302B1 KR 1019950019160 A KR1019950019160 A KR 1019950019160A KR 19950019160 A KR19950019160 A KR 19950019160A KR 100190302 B1 KR100190302 B1 KR 100190302B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- insulating film
- film
- storage electrode
- charge storage
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 제조공정을 간단히 하면서 동시에 충분한 양의 캐패시턴스를 확보할 수 있는 실린더 구조 캐패시터의 전하저장전극 형성방법에 관한 것으로, 반도체 기판에 트랜지스터 또는 여타의 소자 및 층간절연층을 형성한 다음 기 형성된 일정소자와의 콘택을 위한 콘택홀 형성후, 캐패시터의 전하저장전극 형성방법에 있어서, 상기 층간절연층 상부 및 콘택홀 내부에 제 1 전하저장전극용 전도막을 형성하는 제 1 단계; 전하저장전극 영역의 상기 전도막 상부에 정재파 영향을 받는 감광막을 이용한 리소그래피 공정을 통해 주름진 형태의 감광막 패턴을 형성하는 제 2 단계; 상기 감광막 패턴 측벽에 절연층을 형성하는 제 3 단계; 상기 감광막 패턴 및 절연층을 삭각장벽으로 하여 하부의 상기 제 1 전하저장전극용 전도막을 식각하는 제 4 단계; 상기 감광막 패턴을 제거한 다음, 전체 상부에 제 2 전하저장전극용 전도막을 증착하고, 블랭킷 에치백하는 제 5 단계; 및 상기 절연층을 제거하는 제 6 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method of forming a charge storage electrode of a cylindrical capacitor that can simplify a manufacturing process and at the same time ensure a sufficient amount of capacitance. A method of forming a transistor or other device and an interlayer insulating layer on a semiconductor substrate, and then A method for forming a charge storage electrode of a capacitor after forming a contact hole for contact with an element, the method comprising: a first step of forming a conductive film for a first charge storage electrode in an upper portion of the interlayer insulating layer and in a contact hole; A second step of forming a wrinkled photosensitive film pattern through a lithography process using a photosensitive film affected by standing waves on the conductive film in the charge storage electrode region; Forming an insulating layer on sidewalls of the photoresist pattern; Etching the lower conductive film for the first charge storage electrode using the photoresist pattern and the insulating layer as a cut barrier; Removing the photoresist pattern, and then depositing a conductive film for the second charge storage electrode on the entire upper portion, and blanket etching back; And a sixth step of removing the insulating layer.
Description
제1a도 내지 제1d도는 본 발명의 일실시예에 따른 전하저장전극 형성 공정 단면도.1A to 1D are cross-sectional views of a process of forming a charge storage electrode according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 2 : 층간절연막 3 : 폴리실리콘막1, 2: interlayer insulating film 3: polysilicon film
4 : 감광막 패턴 5 : 산화막4: photosensitive film pattern 5: oxide film
6A : 제1실린더 6B : 제2실린더6A: 1st cylinder 6B: 2nd cylinder
본 발명은 반도체 장치 제조 분야에 관한 것으로 특히, 전하저장전극의 유효 표면적을 넓혀 캐패시턴스를 증대시키기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method for increasing capacitance by increasing the effective surface area of a charge storage electrode.
단순 스택구조의 캐패시터나 실린더 구조의 캐패시터는 제조공정이 간단하여 널리 사용되고 있으나, 소자의 집적도가 향상되고, 단위 셀의 크기가 축소됨에 따라 충분한 양의 캐패시턴스를 확보하는데 한계가 따르며, 이웃하는 전하저장전극 간의 브릿지(bridge) 유발 우려가 높다.Capacitors of simple stack structure or capacitors of cylindrical structure are widely used due to the simple manufacturing process, but there is a limit in securing sufficient capacitance as device density is increased and unit cell size is reduced. There is a high risk of causing bridges between electrodes.
종래에는 실린더 구조의 캐패시터, 핀(Fin) 구조의 캐패시터 등 여러 가지 변형된 형태의 캐패시터를 사용하여 전술한 문제점을 해결하기 위한 시도가 있었으나, 제조공정 상의 어려움 등으로 인하여 양산에 많은 문제점이 있다.Conventionally, there have been attempts to solve the above-mentioned problems by using various types of modified capacitors, such as a capacitor of a cylinder structure and a capacitor of a fin structure, but there are many problems in mass production due to difficulties in the manufacturing process.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 제조공정이 간단하면서 동시에 충분한 양의 캐패시턴스를 확보할 수 있는, 측벽에 주름을 갖는 이중 실린더 구조의 전하저장전극 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method of forming a charge storage electrode of a double-cylinder structure having a wrinkle on the side wall, which can simplify the manufacturing process and at the same time secure a sufficient amount of capacitance. .
상기 목적을 달성하기 위한 본 발명은, 반도체 기판과 연결되는 제1 전도막을 형성하는 제1단계, 상기 제1 전도막 상에, 정재파 영향을 받은 감광막으로 그 측벽에 주름을 갖는 감광막 패턴을 형성하는 제2단계, 상기 제2단계가 완료된 전체 구조상에 절연막을 형성하고, 상기 절연막을 전면식각하여 상기 감광막 패턴 측벽 상에 절연막을 잔류시키는 제3단계, 상기 감광막 패턴을 제거하여, 표면에 주름을 갖는 절연막 기둥을 형성하는 제4단계, 상기 제4단계가 완료된 전체 구조상에 제2 전도막을 형성하고, 상기 제2 전도막을 전면식각하여 상기 절연막 기둥 측벽에 상기 제2 전도막을 잔류시키는 제5단계 및 상기 절연막 기둥을 제거하여, 상기 제1 전도막과 연결되며 그 측벽에 주름을 갖는 제1 실린더 및 상기 제1 실린더를 둘러싸며 그 측벽에 주름을 갖는 제2 실린더로 이루어진 전하저장전극을 형성하는 제6단계를 포함하는 측벽에 주름을 갖는 이중 실린더 구조의 전하저장전극 형성 방법을 제공한다.The present invention for achieving the above object, a first step of forming a first conductive film connected to a semiconductor substrate, on the first conductive film, forming a photosensitive film pattern having wrinkles on the sidewalls of the photosensitive film affected by standing waves A third step of forming an insulating film on the entire structure of the second step, the second step is completed, the third step of remaining the insulating film on the photosensitive film pattern sidewall by etching the entire surface of the insulating film, by removing the photosensitive film pattern, having a wrinkle on the surface A fourth step of forming an insulating film pillar, a fifth conductive film forming a second conductive film on the entire structure of the fourth step, and etching the entire surface of the second conductive film to leave the second conductive film on the sidewall of the insulating film pillar; Removing the insulating film pillar, the first cylinder is connected to the first conductive film and has a corrugation on the side wall and the corrugation on the side wall surrounding the first cylinder Provided is a method of forming a charge storage electrode having a double cylinder structure having wrinkles on a sidewall including a sixth step of forming a charge storage electrode formed of a second cylinder.
이하, 첨부된 도면 제1a도 내지 제1d도를 참조하여 본 발명의 일 실시예에 따른 측벽에 주름을 갖는 이중 실린더 구조의 전하저장전극 형성 방법을 설명한다.Hereinafter, a method of forming a charge storage electrode having a double cylinder structure having wrinkles on sidewalls according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1D.
먼저, 제1a도에 도시한 바와 같이 트랜지스터 및 비트라인 형성 공정이 완료된 반도체 기판 상(도시하지 않음)에 제1 및 제2 층간절연막(1, 2)을 형성하여 평탄화 시킨다. 이때, 제2 층간절연막(2)은 이후에 형성될 플라즈마 보조 화학기상증착법(PECVD)에 의한 산화막과는 습식식각 선택비가 다른 산화막이 질화막으로 형성한다.First, as shown in FIG. 1A, first and second interlayer insulating films 1 and 2 are formed and planarized on a semiconductor substrate (not shown) in which transistor and bit line forming processes are completed. In this case, the second interlayer insulating film 2 is formed of an nitride film having a wet etching selectivity different from that of the oxide film formed by the plasma assisted chemical vapor deposition (PECVD).
이어서, 제1 및 제2 층간절연막(1, 2)을 이방성 건식식각법을 이용하여 선택적으로 식각해서 반도체 기판을 노출시키는 콘택홀을 형성하고, 전체 구조상에 제1 폴리실리콘막(3)을 형성하여 콘택홀을 통해 제1 폴리실리콘막(3)이 반도체 기판과 연결되도록 한다.Subsequently, the first and second interlayer insulating films 1 and 2 are selectively etched using anisotropic dry etching to form contact holes for exposing the semiconductor substrate, and the first polysilicon film 3 is formed on the entire structure. The first polysilicon film 3 is connected to the semiconductor substrate through the contact hole.
다음으로, 제1 폴리실리콘막(3) 상에 정재파 영향을 받는 감광막을 도포한 다음 전하저장전극 형성용 마스크를 이용한 포토리소그래피 공정을 실시하여 감광막 패턴(4)을 형성한다. 이때, 감광막 패턴(4)은 노광시 정재파 효과로 그 측벽에 주름이 형성된다.Next, a photosensitive film subjected to standing waves is applied on the first polysilicon film 3, and then a photolithography process using a mask for forming a charge storage electrode is performed to form the photosensitive film pattern 4. At this time, the photoresist pattern 4 has wrinkles on its sidewalls due to standing wave effects during exposure.
다음으로, 감광막 패턴(4) 형성이 완료된 전체 구조상에 산화막(5)을 형성하여, 감광막 패턴(4) 측벽 상에 형성되는 산화막(5)이 감광막 패턴(4) 측벽의 주름을 따라 주름지도록 한다. 이때, 상대적으로 낮은 온도에서 산화막 형성이 가능한 플라즈마 보호 화학기상증착법(PECVD)으로 산화막(5)을 형성하여 감광막 패턴(4)이 타지 않도록 한다.Next, an oxide film 5 is formed on the entire structure where the photoresist pattern 4 is formed so that the oxide film 5 formed on the sidewall of the photoresist pattern 4 is wrinkled along the wrinkles of the sidewall of the photoresist pattern 4. . At this time, the oxide film 5 is formed by plasma protective chemical vapor deposition (PECVD), which enables formation of an oxide film at a relatively low temperature, so that the photoresist pattern 4 is not burned.
이어서, 산화막(5)을 전면식각하여 제1b도에 도시한 바와 같이 감광막 패턴(4) 측벽 상에 산화막(5)이 주름진 상태로 남도록 한다.Next, the oxide film 5 is etched entirely so that the oxide film 5 remains wrinkled on the sidewalls of the photosensitive film pattern 4 as shown in FIG. 1B.
다음으로, 제1c도에 도시한 바와 같이 감광막 패턴(4) 및 산화막(5)을 식각 마스크로 이용하여 제1 폴리실리콘막(3)을 선택적으로 식각해서, 제1 폴리실리콘막(3)이 콘택홀 내부와 콘택홀 입구 부분에 잔류되도록 하고, 콘택홀 입구의 양단부에서 산화막(5)과 제1 폴리실리콘막(3)이 연결되도록 한다. 이어서, 감광막 패턴(40)을 제거하여 주름진 산화막(5) 기둥을 형성한다.Next, as shown in FIG. 1C, the first polysilicon film 3 is selectively etched using the photosensitive film pattern 4 and the oxide film 5 as an etching mask, so that the first polysilicon film 3 is etched. The oxide film 5 and the first polysilicon film 3 are connected to both ends of the contact hole and the contact hole inlet, and are connected at both ends of the contact hole inlet. Subsequently, the photosensitive film pattern 40 is removed to form a corrugated oxide film 5 pillar.
다음으로, 전체 구조상에 제2 폴리실리콘막을 증착하여, 주름진 산화막(5) 기둥의 측벽을 따라 제2 폴리실리콘막이 주름지도록 한다. 이어서, 제2 폴리실리콘막을 전면식각하여 산화막(5) 기둥의 측벽 상에 제2 폴리실리콘막이 남도록 하고, 제2 층간 절연막(2)과 산화막(5)과의 식각 선택비가 높은 용액으로 식각하여 산화막(5)을 제거함으로써, 그 측벽이 주름진 제1 실린더(6A)와, 제1 실린더(6A)를 둘러싸며 그 측벽 역시 주름진 제2 실린더(6B)로 이루어지는 이중 실린더 구조의 전하저장전극을 형성한다. 이때, 제1 실린더(6A)와 제2 실린더(6B)는 제1 폴리실리콘막(3)과 연결된다.Next, a second polysilicon film is deposited on the entire structure so that the second polysilicon film is corrugated along the sidewall of the corrugated oxide film 5 pillar. Subsequently, the second polysilicon film is etched entirely so that the second polysilicon film remains on the sidewall of the pillar of the oxide film 5, and the oxide film is etched with a solution having a high etching selectivity between the second interlayer insulating film 2 and the oxide film 5. By removing (5), a double cylinder structured charge storage electrode is formed, which is composed of the first cylinder 6A having a corrugated sidewall and the second cylinder 6B having a corrugated side wall surrounded by the first cylinder 6A. . At this time, the first cylinder 6A and the second cylinder 6B are connected to the first polysilicon film 3.
상기와 같이 이루어지는 본 발명은 전하저장전극을 주름진 폴리실리콘막으로 이중 실린더 구조를 형성함으로써, 비교적 간단한 제조공정으로 높은 캐패시턴스를 얻을 수 있는 전하저장전극을 형성할 수 있다.According to the present invention as described above, the charge storage electrode can be formed of a corrugated polysilicon film to form a double cylinder structure, whereby a charge storage electrode capable of obtaining high capacitance can be formed by a relatively simple manufacturing process.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950019160A KR100190302B1 (en) | 1995-06-30 | 1995-06-30 | Double cylinder capacitor fabrication method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950019160A KR100190302B1 (en) | 1995-06-30 | 1995-06-30 | Double cylinder capacitor fabrication method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970004004A KR970004004A (en) | 1997-01-29 |
KR100190302B1 true KR100190302B1 (en) | 1999-06-01 |
Family
ID=19419505
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950019160A KR100190302B1 (en) | 1995-06-30 | 1995-06-30 | Double cylinder capacitor fabrication method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100190302B1 (en) |
-
1995
- 1995-06-30 KR KR1019950019160A patent/KR100190302B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR970004004A (en) | 1997-01-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2591930B2 (en) | Method for manufacturing capacitor of semiconductor device | |
KR100255064B1 (en) | Method of forming a capacitor over a semiconductor substrate | |
JP2780156B2 (en) | Semiconductor memory device and method of manufacturing the same | |
KR100190302B1 (en) | Double cylinder capacitor fabrication method of semiconductor device | |
US20070155114A1 (en) | Method for manufacturing semiconductor device | |
JPH0831577B2 (en) | Highly integrated semiconductor device manufacturing method | |
KR0135709B1 (en) | Manufacture of semiconductor device | |
KR100218730B1 (en) | Fabricating method of semiconductor device | |
KR0151257B1 (en) | Method for manufacturing a semiconductor memory device | |
KR950004524A (en) | Method of forming charge storage electrode of capacitor | |
KR100315040B1 (en) | Method for forming capacitor in dram device | |
KR100232161B1 (en) | Manufacturing method of semiconductor memory device | |
KR100382536B1 (en) | Capacitor structure and manufacturing method thereof | |
KR970011676B1 (en) | Method of forming semiconductor device capacitor | |
KR100236072B1 (en) | Structure of capacitor for semiconductor device and manufacturing method thereof | |
KR960013634B1 (en) | Capacitor manufacture of semiconductor device | |
KR100204021B1 (en) | Forming method for charge storage electrode of semiconductor device | |
KR960003859B1 (en) | Method of making a capacitor for a semiconductor device | |
KR0179144B1 (en) | Method for manufacturing semiconductor capacitor | |
KR960006721B1 (en) | Stacked capacitor fabrication process | |
KR19980020704A (en) | Capacitor Manufacturing Method for Semiconductor Devices | |
KR950034784A (en) | Method for forming storage electrode of semiconductor device | |
KR19990004895A (en) | Charge storage electrode of semiconductor device and forming method thereof | |
KR19990065309A (en) | Manufacturing method of semiconductor device with improved capacitance using anti-reflection film | |
KR970003959A (en) | Method of forming charge storage electrode of capacitor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20051219 Year of fee payment: 8 |
|
LAPS | Lapse due to unpaid annual fee |