KR100204021B1 - Forming method for charge storage electrode of semiconductor device - Google Patents
Forming method for charge storage electrode of semiconductor device Download PDFInfo
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- KR100204021B1 KR100204021B1 KR1019950050931A KR19950050931A KR100204021B1 KR 100204021 B1 KR100204021 B1 KR 100204021B1 KR 1019950050931 A KR1019950050931 A KR 1019950050931A KR 19950050931 A KR19950050931 A KR 19950050931A KR 100204021 B1 KR100204021 B1 KR 100204021B1
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- charge storage
- storage electrode
- mask
- interlayer insulating
- halftone phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 하프톤 위상반전마스크를 사용하여 전하저장전극의 콘택홀 형성을 위한 마스크 및 식각 공정을 수행하여, 하프톤 위상반전마스크의 사이로브 효과에 의해 전하저장전극의 표면적을 넓혀주는 방법에 관한 것으로, 전하저장전극에 의한 단차를 최소화시킴으로 후속 공정인 금속 콘택 마스크 형성 및 금속 마스크 공정의 공정 여유도를 감소시켜 후속 공정을 용이하게 하고, 공정이 단순화된다.The present invention relates to a method for enlarging the surface area of a charge storage electrode by a sirobe effect of the halftone phase shift mask by performing a mask and an etching process for forming a contact hole of the charge storage electrode using a halftone phase shift mask. By minimizing the step difference caused by the charge storage electrode, the process margin of the metal contact mask formation and the metal mask process, which is a subsequent process, is reduced, thereby facilitating the subsequent process, and the process is simplified.
Description
제1도는 하프톤 위상반전마스크를 설명하기 위한 개념도, 제2a도는 내지 제2c도는 본 발명의 일실시예에 따른 전하저장전극 형성 공정도.1 is a conceptual diagram for explaining a halftone phase inversion mask, Figures 2a through 2c is a process chart of forming a charge storage electrode according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
100 : 하프톤 위상반전마스크 200 : 강도분포곡선100: halftone phase inversion mask 200: intensity distribution curve
201 : 사이드로브 1 : 층간절연막201: side lobe 1: interlayer insulating film
2 : 포토레지스터 패턴 3 : 폴리실리콘막2: photoresist pattern 3: polysilicon film
본 발명은 반도체 메모리 장치의 캐패시터 형성 방법에 관한 것으로, 특히 간소화된 공정으로 표면적을 극대화한 캐패시터의 전하저장전극(storage node)을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor in a semiconductor memory device, and more particularly, to a method of forming a storage node of a capacitor having a maximum surface area by a simplified process.
일반적으로, 반도체 메모리 장치의 집적도가 점차 증가하게 됨에 제한된 면적에서 장치가 필요로 하는 캐패시턴스를 확보하기 위하여 캐패시터의 전하저장전극은 그 표면적을 크게하여야 한다.In general, as the degree of integration of semiconductor memory devices is gradually increased, the charge storage electrode of the capacitor has to have a large surface area in order to secure the capacitance required by the device in a limited area.
따라서, 종래에는 핀 구조나 실린더 구조등 다양한 3차원 구조의 전하저장전극을 형성하고 있다.Therefore, conventionally, charge storage electrodes having various three-dimensional structures, such as fin structures and cylinder structures, are formed.
그러나, 이러한 3차원 구조의 전하저장전극은 기판의 단차를 증가시키므로 후속 공정인 금속 콘택 마스크 및 금속 마스크 공정에서 공정의 여유도가 감소되는 결과를 초래했으며 또한 그 형상을 구현하기 위한 공정이 난이하여 제조수율을 떨어뜨리게 된다.However, the charge storage electrode of the three-dimensional structure increases the step height of the substrate, resulting in a reduction in the margin of the process in the subsequent metal contact mask and metal mask process, and also difficult to implement the shape The production yield will be reduced.
따라서, 제조 공정의 단순화 및 단차 유발을 방지하면서 고집적 반도체 장치의 캐패시턴스를 확보할 수 있는 전하저장전극 형성 방법이 필요하게 되었다.Accordingly, there is a need for a method of forming a charge storage electrode capable of securing the capacitance of a highly integrated semiconductor device while simplifying the manufacturing process and preventing the step.
본 발명은 상기 제반 요구 사항에 따라 안출된 것으로, 제조 공정의 단순화 및 단차를 줄이면서도 고집적 장치의 캐패시턴스를 확보할 수 있는 반도체 장치의 전하저장전극 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in accordance with the above-described requirements, and an object thereof is to provide a method for forming a charge storage electrode of a semiconductor device capable of securing the capacitance of a highly integrated device while simplifying the manufacturing process and reducing the step.
상기 목적을 달성하기 위하여 본 발명은 반도체 장치의 전하저장전극 형성 방법에 있어서, 층간절연막 상에 하프톤 위상반전마스크를 사용한 포토마스크 공정으로 전하저장전극 콘택 부위가 오픈 되며 콘택 부위의 주변지역이 손실된 포토레지스터 패턴을 형성하는 단계; 상기 포토레지스터 패턴을 식각장벽으로 상기 층간절연막을 식각하여 콘택 부위의 반도체 기판을 노출시키고 콘택주변 부위를 부분 식각하는 단계; 상기 포토레지스터 패턴을 제거하는 단계; 및 전체 구조 상부 표면을 따라 소정 두께의 전하저장전극용 전도막을 증착하고 상기 층간절연막의 부분 식각된 부위를 덮는 전하저장전극 마스크를 사용하여 상기 전도막을 패터닝하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a charge storage electrode of a semiconductor device, wherein the charge storage electrode contact region is opened by a photomask process using a halftone phase inversion mask on an interlayer insulating film, and the peripheral region of the contact region is lost. Forming a photoresist pattern; Etching the interlayer insulating layer using the photoresist pattern as an etch barrier to expose a semiconductor substrate at a contact portion and partially etch a portion around the contact; Removing the photoresist pattern; And depositing a conductive film for a charge storage electrode having a predetermined thickness along the entire upper surface of the structure, and patterning the conductive film using a charge storage electrode mask covering a partially etched portion of the interlayer insulating film.
이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
제1도에 도시된 바와 같이 하프톤(Halftone)위상반전마스크(100)는 마스크의 차광지역(101)에서 3-12% 정도로 부분적으로 투과하는 광투과율 물질을 사용하는 마스크로서, 차광지역(101) 및 투광지역(102)의 빛이 상호 간섭 작용을 일으켜 포토레지스터이 도포된 웨이퍼에 도달하는 광의 강도(Intensity) 분포 곡선(200)이 도면에 도시된 바와같이 나타난다.As shown in FIG. 1, the halftone phase reversal mask 100 is a mask using a light transmissive material partially transmitted by 3-12% in the light shielding area 101 of the mask. ) And the intensity distribution curve 200 of light reaching the photoresist-coated wafer where light in the transmissive region 102 interacts with each other, as shown in the figure.
즉, 투광지역(102)의 광 콘트라스트 특성이 종래의 크롬 마스크에 비하여 크게 증가하여 해상력과 초점 여유도가 크게 개선되지만, 반대로 차광지역(101)에 있어서도 사이드로브(Sidelobe)(201)라 불리는 강도 피크(Intensity Peak)가 증가하여 차광지역의 포토레지스터의 일부 노광되게 되는 효과를 가져온다.That is, although the light contrast characteristic of the light-transmitting region 102 is greatly increased compared to the conventional chrome mask, the resolution and the focus margin are greatly improved. The peak (Intensity Peak) is increased, which results in the partial exposure of the photoresist in the light shielding area.
사이드로브의 강도는 차광지역의 광투과율이 증가할수록 증가하며, 노광시 노광원의 유효크기 즉, 높은 간섭성(Coherenct)을 갖는 광으로 노광을 실시할 경우에 증가하고, 콘택 홀간과 같은 피치 크기가 작을수록 증가하게 된다.The intensity of the side lobe increases as the light transmittance in the light shielding area increases, and increases when the exposure is performed with the effective size of the exposure source during exposure, that is, light having high coherenct, and the same pitch size as between contact holes. The smaller the value is, the larger the value becomes.
본 발명은 상기와 같은 특성을 갖는 하프톤 위상반전마스크를 사용하여 마스크 및 식각 공정을 수행함으로써 전하저장전극 콘택 홀을 형성하는 것으로, 이때, 사이드로브 지역의 부위의 층간절연막이 일부 부분식각됨으로, 층간절연막이 골곡지게 된다.According to the present invention, a charge storage electrode contact hole is formed by performing a mask and an etching process using a halftone phase inversion mask having the above characteristics. In this case, since the interlayer insulating film of the portion of the side lobe region is partially etched, The interlayer insulating film becomes corrugated.
그러면 결과적으로 층간절연막 상에 형성되는 전하저장전극 전도막도 굴곡진 부위에 의해 표면적이 증가되게 된다.As a result, the surface area of the charge storage electrode conductive film formed on the interlayer insulating film is increased due to the curved portion.
따라서, 단차를 최소화시키면서도 간단한 공정으로 캐패시턴스가 증가된 전하저장전극을 얻을 수 있다Therefore, a charge storage electrode with increased capacitance can be obtained by a simple process while minimizing step difference.
제2a도 내지 제2c도는 본 발명의 일실시예에 따른 전하저장전극 형성 공정도이다.2A through 2C are process charts for forming a charge storage electrode according to an exemplary embodiment of the present invention.
먼저, 제2a도는 반도체 기판을 덮고 있는 층간절연막(1)상에 하프톤 위상반전마스크를 사용한 마스크 공정으로 전하저장전극 콘택 마스크인 포토레지스터 패턴(2)을 형성한 상태로서, 사이드로브 지역의 포토레지스터(도면의 a 부위)가 손실되어 있음을 알 수 있다. 이때 사이드로브를 의도적으로 발생시키시 위해 적정 노광량을 초과한 노광에너지를 사용하여 노광공정을 실시한다.First, FIG. 2A is a state in which a photoresist pattern 2, which is a charge storage electrode contact mask, is formed on the interlayer insulating film 1 covering the semiconductor substrate by a mask process using a halftone phase inversion mask. It can be seen that the register (site a in the figure) is missing. At this time, in order to intentionally generate side lobes, an exposure process is performed using exposure energy exceeding an appropriate exposure amount.
이어서, 제2b도는 사이드 로브 지역이 일부 손실된 상기 포토레지스터 패턴(2)을 식각장벽으로하여 상기 층간절연막(1)을 식각하고 포토레지스터(2)을 제거한 상태로서, 포토레지스터가 손실되어 있던 지역(도면의 a)의 층간절연막도 부분 식각되어 있음을 알 수 있다.Subsequently, in FIG. 2B, the interlayer insulating film 1 is etched using the photoresist pattern 2 partially missing the side lobe region as an etch barrier and the photoresist 2 is removed, where the photoresist is lost. It can be seen that the interlayer insulating film of (a) in FIG. 5 is also partially etched.
이어서, 제 2C 도와 같이 전하저장전극용 폴리실리콘막(3)을 전체구조 상부 표면을 따라 일정두께로 증착하고, 상기 층간절연막이 부분 식각된 부위를 포함하도록 전하저장전극 마스크를 사용해서 폴리실리콘막(3)을 식각하여 전하저장전극을 형성한다.Subsequently, a polysilicon film 3 for charge storage electrodes 3 is deposited along the upper surface of the entire structure as shown in FIG. 2C, and the polysilicon film is formed using a charge storage electrode mask so that the interlayer insulating film includes a partially etched portion. (3) is etched to form a charge storage electrode.
상술한 바와 같은 본 발명은 전하저장전극에 의한 단차를 최소화시킴으로 후속 공정인 금속 콘택 마스크 형성 및 금속 마스크 공정의 공정 여유도를 감소시켜 후속 공정을 용이하게 하고, 공정이 단순화된다. 결국, 단차 해소, 공정의 간소화, 캐패시턴스 확보를 용이하게 하여 고집적 반도체 메모리 장치의 수율 및 신뢰도를 향상시킨다.As described above, the present invention minimizes the step difference caused by the charge storage electrode, thereby facilitating the subsequent process by reducing the metal contact mask formation and the process margin of the metal mask process. As a result, it is possible to reduce the step difference, simplify the process, and secure the capacitance, thereby improving the yield and reliability of the highly integrated semiconductor memory device.
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