KR100190005B1 - Digital sync. correction method for on screen display - Google Patents

Abstract

The present invention discloses a synchronization correction method for an on screen display (OSD). A system comprising a synchronization separator for separating a horizontal synchronization signal from a signal received from a broadcasting station, a synchronization correction unit for correcting and outputting a frequency of the separated horizontal synchronization signal, and an OSD unit for inputting the corrected horizontal synchronization signal for OSD. In the method of correcting the frequency of the horizontal synchronizing signal, the method may include determining whether a horizontal synchronizing signal is input, measuring a reference signal to determine an operation section when the horizontal synchronizing signal is input, and whether the operation mode is a lock mode. Determining whether it is in the dismantling mode and, if the operation mode is the lock mode, outputs a horizontal synchronizing signal or a pseudo-synchronization signal predicted in advance to the OSD section according to the operation section, and varies the width of the locking section to force the horizontal synchronization signal to be locked If the lock mode to enter the mode and the operation mode is the disassembled mode, the horizontal synchronization signal is output to the OSD unit. Characterized by comprising a dissolution step mode to predict the period of the synchronizing signal, and is effective to compensate a stable synchronizing signal at the time of reproduction of a VTR.

Description

Digital Sync Correction Method for On-Screen Display

1 is a block diagram of a conventional horizontal synchronization correction circuit.

2 is a diagram for explaining a conventional digital synchronization correction circuit in which the method according to the present invention is performed.

3 is a detailed block diagram of the conventional digital synchronous correction circuit shown in FIG.

4 is a flowchart for explaining a digital synchronization correction method for an on-screen display according to the present invention.

FIG. 5 is a conventional flowchart for explaining in detail the 58th step shown in FIG.

FIG. 6 is a conventional flowchart for explaining in detail the sixty-second step shown in FIG.

7 is a flowchart according to the present invention for explaining in detail the step 56 shown in FIG.

FIG. 8 is a flowchart of the present invention for explaining in detail the step 92 shown in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an on screen display (OSD) circuit that displays characters on an image signal in a video tape recorder (VTR), and particularly, to an input horizontal sync signal that is a reference for character display operation. The present invention relates to a digital synchronization correction method for an OSD which makes a frequency stable.

In the OSD circuit, jitter is generated in the input horizontal synchronizing signal, and when the frequency is shaken to some extent, the reference position of the character display is shaken, which causes a fatal problem of shaking the character. That is, when the electric field of the signal received from the broadcasting station is smaller than the predetermined value (usually called a weak electric field), the jitter of the horizontal synchronous signal separated from the received signal is increased from the received signal, which is fatal if directly inputted to the OSD circuit. Character blurring occurs.

FIG. 1 is a block diagram of a conventional horizontal synchronous retaining circuit, and includes a phase detector 22, a loop filter 24, and a voltage constituting a synchronous separator 10, a phase locked loop (PLL) 20. It consists of a voltage controlled oscillator (VCO) 26 and a divider 28.

The sync separator 10 shown in FIG. 1 inputs a signal transmitted from a broadcasting station through an input terminal 1N, and separates and outputs a horizontal sync signal. The VCO 26 of the phase locked loop 20 oscillates the same frequency as the frequency of the input signal, and the output frequency of the VCO 26 is divided by N by a divider 28 that divides the frequency into the phase detector 22. Feedback.

The output frequency of the divider 28 is equal to the frequency of the signal input to the phase detector 22 when the phase locked loop 20 is locked. That is, the analog PLL 20 suppresses jitter of the horizontal synchronizing signal generated in the weak electric field and outputs it to the on-screen display circuit through the output terminal OUT. Therefore, the horizontal synchronizing signal input by the OSC circuit has almost no jitter, and therefore, character shake does not occur even in the case of a weak electric field. Conventional OSD circuits have been able to improve many characteristics by using analog PLL 20, but still suffer from various problems with analog characteristics.

In other words, by using an analog circuit, it is sensitive to noise, and greatly affected by changes in temperature and device values. Also, since the VCO 26 operates at a high frequency, it acts as a source of noise to provide an adjacent circuit. There is a problem that adversely affects.

In addition, conventionally, the period of the horizontal synchronization signal input to the phase locked loop 20 has not been an exact integer multiple of the clock period of the automatic frequency control counter (second counter described later). Therefore, there is a need to track the period of the input horizontal synchronization signal by varying the lock period.

In order to solve the above-mentioned problems of the present invention, the jitter of the horizontal synchronizing signal used by the on-screen display is digitally suppressed to stabilize the frequency of the horizontal synchronizing signal, resulting in character shaking in the weak electric field. The present invention provides a digital synchronization correction method for an on-screen display that varies the lock section in the lock mode so as not to.

A synchronization separator for separating a horizontal synchronization signal from a signal received from a broadcasting station according to the present invention for achieving the above object, a synchronization correction unit for correcting and outputting the frequency of the separated horizontal synchronization signal and the correction pin horizontal synchronization signal In a system including an on-screen display to be used for input on-screen display, the digital synchronization correction method for correcting the frequency of the horizontal synchronization signal, the first judging step of determining whether the horizontal synchronization signal is input; A signal measuring step of measuring a reference signal to determine an operation section when a horizontal synchronization signal is input; a second judging step of determining whether an operation mode is a lock mode or a disengagement mode; and if the operation mode is the lock mode, the operation section The horizontal synchronization signal or the pseudo-prediction signal predicted in advance according to the on-screen Outputting to the lean display unit and varying the width of the lock section to force the horizontal synchronous signal to enter the lock mode; and outputting the horizontal synchronous signal to the on-screen display unit if the operation mode is the dismantling mode. Preferably, the decompression mode step of predicting the period of the pseudo-synchronous signal.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of a conventional digital correction circuit for performing a digital synchronous correction method for an on-screen display according to the present invention will be described.

2 is a diagram for explaining a digital synchronization correction circuit in which the method according to the present invention is performed, and is composed of a synchronization separator 30, a digital synchronization correction circuit 32, and an OSD unit 34.

The sync separator 30 shown in FIG. 2 separates only the horizontal sync signal from the signal input through the input terminal IN and outputs it to the digital sync correction circuit 32. The digital synchronous correction circuit 32 corrects the frequency of the horizontal synchronous signal and outputs it to the on-screen display unit 34.

Here, the period of the horizontal synchronization signal output from the synchronization separator 30 is Ti, the period of the signal output from the digital synchronization correction circuit 32 is To, and the period of the ideal horizontal synchronization signal without jitter is Th, digital synchronization correction. When the jitter of the signal input / output to / from the circuit 32 is J (i) and J (o), respectively, the periods Ti, To, J (o) and J (i) are as follows.

Ti = Th + J (i) --------- Formula (1)

To = Th + J (o) -------- Formula (2)

J (o) ≪ J (i) --------- Condition 1

Condition 1 corresponds to the object of the present invention.

The digital synchronization correction circuit 32 shown in FIG. 2 has two operation modes as follows.

First, the unlock mode is a transient state in which the lock mode is searched, and predicts an ideal period Th of the horizontal sync signal output from the sync separator 30. Next, the lock mode is locked, and the horizontal synchronization signal coming into the lock range is output to the on-screen display unit 34 without correction. However, when the horizontal synchronizing signal comes out of the lock section, a pseudo synchronizing signal having an ideal period Th predicted in the dismantling section is output to the on-screen display unit 34 instead of the horizontal synchronizing signal entered outside the current section. .

On the other hand, the digital synchronization correction circuit 32 has two operating sections, that is, a lock section and a pull in lock range.

First, the lock section is a section in which the horizontal synchronization signal input is allowed in the lock mode, and the pull-in section is a section counting the second variable when the lock mode is switched from the disassembly mode.

Here, the second variable indicates a lock in number, which is a variable value for switching between the lock mode and the unlock mode, and means the total number of times of the horizontal synchronization signal entering the lock section.

FIG. 3 is a detailed block diagram of the conventional digital synchronous correction circuit 32 shown in FIG. 2, which increments when a first signal is input, decreases when a second signal is input, and first and second signals. A first counter 40 which outputs a preset value which is not changed if it is not input, a preset counter in response to the preset value and the preset enable signal c, and a second counter which performs a counting operation in response to a clock input from the outside 42 and a preset enable signal C are generated when the horizontal synchronization signal is input, and a first signal is generated when the horizontal synchronization signal is input earlier than the lock section in the disassembly mode, and a second signal is generated when the horizontal synchronization signal is input later and locked. If the input is input to the interval, the first and second signals are not generated, and the operation value is set by comparing the counting value of the second counter 42 when the horizontal synchronization signal is input with the preset values and setting the pseudo synchronization signal. And controlling the switching of the operation mode by comparing the value of the second counter 42 with the operation section, and selectively selecting the horizontal synchronization signal or the pseudo synchronization signal according to the operation section in the lock mode to the on-screen display unit 34. The control unit 44 outputs the data.

The first counter 40 shown in FIG. 3 may be implemented as an up / down counter, and determines the preset value of the second counter 42, that is, the first variable.

The first and second signals input to the first counter 40 are output from the controller 44 and are synchronized with the corrected horizontal synchronization signal output through the output terminal OUT. The first counter 40 increases the preset value by one in response to the first signal generated once by the controller 44 whenever the horizontal synchronous signal is input in advance in the dismantling mode before the lock section. Each time, the preset value is decreased by one in response to the second signal generated once from the controller 44. The first counter 40 does not convert the preset value when the horizontal synchronization signal is input in the lock section. That is, it does not increase or decrease the preset value.

The second counter 42 outputs from the first counter 40 in response to the preset enable signal C generated from the controller 44 when the horizontal synchronous signal is input to the controller 44 through the input terminal IN1. Inputs a preset value, and is preset in response to the entered preset value. After the preset operation, an up counting operation is performed according to a clock input through the input terminal IN2.

When the horizontal synchronization signal is input to the control unit 44, a value counted by the second counter 42 is referred to as a reference signal, and a period of a clock inputted through the input terminal IN2 to the second counter 42 is Tck. The period Ti of the horizontal synchronization signal input to the controller 44 is expressed by the following equation (3).

Ti = (reference signal-first variable) × Tck -------- Equation (3)

In this case, equation (3) is used by estimating the period of the pseudo synchronizing signal output to the on-screen display unit 34 in the section outside the lock section in the lock mode.

As a result, the controller 44 compares the reference signal with preset values and determines an operation section, controls the operation switching between the dismantling mode and the lock mode, and presets the second counter 42 when the horizontal synchronization signal is input. The enable signal C is output. In addition, it is determined whether the horizontal synchronization signal outputted through the output terminal OUT is a horizontal synchronization signal inputted through the input terminal IN1 or a pseudo synchronization signal, and the first and second signals are first counter 40. Will output

Hereinafter, a digital synchronization correction method for an on-screen display according to the present invention will be described with reference to the accompanying drawings.

FIG. 4 is a flowchart for explaining a digital synchronization correction method for an on-screen display according to the present invention performed by the control unit 44 shown in FIG. 3, and outputs a reference signal by determining whether a horizontal synchronization signal has been input. Steps 50 and 52, and a step of performing a correction operation according to the operation mode (steps 54 to 58).

The controller 44 shown in FIG. 3 determines whether the horizontal synchronization signal is input (step 50), and if so, measures the reference signal which is the counting value of the second counter 42 (step 52). After operation 52, the operation mode is checked (step 54), and in the lock mode, the width of the lock section is varied according to the operation section, and a horizontal sync signal or a pseudo sync signal is sent to the OSD unit 34 (step 56). In the disassembly mode, the horizontal synchronization signal is sent to the 0SD unit 34, and the period of the pseudo-synchronization signal is predicted (step 58).

FIG. 5 is a conventional flowchart for explaining in detail the step 58 shown in FIG. 4, and when the horizontal synchronizing signal is input, the horizontal synchronizing signal is immediately output to the on-screen display unit 34. Initializing the second counter 42 shown in FIG. 60 (step 60), and varying the first variable and the second variable according to the operation section in which the horizontal synchronization signal is input after the 60th step (step 62). And after step 62, determining whether the second variable has exceeded the predetermined threshold (step 64); and if the second variable has exceeded the predetermined threshold, switching from the disassembly mode to the lock mode (step 66). Consists of

FIG. 6 is a conventional flowchart for describing in detail the sixty-second step shown in FIG. 5, wherein the variables are varied by comparing the pull-in-section and the locking section with the input section of the horizontal synchronization signal. 70 to 86). The operation section of the dismantling mode is divided according to the reference signal.

In other words, if the reference signal is within the lock period, the operation period is divided into a lock period, and if the reference signal is within the pull-in period, the operation period is divided into a pull-in period.

Step 62 of FIG. 5 determines whether the horizontal synchronization signal is out of the pull-in-section (step 70), and if the horizontal synchronization signal is out of the pull-in-section, the first variable. Increasing the number and decreasing the second variable (step 72), if the horizontal synchronization signal is not out of the pull-in period, determining whether the horizontal synchronization signal is outside the lock period (step 74), and horizontal synchronization If the signal is outside the lock period, the first variable is increased, and the second variable is not changed (step 76). If the horizontal synchronous signal is not outside the lock period, determining whether the horizontal synchronous signal is within the lock period. (Step 78), if the horizontal synchronous signal is in the lock section, but not changing the first variable, and increasing the second variable (step 80), if the horizontal synchronous signal is not in the lock section, pull-in- Determining whether it is in the section ( Step 82), the first variable is decreased if the horizontal synchronization signal is in the pull-in period, the second variable is not changed (step 84), and the first variable is not in the pull-in period. The variable and the second variable are both reduced, and the process proceeds to step 64 shown in FIG.

That is, in the dismantling mode, when the horizontal synchronous signal is input in front of the lock section, the first variable, which is a preset value, is increased, and when the horizontal synchronous signal is input after the lock section, the first variable is decreased, as can be seen from Equation (3). The second counter 42 has an appropriate preset value (first variable), and follows the cycle of the input horizontal synchronization signal. At this time, the period Ti of the horizontal synchronization signal input through the input terminal IN1 and the first variable output from the first counter 40 have a relationship as shown in Equation (4).

Ti = (1r-first variable) × Tck -------- Equation (4)

Here, 1r represents a reference signal in the lock section.

On the other hand, when the horizontal synchronization signal enters the lock section, the second variable, which is the number of times the lock section has entered, is increased by one, and when the horizontal sync signal is out of the pull-in section, the second variable is decreased. In addition, the second variable does not change when the lock period is outside the pull-in-section. This is to minimize the effect of entering or exiting the lock section by the jitter of the input signal to the maximum.

As can be seen from equation (4), since the input horizontal synchronization signal has jitter, the first variable changes from time to time. However, since the average value of jitter is 0 and the probability of the jitter-free input period Th is high, the preset value when the second variable exceeds a predetermined threshold corresponds to the jitter-free input period Th.

In this way, the ideal period Th of the pseudo synchronization signal can be predicted.

Therefore, when the second variable exceeds a predetermined threshold value, the switch is released from the dismantling mode to the lock mode and the preset value (the first variable) is fixed.

7 is a flowchart according to the present invention for explaining in detail the step 56 shown in FIG. 4, the step of fixing the value of the first variable to the value immediately before the mode change (step 90), horizontal synchronization The second variable is changed (step 92) and the second variable is changed while outputting a horizontal sync signal or a pseudo sync signal to the on-screen display unit 34 by varying the width of the lock section according to the operation period of the signal. It is determined whether the threshold value has been exceeded (step 94), and when the threshold value is exceeded, the process is switched to the dismantling mode (step 96).

In the lock mode, the operation section is divided into a lock section when the reference signal is in the lock section and a pull-out section when the reference signal is in the pull-out section. Here, the pull-out-range means a section in which the second variable is counted when the lock mode is released from the lock mode.

FIG. 8 is a flowchart according to the present invention for explaining step 92 shown in FIG. 7 in detail. After step 90, it is determined whether the horizontal synchronization signal enters the front or the rear of the lock section. Step), and if the horizontal synchronization signal comes before or after the lock section, the pseudo sync signal is output to the on-screen display unit 34 at the end of the lock section, and the reference signal is initialized, the second variable is decreased, (Step 102), if the horizontal synchronization signal is not in front of or behind the lock section, determining whether the horizontal sync signal is in the lock section (step 104), and the horizontal sync signal is locked. If inside, the horizontal synchronization signal inputted through the input terminal IN1 is output to the on-screen display unit 34, and the existing signal is initialized, the second variable is increased, and the lock is performed. Initializing the width of the liver (step 106) and if the horizontal synchronization signal does not fall within the lock section, the pseudo sync signal is output to the on-screen display unit 34 at the time when the lock section ends, and the reference signal is initialized. The second variable is decreased, the width of the lock section is increased, and the process proceeds to step 94 (step 108).

The output timing of the horizontal synchronization signal output from the digital synchronization correction circuit 32 and the preset timing at which the second counter 42 is preset are input to the controller 44 in any operation section of the horizontal synchronization signal input through the input terminal IN1. You can see that it depends. That is, when the horizontal synchronous signal enters the lock section, the width of the lock section is initialized to the initial value without changing the width of the lock section. If the horizontal synchronous signal does not enter the lock section, the lock section is forcibly increased by increasing the width of the lock section. Enter the mode.

In addition, the second variable is not changed when it is outside the lock period but in the pull-out period. This is to prevent the lock mode from being easily released due to the jitter because the jitter of the input signal may easily go out of the lock section. When the input horizontal sync signal is changed to the input period without jitter or the jitter of the input signal is severe enough to go out of the pull-out section, the second variable becomes smaller than the threshold value and the power of the mode is turned off in the dismantling mode. Is done.

As described above, the digital synchronous correction method using the on-screen display according to the present invention can solve the problem of the conventional analog circuit because it digitally corrects the frequency of the horizontal synchronous signal, Since both the period Th and the clock period Tck of the digital synchronous correction circuit divide and use the signal output from the crystal oscillator X-TAL, there is almost no variation in the period (Th = 910.5 * Tck). However, for example, at the time of reproduction in a video tape recorder, the period Ti of the input signal, i.e., the horizontal synchronizing signal, becomes Ti = Th-(second variable-first variable) * Tck so that the deviation of the input signal period is varied. It becomes bigger. At this time, the digital synchronization correction method according to the present invention has the effect of compensating jitter of the input signal by varying the lock period and tracking the period Ti of the input signal by the period Th of the normal signal. have.

Claims (3)

A synchronization separator for separating the horizontal synchronization signal from a signal received from a broadcasting station, a synchronization correction unit for correcting and outputting a frequency of the separated horizontal synchronization signal, and an on-screen display for inputting the corrected horizontal synchronization signal In a digital synchronization correction method for correcting a frequency of the horizontal synchronization signal in a system including a screen display unit, the first determination step of determining whether the horizontal synchronization signal is input, and if the horizontal synchronization signal is input, determine an operation section. A signal measuring step of measuring a reference signal, a second judging step of determining whether an operation mode is a lock mode or a release mode; and if the operation mode is the lock mode, the horizontal synchronization signal or a pre-predicted pseudo synchronization signal according to the operation section Output to the on-screen display unit, A lock mode step of forcing the horizontal synchronization signal to enter the lock mode and outputting the horizontal synchronization signal to the on-screen display unit if the operation mode is the release mode, and predicting a period of the pseudo synchronization signal. And a dismantling mode step. The method of claim 1, wherein the locking mode step comprises: a variable value fixing step of fixing a value of a first variable to a value immediately before a mode change, and varying a width of the locking section according to an operation section of the horizontal synchronization signal; A variable variable and timing determining step of changing a second variable while outputting a synchronizing signal or the pseudo synchronizing signal to the on-screen display, a third judging step of determining whether the second variable exceeds a predetermined threshold value, and the second And a mode switching step of switching to the dismantling mode when the two variables exceed the predetermined threshold box, wherein the period of the pseudo synchronization signal is (reference signal-first variable) x external clock period. Digital synchronization correction method. 3. The method of claim 2, wherein the variable variable and timing determining step comprises determining whether the horizontal synchronization signal is in front of or behind the lock period after the variable value fixing step. Initializing the reference signal, decreasing a second variable, and increasing the width of the lock section while outputting the pseudo sync signal to the on-screen display at the end of the lock section if it is later entered. Determining whether the horizontal synchronization signal is within the lock period when not in front of or behind the locking period; and outputting the horizontal synchronization signal to the on-screen display unit when the horizontal synchronization signal is within the lock period. While initializing the reference signal, increasing the second variable, Initializing the width of the lock section; and if the horizontal sync signal does not fall within the lock section, outputting the pseudo-synchronous signal to the on-screen display unit at the time when the lock section ends, and initializing the reference signal. Reducing the two variables, increasing the width of the locking section, increasing the width of the locking section, and proceeding to the third determination step.