KR100189817B1 - Method and circuit to generate the focus signal of image pickup apparatus - Google Patents

Abstract

The present invention relates to a method and a circuit for generating a focus signal of an imaging device.

Analog / digital conversion means for converting a luminance signal of a video device into a digital signal; Digital signal processing means for obtaining an average value of the digital signals, accumulating the amount of change, and generating the result as a focus signal; And area selection means for generating a predetermined signal during a time in which a predetermined effective area is scanned for each field to control an operation time of the signal processing means.

By not using a high pass filter and a low pass filter, hardware can be scaled down.

Description

Method and circuit for generating focus signal of video equipment

1 is a schematic block diagram showing a conventional focus signal generating circuit.

2 is a schematic block diagram illustrating a focus signal generating circuit according to an exemplary embodiment of the present invention.

3 is a view showing a field screen for explaining the area selector of FIG.

4 is a block diagram showing the area selector of FIG.

5 is a block diagram illustrating a horizontal section selection circuit of FIG. 4.

6 is a block diagram illustrating a vertical section selection circuit of FIG. 4.

7 is a block diagram showing the digital signal processor of FIG.

* Explanation of symbols for main parts of the drawings

201: analog / digital converter 202: digital signal processor

203: region selector 401: horizontal section selection circuit

402: vertical section selection circuit 403: AND gate

701, 702, 703, 704: average value calculation unit

705, 706: change amount detecting section 707, 708: accumulating part

The present invention relates to a method and a circuit for generating a focus signal of an imaging device.

For example, a video presenter, a video camera, a camcorder, and the like generally generate a video signal using a charge coupled device (CCD). The video signal generated in this way is roughly divided into a luminance signal and a chroma signal. In the meantime, the automatic focusing unit of the imaging apparatus generates a focus signal proportional to the degree of focus, and then moves the objective lens to reflect the generated focus signal. Basically, the better the focus is, the higher the contrast and the higher the frequency component of the luminance signal. Therefore, the principle of generating the focus signal is to detect a high frequency component of the luminance signal which increases in proportion to the degree of focusing.

In the focus signal generation method of such a video device, a high pass filter (HPF) and a low pass filter (LPF) are conventionally used to detect a predetermined high frequency component. That is, a high pass filter for detecting high frequency components of the luminance signal and a low pass filter for removing noise were used in series. The detected high frequency component is converted into a digital signal and then integrated over a predetermined area of the field, thereby becoming a focus signal.

1 is a schematic block diagram showing a conventional focus signal generating circuit. As shown in FIG. 1, a conventional focus signal generating circuit includes a high pass filter (HPF) 101 for detecting a high frequency component of the luminance signal Y; A low pass filter (LPF) 102 for removing noise on the detected high frequency components; An analog to digital converter (ADC) 103 for converting an output signal from the low pass filter 102 into a digital signal; A digital integrator 104 for integrating the digital signal to output a focus signal AF; And an area selector 105 which generates a predetermined signal during a time when a predetermined effective area is scanned for each field, and controls the integration time of the digital integrator 104. The analog / digital converter 103 and the region selector 105 operate in synchronization with the clock signal CLK. In addition, the clock signal CLK and the horizontal synchronizing signal H _SYNC input to the area selector 105 are used to determine the scan time for the effective area. The vertical synchronizing signal V _SYNC is used to reset the area selector 105 and the digital integrator 104 field by field. The reset signal RESET output from the area selector 105 is a signal generated by the vertical synchronizing signal V _SYNC and resets the focus signal AF for each field. In addition, the area selection signal AS output from the area selector 105 is a signal for operating the digital integrator 104 only during the scan time for the effective area. The data valid signal DV output from the area selector 105 is a signal generated from the end of the valid area to the time at which the vertical synchronizing signal V _SYNC is generated. For example, an external circuit, for example, a lens driving circuit may generate the focus signal AF. This is the signal to be input.

The conventional focus signal generation circuit as described above has a problem in that the scale of the hardware increases due to the use of a high pass filter and a low pass filter.

The present invention has been made to solve the above problems, and an object thereof is to provide a method and a circuit for generating a focus signal without using a high pass filter and a low pass filter.

In order to achieve the above object, a focus signal generation method of an imaging apparatus according to the present invention includes:

A first step of converting a luminance signal of a video device into a digital signal,

A second step of obtaining an average value of the digital signal to remove noise of the luminance signal,

A third step of obtaining a change amount of the average value to detect a high frequency component of the luminance signal, and

And a fourth step of periodically accumulating the change amount in order to obtain the magnitude of the high frequency component and generating the result as a focus signal.

In addition, in order to achieve the above object, the focus signal generating circuit of the imaging apparatus according to the present invention,

Analog / digital conversion means for converting a luminance signal of a video device into a digital signal,

Digital signal processing means for obtaining an average value of the digital signals, accumulating the amount of change, and generating the result as a focus signal; and

And a region selecting means for generating a predetermined signal during the time when the predetermined effective region is scanned for each field and controlling the operation time of the signal processing means.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a schematic block diagram illustrating a focus signal generating circuit according to an exemplary embodiment of the present invention. As shown in FIG. 2, the focus signal generating circuit of the present embodiment calculates an average value of the analog / digital converter (ADC) 201 for converting the luminance signal Y into the digital luminance signal D, and accumulates the change amount. The digital signal processor (DSP) 202, which generates the result as a focus signal, and generates a predetermined signal during a time when a predetermined effective area is scanned for each field, thereby reducing the operation time of the digital signal processor 202. It has an area selector 203 to control.

In FIG. 2, the analog / digital converter 201, the digital signal processor 202, and the region selector 203 operate in synchronization with the clock signal CLK. In addition, the clock signal CLK and the horizontal synchronizing signal H _SYNC input to the region selector 203 are used to determine the scan time for the valid region. Meanwhile, the vertical synchronization signal V _SYNC is used to reset the area selector 203 and the digital signal processor 202 for each field. The region selection signal AS output from the region selector 203 is a signal that causes the digital signal processor 202 to operate only during the scan time for the effective region. The data valid signal DV output from the area selector 203 is a signal generated from the end of the valid region to the time at which the vertical synchronizing signal V _SYNC is generated. For example, an external circuit, for example, a lens driving circuit may generate the focus signal AF. This is the signal to be input.

The digital signal processor 202 obtains an average value of the digital luminance signal D input from the analog-to-digital converter 201, calculates a change amount of the average value, accumulates the change amount for each field, and generates a result as a focus signal. That is, the noise of the luminance signal Y is removed by obtaining the average value of the digital luminance signal D, the high frequency component of the luminance signal Y is detected by obtaining the change amount of the average value, and the change amount is accumulated for each field to generate the high frequency component. You can get the size of. Therefore, the focus signal generating circuit of this embodiment does not need a high pass filter and a low pass filter.

3 is a view showing a field screen for explaining the area selector of FIG. In FIG. 3, reference numeral 301 denotes a field screen, and 302 denotes a set valid area. The region selection signal AS output from the region selector 203 of FIG. 2 becomes high only while the effective region 302 as shown in FIG. 3 is scanned. Here, the region selector 203 of FIG. 2 counts the clock signal CLK of FIG. 2 to identify the points J and K of FIG. 3 and the horizontal synchronization signal H _SYNC of FIG. 2 to identify the points M and N of FIG. do.

4 is a block diagram showing the area selector of FIG. As shown in FIG. 4, the area selector according to the present embodiment generates a horizontal section signal AS _H in a high state during the time when the horizontal section of the effective region 302 of FIG. 3 is scanned. ; The vertical section signal AS _V in the high state is generated while the vertical section of the effective region 302 of FIG. 3 is scanned, and the data valid signal DV in the high state is generated from the end point of the scanning of the vertical section. And a vertical section selection circuit 402 and an AND gate 403 for AND-combining the output signals AS _H and AS _V of the horizontal section selection circuit 401 and the vertical section selection circuit 402 with each other. The horizontal section selection circuit 401 counts the input clock signal CLK so that the horizontal section signal AS _H is outputted high only during the time when the horizontal section of the effective region 302 of FIG. 3 is scanned. The horizontal synchronization signal H _SYNC input to the horizontal section selection circuit 401 performs a periodic reset function. The vertical section selection circuit 402 counts the input horizontal synchronizing circuit H _{YNC so} that the vertical section signal AS _V is output in a high state only during the time when the vertical section of the effective region 302 of FIG. 3 is scanned. In addition, the vertical section selection circuit 402 causes the data valid signal DV to go high from the time point when the scanning of the vertical section ends. The vertical synchronizing signal V _SYNC performs a periodic reset function of the vertical section selection circuit 402.

5 is a block diagram illustrating a horizontal section selection circuit of FIG. 4. As shown in FIG. 5, the horizontal section selection circuit according to the present embodiment includes a counter 501 that counts an input club signal CLK, and when the output of the counter 501 is a value J corresponding to a start point of the horizontal section. A first equivalent comparator 502 for outputting a signal in a high state only, and a signal for outputting a high state signal only when the output of the counter 501 is a value K corresponding to an end point of the horizontal section. When the output signals of the second equivalent comparator 503 and the first equivalent comparator 502 and the second equivalent comparator 503 are switched from the low state to the high state of the OR gate 504 and the OR gate 504, It has a D flip flip-flop 505 whose output state is reversed. Here, the horizontal synchronizing signal H _SYNC is input to the reset terminal RST of the counter 501 and the D flip-flop 505, and the clock signal CLK is input to the clock terminal CK of the counter 501. The output signal of the OR gate 504 is input to the clock terminal CK of the 505 flip-flop. The toggle function of the D flip-flop 505 is enabled by connecting the Q terminal and the D terminal. Instead of the D flip-flop 505, a T flip-flop may be used.

In FIG. 5, when the horizontal synchronizing signal H _SYNC is input, the counter 501 and the D flip-flop 505 are reset, so that the counter 501 counts the clock signal CLK from the reset point, and the horizontal section signal AS _H is in a low state. Becomes When the output of the counter 501 becomes the value J corresponding to the start point of the horizontal section, the first equivalent comparator 502 outputs a high state signal, so that the horizontal section signal AS _H is inverted to have a high state. do. When the output of the counter 501 reaches a value K corresponding to an end point of the horizontal section, the second equivalent comparator 503 outputs a high state signal, so that the horizontal section signal AS _H is inverted to a low state. Becomes Therefore, the horizontal section signal AS _H becomes high only during the time when the horizontal section of the effective region 302 of FIG. 3 is scanned.

6 is a block diagram illustrating a vertical section selection circuit of FIG. 4.

As shown in FIG. 6, the vertical section selection circuit according to the present embodiment has a counter 601 that counts an input horizontal synchronization signal H _SYNC, and when the output of the counter 601 is a value M corresponding to a start point of the vertical section. A first equivalent comparator 602 that outputs a signal of only a high state, and a second equivalent comparator 603 that outputs a signal of a high state only when the output of the counter 601 is a value N corresponding to an end point of the vertical section. OR gate 604 for OR coupling the output signals of the first equivalent comparator 602 and the second equivalent comparator 603 with each other, and when the output of the OR gate 604 is switched from a low state to a high state, The first D-type flip-flop 605 in which the output state is inverted, and the second D-type in which its output state is inverted when the output of the second equivalent comparator 603 transitions from a low state to a high state Equipped with flip-flop 606 . Here, the vertical synchronizing signal V _SYNC is input to the reset terminal RST of the counter 601, the first D-type flip-flop 605, and the second D-type flip-flop 606, and the horizontal synchronizing signal H _SYNC is input to the clock terminal CK of the counter 601. The output signal of the second equivalent comparator 603 is input to one terminal of the OR gate 604 and to the clock terminal CK of the second D flip-flop 606. The output signal of the OR gate 604 is input to the clock terminal CK of the D flip-flop 605. The toggle function of the D flip-flops 605 and 606 is enabled by connecting the Q terminal and the D terminal. Instead of the D flip-flops 605 and 606, a T flip-flop may be used.

When the vertical synchronizing signal V _SYNC is input in FIG. 6, the counter 601 and the D flip-flops 605 and 606 are reset, so that the counter 501 counts the horizontal synchronizing signal H _SYNC from the time of reset, and the vertical section signal AS _V is low. (Low) state. When the output of the counter 601 reaches a value M corresponding to the start point of the vertical section, the first equivalent comparator 602 outputs a high state signal, so that the vertical section signal AS _V is inverted to have a high state. do. When the output of the counter 601 reaches a value N corresponding to an end point of the vertical section, the second equivalent comparator 603 outputs a high signal, so that the vertical section signal AS _V is inverted to a low state. And the data valid signal DV is inverted to a high state. Therefore, the vertical interval signal AS _V goes high (High) state only during the time that the vertical section scan of the third-degree effective region 302, the data valid signal DV is the vertical synchronization signal V _SYNC from the time the scanning in the vertical interval with end It is high until the time when it is generated.

7 is a block diagram showing the digital signal processor of FIG. As shown in FIG. 7, the digital signal processor according to the present embodiment includes an average value calculator 701, 702, 703, 704 for calculating an average value of the input digital luminance signal D, and a change amount detector for detecting the change amount of the average value. 705, 706, and accumulating parts 707, 708 that accumulate the detected amount of change.

Here, the average value calculators 701, 702, 703, and 704 are latch parts 701 and 702 which sequentially store the input digital luminance signal D in accordance with a predetermined clock signal CLK. Signals Dn, D _n-1 ,... , A first adder 703 that sequentially adds D ₁ by a predetermined number n, and a divider 704 that divides the output signal Sn of the first adder 703 by the number n. The change amount detectors 705 and 706 may include a delay element 705 for delaying the output signal An of the divider 704 for one period of the clock signal CLK, and an output signal An of the divider 704 and an output of the delay element 705. A subtractor 706 for obtaining a difference from the signal A _n-1 .

In FIG. 7, since the latch portions 701 and 702 are n latches, the first adder 703 adds n digital luminance signals to output the result. When one clock signal CLK is generated, the input signals Dn, D _n-1 ,... Of the first adder 703 are generated. , D ₁ is moved by one position. That is, D _n-1 is replaced as the input signal Dn and a new input signal is replaced as D ₁ . Therefore, the output signal Sn of the first adder 703 represents the sum of n input signals including the new input signal D ₁ each time the clock signal CLK is generated. The divider 704 outputs the average value signal An by dividing the output signal Sn by n. Since the average value signal An is input to the subtractor 706 and the n + 1th latch 705, the subtractor 706 outputs the difference between the average value signal An and the output signal An-1 of the n + 1th latch 705 │An-A _n-1 │. do. The accumulators 707 and 708 are the second adder 707 and the n + 2 latch 708. The output signal of the n + 2 latch 708, that is, the focus signal AF is fed back to one input terminal IN ₁ of the second adder 707. As a result, a value obtained by sequentially accumulating the input signal | An-A _n-1 | of the other input terminal IN ₂ of the second adder 707 is output. Here, the AND gate 709 AND-couples the region selection signal AS and the clock signal CLK and inputs an output thereof to the n + 2 latch 708 so that the accumulators 707 and 708 operate only during the scan time of the valid region. .

As illustrated in FIG. 7, the digital signal processor 202 of FIG. 2 removes noise of the luminance signal Y by obtaining an average value of the digital luminance signal D, and obtains a high frequency component of the luminance signal Y by obtaining an amount of change of the average value. The magnitude of the high frequency component can be determined by accumulating the change amount by field. Therefore, the focus signal generating circuit of this embodiment does not need a high pass filter and a low pass filter.

As described above, according to the method and circuit for generating the focus signal of the imaging apparatus according to the present invention, since the high pass filter and the low pass filter are not used, the scale of the hardware can be reduced.

The present invention is not limited to the above embodiment, and its use and improvement are possible at the level of those skilled in the art.

Claims (9)

A first step of converting a luminance signal of a video device into a digital signal, a second step of obtaining an average value of the digital signal to remove noise of the luminance signal, and a change amount of the average value to detect a high frequency component of the luminance signal And a fourth step of periodically accumulating the amount of change in order to obtain the magnitude of the high frequency component, and generating a result as a focus signal. Analog / digital conversion means for converting a luminance signal of a video device into a digital signal, a digital signal processing means for obtaining an average value of the digital signal, accumulating the amount of change, and generating the result as a focus signal, and a predetermined effective area for each field And a region selecting means for generating a predetermined signal during this scanning time to control an operation time of the signal processing means. The horizontal section selecting circuit of claim 2, wherein the region selecting means comprises: a horizontal section selecting circuit which generates a horizontal section signal in a high state during a time in which the horizontal section of the effective region is scanned, and a time in which the vertical section of the valid region is scanned A vertical section selection circuit for generating a vertical section signal in a high state, and generating a data valid signal in a high state from a time point at which the scanning of the vertical section ends, and an output of the horizontal and vertical section selection circuits; And an AND gate for AND-combining signals to each other and outputting the focus signal generating circuit. 4. The circuit of claim 3, wherein the horizontal section selection circuit comprises: counting means for counting a predetermined clock signal, and outputting a signal in a high state only when an output of the counting section is a value corresponding to a start point of the horizontal section. First equivalent comparing means, second equivalent comparing means for outputting a signal in a high state only when the output of the counter is a value corresponding to an end point of the horizontal section, and output signals of the first and second equivalent comparing means. OR gates OR-coupled to each other, and a first toggle means in which its output state is inverted when the output of the OR gate is switched from a low state to a high state. Focus signal generation circuit of the video equipment. 4. The apparatus of claim 3, wherein the vertical section selecting circuit comprises: counting means for counting a horizontal synchronizing circuit and a first outputting signal of a high state only when an output of the counting section is a value corresponding to a start point of the vertical section; Equivalent comparison means, the second equivalent comparison means for outputting a signal in a high state only when the output of the counting unit is a value corresponding to the end point of the vertical section, and the output signals of the first and second equivalent comparison means OR gates to be OR coupled, when the output of the OR gate is switched from a low state to a high state, if its output state is inverted, a first toggle means, and the second equivalent comparison means And a second toggle means in which its output state is inverted when the output of the signal is switched from the low state to the high state. 3. The digital signal processing means according to claim 2, wherein the digital signal processing means includes an average value calculating means for calculating an average value of the digital signal, a change amount detecting means for detecting a change amount of the average value, and an accumulating means for accumulating the detected change amount. Focus signal generating circuit of a video device. The method of claim 6, wherein the average value calculating means comprises: a latch unit for sequentially storing the digital signal in accordance with a predetermined clock signal, an adder for sequentially adding each signal stored in the latch unit by a predetermined number, and the output of the adder. And a divider for dividing the signal by the number. 8. The apparatus of claim 7, wherein the change amount detecting means obtains a delay element for delaying the output signal of the divider for one period of the clock signal, and a difference between the output signal of the divider and the output signal of the delay element. A focus signal generation circuit of an image processor comprising a subtractor. 8. The digital signal processing means according to claim 7, characterized in that the digital signal processing means further includes an AND gate for AND combining the output signal from the area selection means and the clock signal, and controlling the operation of the accumulation means as an output thereof. Focus signal generation circuit of the video equipment.