KR100188022B1 - Etching rate measuring method of semiconductor film - Google Patents
Etching rate measuring method of semiconductor film Download PDFInfo
- Publication number
- KR100188022B1 KR100188022B1 KR1019960010641A KR19960010641A KR100188022B1 KR 100188022 B1 KR100188022 B1 KR 100188022B1 KR 1019960010641 A KR1019960010641 A KR 1019960010641A KR 19960010641 A KR19960010641 A KR 19960010641A KR 100188022 B1 KR100188022 B1 KR 100188022B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- etching
- semiconductor
- film quality
- etching rate
- Prior art date
Links
- 238000005530 etching Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 239000000470 constituent Substances 0.000 abstract description 6
- 238000011068 loading method Methods 0.000 abstract description 6
- 238000005259 measurement Methods 0.000 abstract description 4
- 239000012528 membrane Substances 0.000 abstract 2
- 238000007796 conventional method Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
본 발명은 반도체 소자의 제조시 각종 막질의 식각 정도를 간단한 방법으로 측정할 수 있도록 한 반도체 구성 막질의 식각률 측정 방법에 관한 것으로, 반도체 기판 상에 막질을 침적하는 단계; 상기 막질상에 포토레지스트를 침척하고 패턴을 형성하는 단계; 상기 포토레지스트 패턴의 개구부를 통하여 하부 막질을 선택적으로 식각하는 단계; 및, 상기 막질의 식각 부분과 식각되지 않은 부분의 두께를 각각 측정하여 막질의 식각률을 구하는 단계를 구비하여 이루어져 있다.The present invention relates to a method for measuring an etching rate of a semiconductor constituent film to measure the degree of etching of various film qualities in the manufacturing of a semiconductor device, the method comprising: depositing a film quality on a semiconductor substrate; Infiltrating the photoresist on the film and forming a pattern; Selectively etching the lower film quality through the opening of the photoresist pattern; And measuring the thicknesses of the etched portions and the unetched portions of the membranes, respectively, to obtain the etch rate of the membranes.
이 방법은 막질의 식각률을 2번의 반도체 웨이퍼 로딩에 의해 측정하였던 종래의 방법에 비해, 1번의 웨이퍼 로딩에 위해 식각률 측정을 가능케 함으로써 전반적인 반도체 제조 공정이 보다 간단해지게 되어, 본 발명을 적용하면 반도체 제조의 생산성 및 작업 효율을 향상시킬 수 있게 되는 것이다.This method simplifies the overall semiconductor fabrication process by enabling the etching rate measurement for one wafer loading, compared to the conventional method in which the film quality etch rate was measured by two semiconductor wafer loadings. It is possible to improve the productivity and work efficiency of manufacturing.
Description
제1도는 반도체 구성 막질의 종래 식각률 측정 순서를 보이는 공정도.1 is a process chart showing a conventional etching rate measurement procedure of the semiconductor constituent film quality.
제2도는 본 발명에 따른 막질의 식각률 측정 순서를 보이는 공정도.2 is a process chart showing the etching rate measurement procedure of the film quality according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 실리콘 기판 20 : 폴리실리콘막10 silicon substrate 20 polysilicon film
30 : 포토레지스트30: photoresist
본 발명은 반도체 구성 막질의 식각률 측정 방법에 관한 것으로서, 보다 상세하게는 반도체 소자의 제조 공정중 각종 막질의 식각 정도를 간단한 방법으로 측정할 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for measuring the etching rate of semiconductor constituent films, and more particularly, to a method capable of measuring the degree of etching of various films in a semiconductor device manufacturing process.
반도체 소자의 제조 공정에서 막질의 식각은 소자의 신뢰도를 좌우하는 중요한 공정이다. 따라서 막질의 식각 공정을 정확히 제어하기 위해 식각 공정 이전에 모니터링 웨이퍼를 사용하여 식각되는 정도를 사전에 점검하고, 이 모니터링 웨이퍼가 이상이 없는 경우에만 다음 공정, 즉 막질의 식각률을 구하는 공정을 진행하게 된다.In the semiconductor device manufacturing process, the etching of the film is an important process that determines the reliability of the device. Therefore, in order to precisely control the etching process of the film quality, the degree of etching using the monitoring wafer is checked in advance before the etching process, and when the monitoring wafer is intact, the next process, that is, the process of obtaining the film quality etching rate, is performed. do.
제1도를 참조하여 종래 기술을 설명한다. 먼저 (a),(b)도에 도시된 바와 같이 실리콘 기판(10)상에 침적된 폴리실리콘막(20)의 두께를 계측기로 측정하고, (c)도에서와 같이 상기 폴리실리콘막(20) 상부에 포토레지스트(30)를 도포한다. 그리고 (d),(e)도와 같이 포토레지스트(30)를 노광 및 현상하고, 이의 개구부를 통하여 하부 폴리실리콘막(20)을 선택적으로 식각한 다음 폴리실리콘막(20)의 식각된 부분의 두께를 측정한다.The prior art will be described with reference to FIG. First, as shown in (a) and (b), the thickness of the polysilicon film 20 deposited on the silicon substrate 10 is measured with a measuring instrument. As shown in (c), the polysilicon film 20 is measured. The photoresist 30 is coated on the top. And exposing and developing the photoresist 30 as shown in (d) and (e), selectively etching the lower polysilicon film 20 through the opening thereof, and then the thickness of the etched portion of the polysilicon film 20. Measure
즉, 폴리실리콘 막질의 식각률을 알아보기 위해 웨이퍼를 두 번에 걸쳐 로딩하여 각각 식각 전, 후의 막질 두께를 계측기로 측정하여 막질의 식각률을 계산하였다.That is, in order to determine the etch rate of the polysilicon film, the wafer was loaded twice, and the thickness of the film was measured by measuring the thickness of the film before and after etching, respectively.
그러나 이와 같이 막질의 식각 정도를 알아보기 위해 웨이퍼를 2번에 걸쳐 로딩하기 때문에 이는 반도체 제조 공정이 복잡하게 하고 또한 반도체 제조 시간을 연장시키는 요소로 작용하고 있는 실정이다.However, since the wafer is loaded twice in order to check the degree of etching of the film, the semiconductor manufacturing process is complicated and the semiconductor manufacturing time is extended.
따라서 본 발명은 상기 문제점을 해결하고자 한 것으로, 그 목적은 한번의 웨이퍼 로딩에 의해 식각 전, 후의 막질 두께를 측정하여 식각률을 구할 수 있도록 한 반도체 구성 막질의 식각률 측정 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above problems, and an object thereof is to provide an etching rate measuring method of a semiconductor constituent film so that the etching rate can be obtained by measuring the film thickness before and after etching by one wafer loading.
상기 본 발명의 목적을 달성하기 위한 반도체 구성 막질의 식각률 측정 방법은, 반도체 기판 상에 막질을 침적하는 단계; 상기 막질상에 포토레지스트를 침척하고 패턴을 형성하는 단계; 상기 포토레지스트 패턴의 개구부를 통하여 하부 막질을 선택적으로 식각하는 단계; 및, 상기 막질의 식각 부분과 식각되지 않은 부분의 두께를 각각 측정하여 막질의 식각률을 구하는 단계를 구비하여 이루어진 데에 그 특징이 있다.In order to achieve the object of the present invention, a method for measuring an etch rate of a semiconductor constituent film includes depositing a film on a semiconductor substrate; Infiltrating the photoresist on the film and forming a pattern; Selectively etching the lower film quality through the opening of the photoresist pattern; And measuring the thicknesses of the etched portions and the non-etched portions of the film quality to obtain the etch rate of the film quality, respectively.
이하, 실시예를 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to Examples.
제2도는 본 발명에 따른 반도체 구성 막질의 식각률 측정 방법을 설명하기 위한 공정 순서도이다.2 is a flowchart illustrating a method of measuring an etching rate of a semiconductor constituent film according to the present invention.
도면을 참조하면, 먼저 (a)도와 같이 실리콘 기판(10) 상부 전면에 폴리실리콘막(어떠한 막질이든 관계없다)(20)을 침적하고, (b)도와 같이 상기 폴리실리콘막(20) 상에 포토레지스트(30)를 도포한다.Referring to the drawings, first, a polysilicon film (regardless of film quality) 20 is deposited on the entire upper surface of the silicon substrate 10 as shown in (a), and on the polysilicon film 20 as shown in (b). The photoresist 30 is applied.
다음 (c)도와 같이 상기 포토레지스트(30)를 노광 및 현상하여 패턴을 형성하고, (d)도와 같이 포토레지스트 패턴의 개구부를 통하여 폴리실리콘막(20)을 선택적으로 식각한다.Next, as shown in (c), the photoresist 30 is exposed and developed to form a pattern, and as shown in (d), the polysilicon film 20 is selectively etched through the opening of the photoresist pattern.
다음 (e)도와 같이 폴리실리콘막(20)의 식각된 부분의 두께와 식각되지 않은 부분의 두께를 각각 측정하여 식각률을 구한다.Next, as shown in (e), the thickness of the etched portion and the unetched portion of the polysilicon film 20 are measured, respectively, to obtain an etch rate.
이와 같은 공정에 의해 반도체 소자의 공정 진행시 막질의 두께를 한 공정에서 측정하게 되면, 두께 측정에 의한 식각률 계산이 한 번의 웨이퍼 로딩에 의해 이루어지게 된다.When the thickness of the film quality is measured in one process by the above process, the etching rate calculation by the thickness measurement is performed by one wafer loading.
따라서, 종래에는 막질의 식각률을 2번의 반도체 웨이퍼 로딩에 의해 측정하였는데 반해, 본 발명은 1번의 웨이퍼 로딩에 의해 가능케 함으로써 전반적인 반도체 제조 공정이 보다 간단해지므로, 본 발명을 적용한다면 반도체 제조의 생산성 및 작업 효율을 향상시킬 수 있다.Therefore, while the etching rate of the film quality was conventionally measured by two semiconductor wafer loadings, the present invention makes the overall semiconductor manufacturing process simpler by enabling one wafer loading. Work efficiency can be improved.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960010641A KR100188022B1 (en) | 1996-04-09 | 1996-04-09 | Etching rate measuring method of semiconductor film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960010641A KR100188022B1 (en) | 1996-04-09 | 1996-04-09 | Etching rate measuring method of semiconductor film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970072161A KR970072161A (en) | 1997-11-07 |
| KR100188022B1 true KR100188022B1 (en) | 1999-06-01 |
Family
ID=19455340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960010641A KR100188022B1 (en) | 1996-04-09 | 1996-04-09 | Etching rate measuring method of semiconductor film |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100188022B1 (en) |
-
1996
- 1996-04-09 KR KR1019960010641A patent/KR100188022B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970072161A (en) | 1997-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100188022B1 (en) | Etching rate measuring method of semiconductor film | |
| US4717445A (en) | Etch bias monitoring technique | |
| JP2000294490A (en) | Semiconductor device and its manufacture | |
| JP2995749B2 (en) | Semiconductor device | |
| JPH07142572A (en) | Semiconductor device and manufacture thereof | |
| KR960010726B1 (en) | Method of forming pattern of semiconductor device | |
| KR960011469B1 (en) | Determining mehtod of photoresist film thickness | |
| KR19980067203A (en) | Spacer Formation Method of Semiconductor Device | |
| KR100476935B1 (en) | Method for control of critical dimensions during etch process | |
| KR950012542B1 (en) | Method of forming contact hole by double selective exposure of photomask | |
| KR100260243B1 (en) | Pressure sensor and method for fabricating thereof | |
| KR19980065656A (en) | Overlay keys unaffected by membrane quality asymmetry | |
| KR100192433B1 (en) | Method of measuring focus to fabricate semiconductor device | |
| JPH11150058A (en) | Method for measuring positional deviation and stress and x-ray mask | |
| KR970013155A (en) | Contact etching monitoring method for metal wiring | |
| JPH01256128A (en) | Dry etching method | |
| JP2002116556A (en) | Method for manufacturing semiconductor device | |
| JPH04256959A (en) | Method for measuring exposure accuracy | |
| JPH0141247B2 (en) | ||
| JPS59121836A (en) | Formation of positioning mark | |
| JPH0269934A (en) | Manufacture of semiconductor device | |
| JPS62177922A (en) | Manufacture of semiconductor device | |
| KR980012194A (en) | Selecting a dry etch for a semiconductor device | |
| JPH04116948A (en) | Method for measuring size of insulating layer through hole | |
| KR950033684A (en) | Method of selecting optimal thickness of photoresist by reflectance curve |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20061221 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |