KR0186041B1 - Code conversion circuit of radio transmission equipment - Google Patents

Abstract

The present invention relates to a code conversion circuit for converting a code for data communication between a multiplexer and an RF processor in a wireless transmission apparatus.

The present invention provides a deflip-flop 11 for inputting received 64Kbps data to the data stage D and outputting the retimed data X1 by a 256Kbps reference clock signal applied to the clock stage CLK. The retiming data X1 outputted from the output terminal Q of the flip-flop 11 is input to the data terminal D to delay the data X3 delayed by a 256 Kbps reference clock signal applied to the clock terminal CLK. A divider 14 for outputting a second flip-flop clock signal divided through the output terminal Q1 by counting according to the output flip-flop 12 and a 256 Kbps reference clock signal applied to the clock terminal CLK; And converts the data X3 outputted to the output terminal Q of the deflip-flop 12 and the second divided clock signal outputted to the output terminal Q1 of the divider 14 into 256Kbps positive data. The first code converting means constituted by the AND gate 13 and the clock terminal CLK. A divider 14 counting the reference clock signal of 256 Kbps and outputting the first divided clock signal divided through the output terminal Q0, and a first outputted to the output terminal Q0 of the divider 14. Data X5 inputted through the buffer 15 and data X1 outputted to the output terminal Q of the flip-flop 11 are inputted through the inverting element 16. Are inputted to the AND gate 17 for converting to 256Kbps negative data X7, and the 256Kbps negative data X7 outputted from the AND gate 17 to the data terminal D, respectively, and the clock terminal CLK. Second code conversion means comprising a de-flip flop 18 for delaying the reference clock signal of 256 Kbps and outputting the delayed data X8 to the output terminal Q, and the first and second code conversion means. Inserts the output of every 8th bit by inputting 256Kbps data transcoded by It consists of a vibration insertion means.

Description

Code conversion circuit of radio transmitter

1 is a code conversion circuit diagram according to the present invention,

2 is an operational waveform diagram of each part of FIG. 1.

* Explanation of symbols for main parts of the drawings

11, 12, 18, 23, 30, 31: flip-flop 14: divider

13, 17, 28, 29: Andgate 15, 21, 26: Buffer

16, 24, 27: inverting element 20: shift register

22: counter 25: J-K flip flop

The present invention relates to a code conversion circuit for converting a code for data communication between a multiplexer and an RF processor in a wireless transmission apparatus.

In general, a wireless communication device performs public affairs, administration, security, etc. for public purpose communication. Especially in the public communication, the microwave communication method is widely used due to the rapid spread of television and the increase of demand for long distance telephone lines.

The wireless transmission device for data communication using microwaves is a device with convenient operation system, easy maintenance, and various functions. It receives 6 DS3 (45Mbps) input signals and multiplexes them into 2 DS4 (140Mbps) microwave bands. There is a demand for a device capable of converting the data into a wireless transmission.

In order to implement the radio transmission apparatus as described above, an interface by code conversion between the multiplexing apparatus and the RF processing apparatus must be performed. In addition, since the code conversion must be performed by the code conversion rule of CCITT G.703, development of the code conversion circuit according to this rule is required.

Accordingly, an object of the present invention is to provide a code conversion circuit for interfacing between a multiplexing device and an RF processing device in a wireless transmission device.

Another wireless transmission apparatus of the present invention provides a code conversion circuit for converting a code of data transmitted between a multiplexer and an RF processor.

According to the present invention for achieving the above object, the received 64Kbps data input to the data stage (D) and outputs the re-timed data (X1) by the 256Kbps reference clock signal applied to the clock terminal (CLK) 256Kbps reference clock signal applied to the clock terminal CLK by inputting the flip-flop 11 and the retiming data X1 output from the output terminal Q of the deflip-flop 11 to the data terminal D. The second divided clock signal divided through the output terminal Q1 by counting by the de-flop 12 which outputs the data X3 delayed by the signal and the 256 Kbps reference clock signal applied to the clock terminal CLK. A divider 14 for outputting, a data X3 outputted to the output terminal Q of the deflip-flop 12, and a second divided clock signal outputted to the output terminal Q1 of the divider 14, respectively. A first code composed of an end gate 13 for input and converting into positive data of 256 Kbps A divider 14 for counting by a reference clock signal of 256 Kbps applied to the clock terminal CLK and outputting a first divided clock signal divided through an output terminal Q0, and the divider 14; The first divided clock signal outputted to the output terminal Q0 of the data X5 inputted through the buffer 15 and the data X1 outputted to the output terminal Q of the deflip-flop 11 are inverted elements ( 16, an AND gate 17 for inputting the data X6 input through the 16) to 256Kbps negative data X7, and a 256Kbps negative data X7 outputted from the AND gate 17, respectively. Second code conversion means comprising a flip-flop (18) inputted to (D) and delayed to a 256 Kbps reference clock signal applied to the clock terminal (CLK) to output the delayed data (X8) to the output terminal (Q); Inputting 256 Kbps data coded by the first and second code converting means, every eighth ratio; Each buyer illustration of inserting the output of the via migration is characterized in that it consists of inserting means.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a code conversion circuit diagram according to the present invention. The flip-flop 11 inputs received 64 Kbps data into the data stage D, and is generated from an oscillator (not shown) and applied to the clock stage CLK. The retimed data X1 is output by the reference clock signal of S1. The deflip-flop 12 is inputted from the oscillator (not shown) by inputting the retiming data X1 outputted to the output terminal Q of the deflip-flop 11 to the data terminal D, thereby generating a clock stage CLK. The delayed data X3 is output by delaying the second divided signal of the frequency divider 14 to be described later with a 256 Kbps reference clock signal. The divider 14 is divided by the output clocks Q0 and Q1 by the reference clock signal of 256 Kbps generated from the oscillator (not shown) and applied to the clock stage CLK. Output each signal. The AND gate 13 inputs the delay data X3 outputted to the output terminal Q of the deflip-flop 12 and the second divided clock signal outputted to the output terminal Q1 of the divider 14, respectively. The positive signal is extracted from the received 64Kbps data and converted into positive data (X4) of 256Kbps. The AND gate 17 includes data X5 in which the first divided clock signal output to the output terminal Q0 of the divider 14 is input through the buffer 15, and the output terminal of the deflip-flop 11 ( Each of the data X6 input through the inverting element 16 from Q) is input and the negative signal is extracted from the 64Kbps data received and converted into negative data X7 of 256Kbps. The deflip-flop 18 inputs 256Kbps negative data X7 outputted from the AND gate 17 to the data terminal D and receives the 256Kbps reference clock signal applied to the clock terminal CLK. The delayed 256Kbps negative data X8 is output to delay the timing with the positive data X4 of 256Kbps outputted from (13). The OR gate 19 logically combines the 256Kbps positive data X4 output from the AND gate 13 and the 256Kbps negative data X8 output to the output terminal Q of the deflip-flop 18. Output The shift register 20 shifts the data X9 output from the oragate 19 starting with the first data and shifts every 8th bit to output a 4-bit delay. The buffer 21 buffers and outputs 4-bit delayed data from the output terminal Q3 of the shift register 20. The counter 22 counts the second clock signal X2 output to the output terminal Q1 of the frequency divider 14 and outputs a carry signal, i.e., a bipolar vibration signal, every eighth bit. The deflip-flop 23 inputs a carry signal (bipolar vibration signal) of the counter 22 to the data terminal D, and outputs a 256 Kbps reference clock signal applied to the clock terminal CLK. Latch output to Q). The JK flip-flop 25 inputs the signal X12 whose signal outputted to the output terminal Q of the de-flop flop 23 is inverted through the inverting element 24 to the input terminals J and K. If the signal X12 inverted through 24 continues to be 1, the output is toggled every bit, and if the signal X12 inverted through the inverting element 24 continues to be 0, the previous state is maintained. . That is, the J-K flip-flop 25 may separate the data X10 buffered and output from the buffer 21 into 256Kbps positive data and 256Kbps negative data. The AND gate 28 inputs the buffered signal through the buffer 26 from the output terminal Q of the JK flip-flop 25 and logically multiplies the data buffered through the buffer 21 to 256 Kbps of positive data. Outputs (X14). The AND gate 29 inputs a signal inverted through the inverting element 27 from the output terminal Q of the JK flip-flop 25 and logically multiplies the data buffered and output through the buffer 21 to be 256 Kbps negative. The data X15 is output. The deflip-flop 30 inputs 256Kbps of positive data X14 outputted from the AND gate 28 to the data terminal D and retimes by a 256Kbps reference clock signal applied to the clock terminal CLK. Eliminate glitches The deflip-flop 31 inputs 256Kbps negative data X15 outputted from the AND gate 29 to the data terminal D and retimes the signal by a 256Kbps reference clock signal applied to the clock terminal CLK. Eliminate glitches

2 is an operational waveform diagram of each part of FIG. 1.

One preferred embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 described above.

Assuming that the received data input through the first input terminal P1 is the same data as the RD64K of FIG. 2, the flip-flop 11 for inputting the received data is 256 Kbps applied through the second input terminal P2. The retiming (or waveform shaping) is performed by the reference clock signal of < RTI ID = 0.0 >, < / RTI > and outputs retiming data X1 as shown in FIG. The deflip-flop 12, which inputs the retiming data X1 output to the output terminal Q of the deflip-flop 11 to the data terminal D, has a clock terminal CLK through a second input terminal P2. The delay data X3 as shown in FIG. 2 (X3) is output to the output terminal Q by being delayed by the reference clock signal of 256 Kbps applied to the output signal Q). The frequency divider 14, which inputs a 256Kbps reference clock signal generated from an oscillator (not shown) and applied to the clock stage CLK, is divided into two divisions as shown in FIG. 2 through the output terminals Q0 and Q1. The first divided clock signal and the second divided clock signal divided by 4 are output as shown in FIG. The AND gate 13 for inputting the delay data X3 outputted to the output terminal Q of the deflip-flop 12 and the second divided clock signal outputted to the output terminal Q1 of the divider 14 are respectively. Logically multiply and convert the signal of 1 of the received 64Kbps data into positive data (X4) of 256Kbps, which is a 1100 signal as shown in FIG. 2 (X4). Data X5 output from the output terminal Q0 of the divider 14 through the buffer 15 and data X6 output from the output terminal Q of the deflip-flop 14 through the inverting element 16. ), Each of the AND gates 17 is logically multiplied to convert a zero signal of the received 64 Kbps data into negative data X7 of 256 Kbps as a 1010 signal as shown in FIG. The deflip-flop 18 for inputting the negative 256 Kbps data X7 output from the AND gate 17 to the data terminal D is delayed by a 256 Kbps reference clock signal applied to the clock terminal CLK. Q) outputs delayed data X8 as shown in FIG. 2 (X8). The OR gate 19 for inputting the positive data X4 of 256 Kbps output from the AND gate 13 and the data X8 output to the output terminal Q of the deflip-flop 18 is logically summed in FIG. 2. Outputs the same data (X9) as (X9). The shift register 20 for inputting the data X9 output from the oragate 19 outputs a predetermined delay through the output terminal Q3 to insert a bias every 8th bit starting from the first data. do. The buffer 21 for inputting data with a predetermined delay output through the output terminal Q3 of the shift register 20 is buffered to output data X10 as shown in FIG. 2. The counter 22 which inputs the second clock signal X2 output to the output terminal Q1 of the divider 14 counts and carries a carry signal as shown in FIG. 2 (X11) every 8th bit, that is, bipolar vibration. Output the signal. The deflip-flop 23 which inputs the carry signal of the counter 22 to the data terminal D is latched to the output terminal Q by a 256 Kbps reference clock signal applied to the clock terminal CLK. JK flip-flop 25 for inputting the signal inverted through the inverting element 24 from the output (Q) of the flip-flop 23 to the input terminal (J, K) is a vibration as shown in FIG. The insertion signal X13 is output. The AND gate 28, which inputs the buffered output signal from the output terminal Q of the JK flip-flop 25 through the buffer 26, is logically multiplied by the data buffered and output through the buffer 21. As shown in (X14), the positive data (X14) of 256 Kbps in which the bias is inserted is output. The AND gate 29, which receives the inverted output signal from the output terminal Q of the JK flip-flop 25 through the inverting element 27, is logically multiplied with the data buffered and output through the buffer 21. As shown in (X15), the negative data (X15) of 256 Kbps with the bias insertion is output. The deflip-flop 30 for inputting the data output from the AND gate 28 to the data terminal D is retimed by a reference clock signal of 256 Kbps applied to the clock terminal CLK. As shown in FIG. 2, positive data (X16) of 256 Kbps from which glitches are removed is output. The deflip-flop 31 for inputting the data output from the AND gate 29 to the data terminal D is retimed by a reference clock signal of 256 Kbps applied to the clock terminal CLK. As shown in FIG. 2, 256Kbps of negative data (X17) from which glitches are removed is output. In the waveform diagram of (X14, X15) of FIG. 2, a denotes a glitch signal, which is removed through the flip-flop 30,31. In addition, b1 and b2 parts shown in the waveform diagrams of FIG. 2 (X16 and X17) indicate the insertion position of the vibration signal.

As described above, the code is converted and processed according to the code conversion rule of CCITT G.703 for data communication between the multiplexer and the RF processor in the wireless transmission apparatus, so that various services can be performed through rapid information transfer.

Claims (1)

A deflip-flop 11 for inputting the received 64 Kbps data to the data stage D and outputting the retimed data X1 by a 256-Kbps reference clock signal applied to the clock stage CLK; The retiming data X1 outputted from the output terminal Q of (11) is input to the data terminal D, and outputs the data X3 delayed by the 256 Kbps reference clock signal applied to the clock terminal CLK. A divider 14 for counting by a flip-flop 12 and a reference clock signal of 256 Kbps applied to the clock terminal CLK, and outputting a second divided clock signal divided through the output terminal Q1, and An AND gate for inputting the data X3 outputted to the output terminal Q of the flip-flop 12 and the second divided clock signal outputted to the output terminal Q1 of the divider 14 to be converted into positive data of 256 Kbps. First code converting means (13) and 256 Kbp applied to clock stage CLK; a divider 14 counting the reference clock signal of s and outputting a first divided clock signal divided through the output terminal Q0, and a first divider outputted to the output terminal Q0 of the divider 14; The data X5 inputted through the buffer 15 and the data X1 outputted to the output terminal Q of the deflip-flop 11 receive the data X6 inputted through the inverting element 16. An AND gate 17 for inputting and converting 256 Kbps negative data X7, respectively, and 256 Kbps negative data X7 outputted from the AND gate 17 are inputted to the data terminal D to receive a clock terminal CLK. Second flip-flop means comprising a flip-flop 18 which outputs the delayed data X8 to the output stage Q by delaying the reference clock signal of 256 Kbps and the first and second code converting means. Input the 256Kbps data transcoded by Code converting circuit of a radio transmission device, it characterized in that the control consists of illustration inserting means.