KR0184892B1 - Encoder pulse 1/n dividing circuit - Google Patents

Abstract

The present invention relates to a 1 / W division circuit of encoder pulses.

In general, the number of pulses of encoder of servo motor connected to servo driver is fixed according to each motor, and there are various problems caused when the value of this pulse is different from the pulse value required by the controller that controls the servomotor. Inevitably, according to the present invention, a circuit for dividing encoder pulses into 1 / N is used to control a motor with an encoder, thereby creating a 1 / N main circuit that allows the desired number of pulses to be used. Is the invention possible.

Description

Encoder pulse 1 / N division circuit

1 is an overall circuit diagram of the present invention

2 is a waveform diagram of the present invention

* Explanation of symbols for main parts of the drawings

10: encoder counter 20: up / down counter

30: comparator 50: operation switch

60: flip-flop 70 70 ': buffer

The present invention relates to the 1 / N division circuit of the encoder pulse, in particular, to control the encoder attached to the encoder to enable smooth control by making the 1 / N division circuit so that the desired number of pulses come out It is about a 1 / N division circuit of pulses.

In this case, the encoder pulse of the servomotor connected to the servo driver is fixed according to each motor.

When the value of this pulse (count / revolution: number of encoder pulses per revolution) and the value of the pulse required by the controller that controls this servomotor were different, the corresponding control was impossible.

Accordingly, an object of the present invention is to provide an encoder pulse 1 / n division circuit capable of dividing an encoder pulse at 1 / n according to a user's selection.

Hereinafter, with reference to the accompanying drawings will be described in detail the technical configuration and effect for achieving the object of the present invention.

Encoder counter 10 for receiving an encoder pulse and generating an up / down pulse, an up / down counter unit 20 for receiving an up / down pulse, and an operation switch for dividing a pulse according to a user's selection to 1 / N (50), the comparator 30 for comparing the N value through the operation switch 50 with the up / down counter 20 pulse, and the up / down for receiving the pulse output through the comparator and outputting the converted pulse. A counter 40, a buffer 70 and 70 'for reading the pulse value, and a flip / flop 60 are included.

Referring to the operation and effect of the present invention configured as described above in detail.

As shown in FIG. 1, the present invention accepts encoder signals A and B phases, generates a quadrupled pulse train and an up / down signal, and generates pulses whenever the number of pulses is equal to n. To make a 1 / n counter.

In other words, when the clock and encoder pulses A and B enter the encoder counter 10, a multiplication pulse and an up / down pulse are output.

In the encoder counter 10, the multiplying pulse and the up / down pulse may be configured as TTL instead of the HCTL 2020 encoder counter 10. However, since the scale of the circuit is increased, 2020 chips are used.

In addition, as shown in FIG. 2, the process from A, B, C .... P of FIG. 1 to A, B, C .... P of FIG. As you can see, the encoder pulse enters A and B, and the multiplication pulse and the up / down pulse appear in C and D.

In order to put this into the 74193 up / down counter unit 20, up / down pulses of E and F are generated using the up / down pulse D.

At this time, the original four cultivation pulses It is the same form as the up and down pulses (E, F) Changed to a pulse such as

When this pulse (E.F) enters the 74193 counter, the counter values (U35 3,2,6,7 and U36 3,2,6,7) change.

When the user uses the operation switch 50, the 74688 comparator 30 compares the counter value with the desired N / N value of 1 / N so that the P = Q (outputs U37 and 19) pulses become low when they are equal. do.

This pulse enters the U43 74193 up / down counter section 20 to produce the desired 1 / N pulse.

However, the explanation so far is when the counter is UP, and when it is DOWN, the following process is performed.

The setting value of the control switch 50 reads this data from the microcomputer using the buffer 70 'of 74245 of U40, and exports the 2'S complement value of this number to the buffer 70 of U39 74373. 74688 The comparator's value is set.

When the down pulse enters the 74193 up / down counter unit 20 of U35,36 and the counter value decreases and is equal to the setting value of the buffer 70 of U39, P = Q (output of U38 19) pulse appears and U43 up / down. The down counter 40 is to be counted down.

In addition, each time P = Q pulse is applied to the output port of the comparator 30, the U35, 36 up / down counter unit 20 is reset, and this process is repeated again.

That is, when the setting of the operation switch 5 is set to 0000 0011, 1111 1100 is set at the output portion of the buffer 70.

When encoder pulses are input from A and B of FIG. 1 from a motor, a quadrupling signal and an up / down signal are output from C and D, and two signals are separated from E and F. FIG.

At this time, the G signal is an enable signal of the comparator 30, but the multiplier signal C comes out until the comparator 30 is set in the up / down counter unit 20, disabling (disab1e), and then operating. Delay signal.

Then, when the comparator signal appears in H or I, it is immediately transmitted to the port LD of the up / down counter unit 20 and the counter value is set back to zero.

It is also passed to the up / down counter 40 to generate an encoder pulse again with this counter value. (M, N)

However, when the value of the counter U43 (3, 2) changes at the same time, a malfunction signal is generated at the NOR gates 7486 and U44, and it is completely converted through the flip-flop (6) to produce a waveform. (O, P)

To this end, the flip-flop 6 is delayed to generate the clock of the flip flop.

In conclusion, this circuit has the ability to divide encoder pulses up to n = 127.

As described above, in the present invention, the number of pulses of the encoder of the servo motor connected to the servo driver is fixed according to each motor, and when the value of the pulse and the value of the pulse required by the controller controlling the servo motor are different. By using this circuit, the user can generate the desired encoder pulse.

Claims (1)

The encoder counter 10 that receives an encoder pulse and generates an up / down pulse 4 times, the up / down counter unit 20 that receives up / down pulses, and the up / down pulses and the pulses of the divided N values are compared. A comparator 30 to operate, an operation switch 50 for dividing a pulse according to a user's selection at 1 / n, an up / down counter 40 for outputting the divided pulse, a buffer 70, 70 'and a flip -1 / N frequency division circuit of the encoder pulse, characterized in that combined with the flop (60) to divide the pulse value according to the motor control to 1 / N.