KR0182071B1 - Structure for preventing moisture from entering into bga semiconductor package - Google Patents
Structure for preventing moisture from entering into bga semiconductor package Download PDFInfo
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- KR0182071B1 KR0182071B1 KR1019950054766A KR19950054766A KR0182071B1 KR 0182071 B1 KR0182071 B1 KR 0182071B1 KR 1019950054766 A KR1019950054766 A KR 1019950054766A KR 19950054766 A KR19950054766 A KR 19950054766A KR 0182071 B1 KR0182071 B1 KR 0182071B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
본 발명은 BGA 반도체 패키지의 습기(Moisture)침투 방지구조에 관한 것으로, PCB기판의 내부에 습기침투 방지판을 내장함으로서, 반도체 패키지 내부로 침투되는 습기를 방지하여 계면박리 및 크랙을 방지하여 패키지의 성능을 향상시킴은 물론, 상기 습기침투 방지판에 의해 반도체 칩의 회로 동작시 발생되는 열을 효율적으로 방출시킬수 있도록 된 BGA 반도체 패키지의 습기침투 방지구조이다.The present invention relates to a moisture penetration prevention structure of the BGA semiconductor package, by embedding the moisture penetration prevention plate inside the PCB substrate, to prevent moisture penetrating into the semiconductor package to prevent interfacial peeling and cracks of the package The moisture permeation prevention structure of the BGA semiconductor package, which improves the performance and is capable of efficiently dissipating heat generated during circuit operation of the semiconductor chip by the moisture penetration prevention plate.
Description
제1도는 종래의 BAG 반도체 패키지 구조를 나타낸 단면도.1 is a cross-sectional view showing a conventional BAG semiconductor package structure.
제2도는 본 발명의 BAG 반도체 패키지 구조를 나탄낸 단면도.2 is a cross-sectional view showing the BAG semiconductor package structure of the present invention.
제3도의 (a)(b)는 제2도의 A부 확대도 및 실시예.(A) and (b) of FIG. 3 are enlarged views of section A and the embodiment of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 반도체 칩 11 : 와이어10: semiconductor chip 11: wire
12 : 에폭시 13 : 컴파운드12: epoxy 13: compound
20 : PCB기판 21 : 관통슬롯20: PCB board 21: through slot
22 : 솔더마스크 23 : 본드 핑거22: solder mask 23: bond finger
30 : 솔더볼 40 : 습기침투 방지판30: solder ball 40: moisture penetration prevention plate
본 발명은 BGA 반도체 패키지의 습기(Moisture)침투 방지구조에 관한 것으로, 더욱 상세하게는 BGA 반도체 패키지의 반도체 칩이 부착되는 PCB기판의 내부에 습기침투 방지판을 내장함으로써, 반도체 패키지 내부로 침투되는 습기를 방지하여 계면박리 및 크랙을 방지할 수 있어 패키지의 성능을 향상시킴은 물론, 상기 습기침투 방지판에 의해 반도체 칩의 회로 동작시 발생되는 열을 효율적으로 방출시킬수 있도록 된 BGA 반도체 패키지의 습기침투 방지구조에 관한 것이다.The present invention relates to a moisture penetration prevention structure of the BGA semiconductor package, and more particularly, by penetrating into the semiconductor package by embedding the moisture penetration prevention plate inside the PCB substrate to which the semiconductor chip of the BGA semiconductor package is attached. Moisture in the BGA semiconductor package can prevent moisture from interfacial peeling and cracks to improve the package performance, as well as efficiently dissipate heat generated during circuit operation of the semiconductor chip by the moisture barrier plate. It relates to a penetration prevention structure.
일반적으로 BAG(Ball Grid Array : 볼 그리드 어레이) 반도체 패키지는 제1도에 도시된 바와같이 PCB기판(20)의 저면으로는 다수의 솔더볼(30)이 부착되어 있으며, 상기 PCB기판(20)의 상태에는 반도체 칩(10)이 에폭시(12) 등의 접착수단에 의해 접착되어 있고, 이 반도체 칩(10)은 신호 전달을 위하여 와이어(11)로 PCB기판(20)의 상면에 형성된 본드 핑거(23 ; Bond Finger)에 본딩되며, 상기 반도체 칩(10) 및 그 외의 주변 구성품을 외부로 부터 보호하기 위하여 컴파운드(13)로 몰딩된 구조로 되어있다.In general, a ball grid array (BAG) semiconductor package has a plurality of solder balls 30 attached to the bottom of the PCB substrate 20, as shown in FIG. In the state, the semiconductor chip 10 is bonded by an adhesive means such as epoxy 12. The semiconductor chip 10 is a bond finger formed on the upper surface of the PCB substrate 20 by the wire 11 for signal transmission. 23 is bonded to the bond finger, and has a structure molded into the compound 13 to protect the semiconductor chip 10 and other peripheral components from the outside.
그러나, 이러한 BGA 반도체 패키지는 PCB기판(20) 저면에 부착된 솔더볼(30)을 입출력 단자로 사용하며, 그 솔더볼(30)의 핀(pin)수가 대부분이 200개가 넘는 다핀으로서, 그 사용되어지는 용도로는 컴퓨터, 통신기기 등에 주로 사용되어져 고속성능을 요구하게 된다.However, such a BGA semiconductor package uses solder balls 30 attached to the bottom surface of the PCB substrate 20 as input / output terminals, and the number of pins of the solder balls 30 is more than 200. It is mainly used for computers, communication devices, etc., and demands high speed performance.
따라서, 반도체 칩(10) 동작중에는 많은 열이 발생되고, 이러한 열을 외부로 방출하게 되는데, 이때 열을 효율적으로 방출시키지 못하면 반도체 칩(10)에서 발생된 열에 의해 반도체 칩(10)의 온도가 상승되어 그 성능 및 기능이 저하된다.Therefore, a large amount of heat is generated during operation of the semiconductor chip 10, and the heat is emitted to the outside. If the heat cannot be efficiently released, the temperature of the semiconductor chip 10 is increased by the heat generated by the semiconductor chip 10. Rises and degrades its performance and functionality.
그러나 종래의 BAG 반도체 패키지는 반도체 칩(10)의 동작중 발생되는 열을 방출하기 위하여 단순히 PCB기판(20)에 관통슬롯(21)을 다수 형성하여 즉, 반도체 칩(10)이 부착되는 부위 저면의 PCB기판(20)에 열방출용 관통슬롯(21)을 형성하여 열을 방출 시켰던 바, 이러한 종래의 열방출 구조로는 고속성능을 발휘하는 반도체 칩(10)의 열을 전부 외부로 방출시키지 못하게 되어 패키지의 성능이 저하되고, 수명이 단축되는 등의 문제점을 내포하고 있는 것이다.However, in the conventional BAG semiconductor package, a plurality of through slots 21 are simply formed on the PCB 20 to dissipate heat generated during the operation of the semiconductor chip 10, that is, the bottom of the portion where the semiconductor chip 10 is attached. The heat dissipation through-slot 21 was formed on the PCB substrate 20 to release heat. In the conventional heat dissipation structure, the heat of the semiconductor chip 10 exhibiting high speed performance is not discharged to the outside. This impairs the package's performance and shortens its lifespan.
뿐만 아니라, 반도체 패키지의 제조공정에서 발생되는 고온(대략 200℃ 정도)에 의해 외부의 습기가 패키지 내부로 침투하게 되어 계면박리 및 크랙을 발생시키는데, 이때 상기 관통슬롯(21)은 습기침투의 주경로가 되기 때문에 이 관통슬롯(21)에 슬더마스크(22)등으로 충진하여 습기침투를 예방하고 있으나, 이와같이 솔더마스크(22)로 관통슬롯(21)을 충진한다 하더라도 여전히 이 부분으로 습기의 침투가 이루어진다.In addition, due to the high temperature (approximately 200 ° C.) generated in the manufacturing process of the semiconductor package, external moisture penetrates into the package, thereby causing interfacial peeling and cracking. As this is a path, the penetration slot 21 is filled with a sled mask 22 to prevent moisture penetration. However, even though the penetration slot 21 is filled with the solder mask 22 in this way, moisture still penetrates into this portion. Is done.
이와같이 반도체 패키지에 습기가 침투하게 되면 계면박리 및 크랙의 발생 요인이 되어 패키지의 신뢰성 테스트에서 불량으로 처리되어 생산성을 저하시키는 등의 문제점이 있었던 것이다.As such, when moisture penetrates into the semiconductor package, it becomes a factor of interfacial peeling and cracking, which is treated as a defect in the reliability test of the package, thereby lowering productivity.
따라서, 본 발명은 이와같은 문제점을 해소하기 위하여 발명된 것으로, BAG 반도체 패키지 내의 반도체 칩의 회로 동작시 발생되는 열을 외부로 보다 효율적으로 방출시킴은 물론, 패키지이 제조공정시 외부의 습기가 패키지 내부로 침투하는 것을 효과적으로 방지하여 패키지의 신뢰성 및 성능을 향상시킬수 있는 BAG 반도체 패키지의 습기(Moisture)침투 방지구조를 제공함에 그 목적이 있다.Accordingly, the present invention has been invented to solve such a problem, and the heat generated during the circuit operation of the semiconductor chip in the BAG semiconductor package is more efficiently discharged to the outside, as well as the moisture inside the package during the manufacturing process. The purpose of the present invention is to provide a moisture permeation prevention structure of the BAG semiconductor package, which can effectively prevent penetration into the package, thereby improving the reliability and performance of the package.
이러한 본 발명의 목적을 달성하기 위해서는 반도체 칩이 상부에 실장되는 PCB기판과, 상기 반도체 칩 상에 구비된 칩패드와 PCB기판을 연결하는 다수의 와이어와, 상기 PCB기판의 저면에 부착되어 신호를 외부로 인출하는 다수의 솔더볼과, 상기 반도체 칩과 그 외의 구성부품을 보호하기 위해 반도체 칩 외부에 몰딩한 컴파운드로 구성된 BAG 반도체 패키지에 있어서, 상기 PCB기판의 내부에 습기침투 방지판을 내장한 것을 특징으로 하는 BAG 반도체 패키지의 습기(Moisture)침투 방지구조에 의해 가능하다.In order to achieve the object of the present invention, a semiconductor chip is mounted on the PCB substrate, a plurality of wires connecting the chip pad and the PCB substrate provided on the semiconductor chip, and is attached to the bottom surface of the PCB substrate to signal A BAG semiconductor package including a plurality of solder balls drawn out to the outside and a compound molded to the outside of the semiconductor chip to protect the semiconductor chip and other components, wherein a moisture permeation prevention plate is embedded in the PCB substrate. Characterized by the moisture penetration prevention structure of the BAG semiconductor package.
즉 PCB기판의 내부에 내장된 습기침투 방지판은 열전달이 양호한 구리(Cu) 또는 구리합금을 사용하여 습기침투를 방지함은 물론, 패키지의 열방출 효율을 극대화 시키도록 된 것이다.That is, the moisture permeation prevention plate embedded in the PCB substrate is used to prevent moisture penetration by using copper (Cu) or copper alloy having good heat transfer, and to maximize the heat dissipation efficiency of the package.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도는 반 발명의 BAG 반도체 패키지 구조를 나타낸 단면도로서, PCB기판(20)의 저면에는 다수의 솔더볼(30)이 부착되어 있으며, 상기 PCB기판(20)의 상면 중심부에는 반도체 칩(10)이 에폭시(12) 등의 접착수단에 의해 부착되어 있고, 상기 반도체 칩(10)과 그 외의 구성부품을 보호하기 위해 반도체 칩(10)의 외부에는 컴파운드(13)로 몰딩되어 있으며, 상기 반도체 칩(10)이 부착된 부위의 PCB기판(20)에는 열방출을 목적으로 다수개의 관통슬롯(21)이 형성된 BAG 반도체 패키지의 구성에 있어서, 상기 PCB기판(20)의 반도체 칩(10)이 장착되는 부위의 중간부에는 습기침투 방지판(40)이 내장되어 열방출의 효과를 극대화 시킴은 물론, 패키지 제조시 상기 습기침투 방지판(40)에 의해 외부의 습기가 침투되는 것을 방지한 구조이다.2 is a cross-sectional view illustrating a semi-invented BAG semiconductor package structure, in which a plurality of solder balls 30 are attached to a bottom surface of a PCB substrate 20, and a semiconductor chip 10 is formed at a center of an upper surface of the PCB substrate 20. It is attached by an adhesive means such as epoxy 12, and is molded with a compound 13 on the outside of the semiconductor chip 10 to protect the semiconductor chip 10 and other components, and the semiconductor chip ( 10) In the configuration of the BAG semiconductor package formed with a plurality of through slots 21 for the purpose of heat dissipation in the PCB substrate 20 of the portion, the semiconductor chip 10 of the PCB substrate 20 is mounted Moisture penetration prevention plate 40 is built in the middle portion of the site to maximize the effect of the heat release, as well as to prevent the moisture from penetrating the outside by the moisture penetration prevention plate 40 during the manufacture of the package.
상기 PCB기판(20)의 중간부에 내장된 습기침투 방지판(40)은 열전달이 양호한 구리(Cu) 또는 구리합금을 사용하는 것이 바람직하며, 이러한 습기침투 방지판(40)은 PCB기판(20)에 형성된 관통슬롯(21)의 중앙을 가로지르도록 내장하여 관통슬롯(21)을 상·하로 분리시키고, 관통슬롯(21)의 내측벽에는 구리(Cu) 도금을 하여 습기침투 방지판(40)과 연결시키면, 열방출의 효율을 극대화 시킬수 있으며, 상기 관통슬롯(21)의 내부에는 솔더마스크를 충진시켜 종래의 관통슬롯(21) 보다 양호한 열방출 효과를 얻을수 있는 것이다.The moisture permeation prevention plate 40 embedded in the middle portion of the PCB substrate 20 is preferably made of copper (Cu) or copper alloy with good heat transfer, and the moisture penetration prevention plate 40 is a PCB substrate 20 The through slots 21 are formed so as to cross the center of the through slots 21 formed in the upper and lower parts, and the inside slots of the through slots 21 are coated with copper (Cu) to prevent moisture penetration plate 40. ), The heat dissipation efficiency can be maximized, and a solder mask is filled in the through slot 21 to obtain a better heat dissipation effect than the conventional through slot 21.
이와같이 습기침투 방지판(40)에 의해 상·하로 분리된 관통슬롯(21)은 제3도의 (a)에 도시된 바와같이 상·하의 관통슬롯(21)을 서로 대응하게 일직선상에 형성할수 있으며, 제3도의 (b)에 도시된 바와같이 상·하의 관통슬롯(21)을 서로 어긋나게 형성하여도 된다.As described above, the through slots 21 separated up and down by the moisture permeation preventing plate 40 may form upper and lower through slots 21 in a straight line corresponding to each other as shown in FIG. As shown in Fig. 3B, the upper and lower through slots 21 may be formed to be offset from each other.
또한, 상기 관통슬롯(21)은 PCB기판(20)의 상면에 형성된 본드 핑거(23) 보다 안쪽에 위치되도록 내장하며, 반도체 칩(10)의 크기보다는 크게 형성하는 것이 바람직하다.In addition, the through slot 21 is embedded to be located inside the bond finger 23 formed on the upper surface of the PCB substrate 20, it is preferable to form larger than the size of the semiconductor chip (10).
이와같이 습기침투 방지판(40)이 내장된 PCB기판(20)을 BGA 반도체 패키지에 적용시키면 습기침투의 양을 상당히 줄일 수 있는 것으로, 225핀의 BGA 반도체 패키지를 온도: 30℃, 습도: 60%의 조건하에서 192시간 동안 노출시켰을 경우 습기의 침투량이 종래의 BGA 반도체 패키지는 0.25wt% 이상이었으나, 습기침투 방지판(40)이 내장된 PCB기판(20)을 사용한 본 발명의 BGA 반도체 패키지는 0,2wt% 이하로 급격히 줄었음을 알수 있었다.Applying the PCB 20 with the moisture permeation prevention plate 40 to the BGA semiconductor package can significantly reduce the amount of moisture penetration. The 225-pin BGA semiconductor package has a temperature of 30 ° C. and a humidity of 60%. The moisture permeation amount of the conventional BGA semiconductor package was 0.25wt% or more when exposed for 192 hours under the condition of, but the BGA semiconductor package of the present invention using the PCB substrate 20 having the moisture permeation preventing plate 40 therein was 0. It was found that the sharp decrease to less than 2wt%.
이와같은 결과는 상기 습기침투 방지판(40)이 습기의 침투경로를 차단하고 있음을 알수 있다. 또한 PCB기판(20)의 중간부에 반도체 칩(10) 보다 큰 습기침투 방지판(40)을 내장하였을 경우에는 반도체 칩(10)의 회로 동작시 발생되는 열의 60 ~ 70% 정도가 반도체 칩(10)의 저면으로 방출되므로, 상기 습기침투 방지판(40)에 의해 열방출의 효과를 극대화 시킬수 있다.As a result, it can be seen that the moisture barrier plate 40 is blocking the penetration path of moisture. In addition, when the moisture permeation prevention plate 40 larger than the semiconductor chip 10 is embedded in the middle of the PCB 20, about 60 to 70% of the heat generated during the circuit operation of the semiconductor chip 10 is a semiconductor chip ( Since it is discharged to the bottom of 10, it is possible to maximize the effect of heat dissipation by the moisture barrier plate 40.
이상의 설명에서 알수 있듯이 본 발명의 BGA 반도체 패키지의 습기침투 방지구조에 의하면, PCB기판의 중간부에 습기침투 방지판을 내장하여 패키지 제조시 습기의 침투를 방지하여 계면박리 및 크랙을 방지하는 것은 물론, 반도체 칩의 회로 동작시 발생되는 열을 효율적으로 방출함으로서 패키지의 성능을 향상시키고, 수명을 연장시킬수 있는 등의 효과가 있다.As can be seen from the above description, according to the moisture permeation prevention structure of the BGA semiconductor package of the present invention, the moisture permeation prevention plate is built in the middle part of the PCB substrate to prevent moisture infiltration during the package manufacturing to prevent interfacial peeling and cracking, as well as By efficiently dissipating the heat generated during the circuit operation of the semiconductor chip, the performance of the package can be improved and the life can be extended.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950054766A KR0182071B1 (en) | 1995-12-22 | 1995-12-22 | Structure for preventing moisture from entering into bga semiconductor package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950054766A KR0182071B1 (en) | 1995-12-22 | 1995-12-22 | Structure for preventing moisture from entering into bga semiconductor package |
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| Publication Number | Publication Date |
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| KR970053664A KR970053664A (en) | 1997-07-31 |
| KR0182071B1 true KR0182071B1 (en) | 1999-03-20 |
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| KR100533276B1 (en) * | 1999-02-26 | 2005-12-05 | 엘지전자 주식회사 | Manufacturing method of PCB and PCB thereby |
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