KR0180790B1 - Apparatus for interfacing data output in the optical disc motoring recording apparatus - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A data output interface device of an optical disk drive recording apparatus.

2. Technical problem to be solved by the invention

The present invention provides a data output interface device capable of removing data in error and efficiently performing data transmission.

3. Summary of Solution to Invention

A data output interface apparatus of an optical disk drive recording apparatus having signal processing means for decoding and outputting a signal reproduced from an optical disk surface, comprising: memory means for storing data input from said signal processing means, and data input from a receiving end; A glitch removal circuit for removing the glitch component included in the request signal, and accessing the storage means in response to the glitch-free transmission request signal, and logically calculating an error bit between the data of a predetermined unit and the data interval obtained as a result of the access. An error generation data elimination circuit for outputting data in the generated data section in a null state, and generating a byte clock for synchronizing parallel conversion of the data in synchronization with a predetermined reference clock and the reference clock; With the output data of the removal circuit Characterized in that it comprises an output means for outputting.

4. Important uses of the invention

It can be important for mini disc players.

Description

Data output interface device of optical disk drive recorder

1 is a block diagram of a conventional data output interface device.

2 is a timing diagram according to FIG.

3 is a block diagram of a data output interface device according to an embodiment of the present invention.

4 is a timing diagram according to FIG. 3;

5 is a glitch elimination circuit diagram embedded in the output interface unit 200 of the third diagram.

6 is an operation timing diagram of the glitch elimination circuit shown in FIG.

FIG. 7 is a circuit diagram showing error generation data embedded in the output interface unit 200 of the third diagram.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk drive recording apparatus, and more particularly, to a data output interface apparatus for outputting data reproduced from an optical disk surface in response to a transmission request signal.

In general, a recordable optical disc drive recording apparatus includes a mini disc player, and the like. The configuration and operation example of the optical disc drive recording apparatus are described in Korean Patent Application No. 94-2311 filed by the applicant of the present application. It is started.

The optical disk drive recording apparatus includes a memory for outputting data by decoding a signal read out from a disk, which is a recording medium, through a signal processing means such as an EFM decoder (Eight to Fourteen Modulation decoder, not shown). It includes a data output interface device for outputting and processing stored data. Such a conventional data output interface device and related configuration are shown in FIG. 1, and the conventional data output interface device is disclosed in detail in Korean Patent Application No. 94-2311. In general, a mini disc player transmits 212 bytes serially in one data transfer request. The data transfer timing is shown in FIG.

In FIG. 2, the waveform (a) is a bit clock output from the output interface unit 20 to the transmission request and data processing unit 30, and (b) the waveform is output from the transmission request and data processing unit 30. (C) the waveform is the data transmitted from the output interface unit 20 to the transmission request and data processing unit 30, and (c) is a low active transmission request signal input to the interface unit 20, d) The waveform is a byte clock output from the output interface unit 20 to the transmission request and the data processing unit 30, and is a sync pulse signal corresponding to one byte of the transmitted data, and (e) the waveform is the transmitted data. Error signal indicating whether an error occurs. The timing diagram shown in FIG. 2 shows transmission timing for one word of data. In general, a mini disc player needs to transmit 212 bytes, and thus the timing operation of FIG. Should be.

Hereinafter, the operation of the conventional data output interface device will be briefly described with reference to FIGS. 1 and 2.

First, when the transmission request signal (b) is input to the output interface unit 20, the output interface unit 20 reads out the data (c) from the memory 10 and sends bytes to the transmission request and data processing unit (30). Serial transmission in units, and also outputs the bit clock (a) to the transmission request and the data processing unit (30). At this time, the frequency of the bit clock (a) is about 5.65MHz. On the other hand, the output interface unit 20 reads an error signal (e) indicating the presence or absence of an error state of the data (c) to be transmitted from the memory (10) 1 during the 1-byte period of the data (c) to be transmitted The transmission request and the data processing unit 30 are transmitted in bit units. That is, the error signal e indicates that there is an error in one byte of transmission data c when it is high. Thereafter, when the transmission request signal b becomes high at the falling edge of the second period of the byte clock d, data transmission of one word is completed, and the above-described operation is repeated 106 times to complete data transmission of 212 bytes.

However, the above-described data output interface apparatus has a problem in that, despite receiving an error signal, the data having an error is transmitted to the transmission request and the data processor 30. In addition, the above-described data output interface device has a disadvantage in that a normal data transfer operation cannot be performed when glitches occur in the transmission request signal.

Accordingly, an object of the present invention is to provide a data output interface device capable of removing data in error and efficiently performing data transmission.

Another object of the present invention is to provide a data output interface device capable of achieving a normal data transfer operation even when an error of a transfer request signal occurs.

In order to achieve the above object, the present invention provides a data output interface device of an optical disk drive recording apparatus having signal processing means for decoding and outputting a signal reproduced from an optical disk surface, wherein the data input from the signal processing means is stored. A glitch removing circuit for removing the glitch component contained in the data transmission request signal inputted from the receiving end, a predetermined unit of data obtained by accessing the storage means in response to the glitch removal transmission request signal and the result; An error generation data elimination circuit for logically operating an error bit of a data section and outputting data in an error-producing data section in a null state, and synchronizing parallel conversion of the data in synchronization with a predetermined reference clock and the reference clock. Generate a byte clock for the error And it characterized in that it consists of an output means for outputting with the output data of the data removal circuit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a data output interface device according to a preferred embodiment of the present invention. The memory 10 stores data input from signal processing means (e.g., an EFM decoder) included in the optical disk drive recording apparatus. And outputting address data to the memory 10 in response to an input of a transmission request signal, receiving and outputting data accessed by the address data, and transmitting a bit clock as a reference clock. An output interface unit 200 for generating and outputting a byte clock for synchronizing the signal, and generating and outputting the transmission request signal to receive the data, the bit clock, and the byte clock and process the data. It consists of a processing part 30.

In addition, the output interface unit 200 performs an operation of accessing and transmitting data stored in the memory 10 in response to the transmission request signal. In addition, the data transmitted from the output interface unit 200 is extended by a predetermined algorithm in the transmission request and the data processing unit 30. At this time, the calculation unit of the transfer request and data processing unit 30 is 212 bytes. That is, the memory 10 stores data in units of 212 bytes, and outputs 212 bytes only when a transmission request is made through the output interface unit 200. The memory 10 stores error bits for each bit indicating whether or not the 212-byte data is in error. Since the data having an error is received by the receiving end, that is, the transmission request and the data processor 30, the memory bit is not used. In the present invention, the data in which the error is confirmed is converted to a specific value (for example, 0) and transmitted, but the error signal is not transmitted.

4 is a timing diagram according to FIG. 3, wherein the waveform (4a) of FIG. 4 represents a bit clock which is a reference clock of the output interface unit 200, and (4b) the waveform represents the transmission request and data processing unit ( 30), the waveform (4c) represents the data transmitted serially from the output interface unit 200, and the waveform (4d) represents the byte clock generated and output from the output interface unit 200. .

FIG. 5 illustrates a glitch elimination circuit diagram embedded in the output interface unit 200 of the third diagram. The glitch elimination circuit shown in FIG. 5 includes a 1D flip-flop 210 which latches the transfer request signal input from the transfer request and data processor 30 in synchronization with a bit clock, and receives the bit clock and inverts the output. An inverter 220 and a second D flip-flop 230 for latching and outputting the output signal of the first D flip-flop 210 in response to the inverted bit clock from the inverter 220.

6 is an operation timing diagram according to the configuration of FIG. 5, wherein the waveform (6a) of FIG. 6 represents a transmission request signal input to the first D flip-flop 210, and the (6b) waveform indicates the bit clock. The waveform (6c) represents the output signal of the second D flip-flop 230.

FIG. 7 is a circuit diagram illustrating an error occurrence data removal circuit embedded in the output interface unit 200 of FIG. 3. The inverter 240 receives an error bit input from the memory 10 and inverts the output. And a logical product operation element 250 that receives the output data from the memory 10 and the inverted error bits, respectively, and performs logical AND operation on the output data.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIGS. 3 to 7.

First, when a transfer request signal such as the wave form (4b) of FIG. 4 is input from the transfer request and data processing unit 30, the glitch removing circuit in the output interface unit 200 extracts the glitch component included in the input transfer request signal. Remove That is, since the transmission request signal acts as a start signal for data transmission, when a glitch occurs due to an external factor, the malfunction of the output interface unit 200 is prevented by the glitch elimination circuit shown in FIG. Referring to the glitch removal process of the transmission request signal with reference to the timing diagrams of FIGS. 5 and 6, the transmission request signal 6a input from the transmission request and data processor 30 is the first D flip-flop 210. It is latched at the rising edge of the bit clock 6b through the output, and is latched at the falling edge of the bit clock 6b via the 2D flip-flop 230 and output as shown in 6c. Therefore, since the transmission request signal 6a is latched by the bit clock 6b, the glitch generated outside the latch time does not affect the transmission operation of the output interface unit 200.

Hereinafter, a process of transmitting data by the output interface unit 200 in response to the transmission request signal will be described. First, the data and error bits transmitted from the signal processing means (e.g., EFM decoder, etc.) are stored in the memory 10. Accordingly, when a transmission request signal is input from the transmission request and data processing unit 30, the output interface unit 200 accesses the memory 10 to read the data and error bits in response to the transmission request signal. In this case, the data represents, for example, audio compression data in a mini disc player or the like. At this time, the data amount read by the output interface unit 200 from the memory 10 is 212 bytes, which is an audio signal extension unit of the transmission request and the data processing unit 30. In addition, when a transmission request signal is input from the transmission request and data processing unit 30, the output interface unit 200 outputs a byte clock and a bit clock to the transmission request and data processing unit 30 in response thereto.

Referring to the above-described operation with reference to the timing diagram of FIG. 4, first, data transmission starts from the moment when the transmission request and the transmission request signal input from the data processing unit 30 fall to the low state. The byte clock has a period of 8 bits for each data to be transmitted, and is used to convert the transmission request and data processor 30 into parallel data of 8 bits.

Meanwhile, in the above-described data transmission process, the output interface unit 200 searches for the corresponding error bit of the data read from the memory 10, and transmits the data in which the error occurred is fixed to 0 state (or null state). The error bit is not transmitted. That is, as shown in FIG. 7, the second inverter 240 receives an error bit of a high state indicating an error occurrence of a corresponding data section and outputs the low bit inverted signal. The inversion signal and the data from the memory 10 are logically operated to generate and output data to be output to the transfer request and data processor 30.

In general, when the compressed audio data is received and the data is processed by the transmission request and the data processing unit 30, the bead that has an error cannot be recovered. Therefore, if the transmitting end makes the error byte 0 and transmits it, the receiving end does not need to process it as 0, thus reducing the transmission line.

Therefore, the present invention eliminates the glitch of the input transmission request signal, thereby preventing malfunction of the output interface circuit, and since it is not necessary to transmit an error bit, the transmission line can be simply configured and the transmission request and data requiring data transmission There is an advantage that the processing unit 30 does not need to perform a separate error bit processing.

Claims (4)

A data output interface apparatus of an optical disk drive recording apparatus having signal processing means for decoding and outputting a signal reproduced from an optical disk surface, comprising: memory means for storing data input from said signal processing means, and data input from a receiving end; A glitch removal circuit for removing the glitch component included in the request signal, and accessing the storage means in response to the glitch-free transmission request signal, and logically calculating an error bit between the data of a predetermined unit and the data interval obtained as a result of the access. An error generation data elimination circuit for outputting data in the generated data section in a null state, and generating a byte clock for synchronizing parallel conversion of the data in synchronization with a predetermined reference clock and the reference clock; With the output data of the removal circuit A data output interface device comprising an output means for outputting. The method of claim 1, wherein the glitch elimination circuit; A first latch means for receiving the transmission request signal and latching it in synchronization with the reference clock; and a second latch means for receiving the output of the first latch means and latching the output in synchronization with the inversion signal of the reference clock. Data output interface device characterized in that. The data output interface device according to claim 1, wherein the data accessed and output from the storage means is audio compression data transmitted in units of 212 bytes. 2. The system of claim 1, wherein the error generating data removal circuit comprises: a; And an inverter for inverting the error bit and a logical multiplication device for performing logical AND operation on the data input and accessed from the inverter output signal and the storage means.