JP2823831B2 - Data output interface circuit of optical disk drive recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an optical disk drive recording apparatus, and more particularly to a data output interface circuit for outputting audio data in response to a data transmission request signal.

[0002]

2. Description of the Related Art A mini-disc player and the like are generally used as a recordable optical disc drive and recording apparatus. One embodiment relating to the configuration and operation of such an optical disc drive and recording apparatus is disclosed in Korean Patent Application No. Ninth
No. 4-2311.

This optical disk drive recording apparatus converts a signal read from a disk serving as a recording medium into an EFM (Eight to Fourteen Modular) signal.
A memory for decoding and outputting data through a signal processing device such as a signal decoder (not shown), and a data output interface circuit for outputting data stored in the memory and processing the output data. Such a conventional data output interface circuit and related configuration is shown in FIG.
No. -2311. Generally, a mini-disc player requires 212 data transmission requests at one time.
Bytes are transmitted serially, and a data transmission timing chart at this time is shown in FIG.

In FIG. 2, (A) waveform shows a bit clock output from the data output interface circuit 20 to the data transmission request and reception data processing section 30, and (B) waveform shows this data transmission request and reception data. From the data processing unit 30 to the data output interface circuit 20
Low active input to the
The state data transmission request signal is shown. The (C) waveform shows data transmitted from the data output interface circuit 20 to the data transmission request and received data processing unit 30, and the (D) waveform shows the data output interface circuit 20.
5 shows a byte clock output to the data transmission request and received data processing section 30 from the data transmission request, and is a synchronization pulse signal corresponding to one byte of the transmitted data. The waveform (E) is an error signal indicating whether an error has occurred in the transmitted data. The timing diagram of FIG. 2 shows the transmission timing for one word of data. In general, the mini disc player should transmit 212 bytes of data, so the timing operation of FIG. 2 must be repeated 106 times. .

The operation of the conventional data output interface circuit will be briefly described with reference to FIGS. First, when the data transmission request signal shown in FIG. 2B is input to the data output interface circuit 20, the data output interface circuit 20 reads the corresponding data of FIG. And serially transmitted to the reception data processing unit 30 in byte units.
Is output to the data transmission request / reception data processing unit 30. At this time, the frequency of the bit clock in FIG. 2A is about 5.65 MHz.

On the other hand, the data output interface circuit 20 reads the error signal shown in FIG. 2E from the memory 10 and transmits the error signal shown in FIG. This read signal is shown in FIG.
Is transmitted to the data transmission request / reception data processing unit 30 in 1-bit units during one byte period of the data. That is, when the error signal in FIG. 2E is in a logic “high” state, it indicates that there is an error in the 1-byte transmission data in FIG. 2C. Thereafter, if the data transmission request signal of FIG. 2B is at the logic "high" state at the falling edge of the second cycle of the byte clock of FIG. 2D, the one-word data transmission operation is completed. By repeating this transmission operation 106 times, the data transmission operation of 212 bytes is completed.

However, in the conventional data output interface circuit, there is a problem that the data in which the error has occurred is transmitted to the data transmission request and reception data processing unit 30 despite the input of the error signal. In addition, the conventional data output interface circuit has a disadvantage that a normal data transmission operation cannot be performed when a glitch occurs in the data transmission request signal.

[0008]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a data output interface circuit capable of efficiently performing a data transmission operation by removing erroneous data. Another object of the present invention is to
An object of the present invention is to provide a data output interface circuit capable of performing a normal data transmission operation even when an error occurs in a data transmission request signal.

[0009]

In order to achieve the above object, the present invention provides a data output interface circuit of an optical disk drive / recording apparatus, comprising a storage means for storing data input from a predetermined signal processing means. In response to the input of a data transmission request signal for requesting data transmission, the storage unit is accessed, and a predetermined unit of data and an error bit indicating an error occurrence state of this data section are input, and a predetermined reference clock; Output means for generating and outputting a byte clock for synchronizing the parallel conversion of the data in synchronization with the reference clock, and outputting the data to a logical "0" state in response to the error bit indicating an error occurrence state It is composed of

[0010]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
FIG. 3 is a block diagram of a data output interface circuit according to a preferred embodiment of the present invention.

FIG. 1 shows a memory 10 for storing data input from a predetermined signal processing means, and outputs address data to the memory 10 in response to the input of a data transmission request signal, and is accessed by the address data. Data output interface circuit 200 for inputting and outputting data, and generating and outputting a byte clock for synchronizing the data transmission using a bit clock as a reference clock.
And a data transmission request and reception data processing unit 30 for generating and outputting the data transmission request signal, receiving the data, the bit clock, and the byte clock and processing the data.

In the structure shown in FIG. 1, data output interface circuit 200 performs an operation of accessing and transmitting data stored in memory 10 in response to the data transmission request signal. The data transmitted from the data output interface circuit 200 is expanded by the data transmission request and reception data processing unit 30 according to a predetermined algorithm. At this time, the unit of calculation of the data transmission request and reception data processing unit 30 is 212 bytes. That is, the memory 10 stores data in units of 212 bytes, and outputs the data 212 bytes at a time only when there is a transmission request through the data output interface circuit 200. The memory 10 stores an error bit for each bit indicating whether or not an error has occurred in the 212-byte data. Even if the data transmission request and the reception data processing unit 30 receive the data in which the error has occurred, the error bit is transmitted. do not use. Thus, in the present invention, data for which an error has been confirmed is converted into a specific value (for example, “0”) and transmitted, and no error signal is transmitted.

FIG. 4 is a timing chart according to FIG.
(A) is a waveform of a bit clock which is a reference clock of the data output interface circuit 200, and (B) is
The waveform of the data transmission request signal of the data transmission request and reception data processing unit 30 is shown in FIG.
(D) shows the waveform of the byte clock generated and output from the data output interface circuit 200.

FIG. 5 is a detailed block diagram showing the input section of the data output interface circuit 200 of the data transmission request signal in the configuration shown in FIG. The figure shows a first D flip-flop 210 which receives and latches a data transmission request signal in synchronization with a bit clock, an inverter 220 which receives and inverts and outputs the bit clock, and a bit clock which is inverted from the inverter 220. And a second D flip-flop 230 that latches and outputs the output signal of the first D flip-flop 210 in synchronization with the clock.

FIG. 6 is a timing chart according to the configuration shown in FIG. 5, and FIG.
10, the waveform of the data transmission request signal input to 10, (B)
Is the waveform of this bit clock, and (C) is the second D
4 shows a waveform of an output signal of the flip-flop 230. FIG.
FIG. 3 is a partial detailed configuration diagram showing in detail the configuration for removing error occurrence data of the data output interface circuit 200 in the configuration shown in FIG. 3, and receives an error bit input from the memory 10 and outputs an inverted output. Inverter 2
And an AND operation element 250 which receives the output data from the memory and the inverted error bit, performs an AND operation, and outputs the result.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIGS. When a data transmission request signal such as the waveform (B) shown in FIG. 4 is input from the data transmission request and reception data processing unit 30, the data output interface circuit 200 generates a glitch of the input data transmission request signal. Remove. That is, since this data transmission request signal acts as a data transmission start signal, when a glitch occurs due to an external factor, the data transmission request signal shown in FIG.
The malfunction of the data output interface circuit is prevented by the glitch removing circuit shown in FIG.

Referring to the timing diagrams of FIGS. 5 and 6,
The process of removing the glitch from the data transmission request signal will be described. The data transmission request signal of FIG. 6A input from the data transmission request and received data processing unit 30 is the first data transmission request signal.
The data is latched and output at the rising edge of the bit clock of (B) through the D flip-flop 210, and is latched and output as at (C) at the falling edge of the bit clock of (B) through the second D flip-flop 230. Therefore, since the data transmission request signal of (A) is latched by the bit clock of (B), glitches occurring at times other than this latch time do not affect the transmission operation of the data output interface circuit 200.

The process of transmitting data by the data output interface circuit 200 in response to the data transmission request signal will be described below. First, the memory 10 stores data and error bits transmitted from external signal processing means (for example, an EFM decoder).
Therefore, the data transmission request and reception data processing unit 30
, A data transmission request signal is input, and in response, data output interface circuit 200 accesses memory 10 to read the data and the error bit. This data means, for example, an audio compression signal in a mini disc player or the like. At this time, the amount of data read from the memory 10 by the data output interface circuit 200 is 212 bytes, which is the data transmission request and expansion unit of the audio signal of the received data processing unit 30. When a data transmission request signal is input from the data transmission request / reception data processing section 30, the data output interface circuit 200 responds to this by setting the byte clock and the bit clock to the data transmission request / reception data processing. Output to the unit 30.

Referring to the timing chart shown in FIG. 4, first, the data transmission operation is started when the data transmission request signal and the data transmission request signal input from the reception data processing unit 30 are in a logical "low" state. From the moment it descends. The byte clock has a cycle of 8 bits of data to be transmitted, and is used by the data transmission request / reception data processing unit 30 to convert the data into parallel data in units of 8 bits.

On the other hand, during the data transmission process, the data output interface circuit 200 searches for the corresponding error bit of the data read from the memory 10 and transmits all the data in which an error has occurred to the logical "0" state. , This error bit is not transmitted. That is, as shown in FIG. 7, the second inverter 240 receives an error bit of a logic “high” state that indicates occurrence of an error in the corresponding data section, outputs the inverted bit as a logic “low” state, and performs a logical product operation. The element 250 performs an AND operation on the inverted signal and the data from the memory 10 to generate and output the data transmission request and the data to be output to the received data processing unit 30.

Generally, when compressed audio data is input and data expansion processing is performed by the data transmission request / reception data processing unit 30, since an error cannot be recovered from a byte in which an error has occurred, an error occurs. The processing is performed by setting the byte to a logical "0" state. Therefore, if a byte in which an error has occurred at the transmitting end is transmitted in a logical "0" state, the receiving end does not have to process the logical "0" state, and the number of transmission lines can be reduced.

[0022]

As described above, according to the present invention, it is possible to prevent a malfunction of a data output interface circuit by removing a glitch of an input data transmission request signal, and to prevent a transmission line from transmitting an error bit. Can be simply configured, and there is an advantage that the data transmission request and the received data processing unit for requesting the data transmission do not have to perform the separate error bit processing.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional data output interface circuit.

FIG. 2 is a timing diagram of the circuit of FIG.

FIG. 3 is a block diagram of a data output interface circuit according to a preferred embodiment of the present invention.

FIG. 4 is a timing diagram of the circuit of FIG. 3;

FIG. 5 is a detailed circuit diagram of a part of the configuration of FIG. 3;

FIG. 6 is a timing diagram of the circuit of FIG. 5;

FIG. 7 is a detailed circuit diagram of another part of the configuration of FIG. 3;

[Explanation of symbols]

 Reference Signs List 10 memory 30 data transmission request and reception data processing unit 200 data output interface circuit 300 data transmission request and reception data processing circuit 210 first D flip-flop 220 inverter 230 second D flip-flop 240 inverter 250 AND operation element

Claims (6)

(57) [Claims] 1. A data output interface circuit of an optical disk drive recording device, comprising: storage means for storing data input from a predetermined signal processing means; and said storage in response to input of a data transmission request signal requesting data transmission. Means for accessing a predetermined unit of data and an error bit indicating an error occurrence state of this data section; a predetermined reference clock; and a byte for synchronizing parallel conversion of this data in synchronization with the reference clock. A data output interface circuit for generating and outputting a clock and outputting the data to a logic "0" state in response to the error bit indicating an error occurrence state. 2. The output interface means includes: first latch means for receiving the data transmission request signal and latching and outputting the data transmission request signal in synchronization with the reference clock; and latch output of the first latch means. And outputs an output latch in synchronization with the inverted signal of the reference clock.
2. The data output interface circuit according to claim 1, comprising: latch means. 3. The data output interface circuit according to claim 1, wherein the data is compressed audio data transmitted in units of 212 bytes. 4. The data output interface circuit according to claim 2, wherein said data is audio compressed data transmitted in units of 212 bytes. 5. The output interface means includes: an inversion means for inverting and outputting the error bit; and an AND operation means for performing an AND operation on an output signal of the inversion means and data in the corresponding data section and outputting the result. The data output interface circuit according to claim 1. 6. An output interface means for inverting and outputting the error bit, and an AND operation for performing an AND operation on an output signal of the inversion means and data in the corresponding data section and outputting an operation result. The data output interface circuit according to claim 4, comprising: