KR0177742B1 - Micro controller development system - Google Patents

Abstract

The present invention relates to a microcontroller development system, in which circuits for implementing uploading, downloading, breakpoints, and single steps are embedded in a microcontroller and a single chip, using a trap instruction that is a software interrupt. It executes the functions and interfaces with a personal computer using a parallel port to implement one-chip MDS.

Description

Microcontroller development system that can be integrated into the chip of the microcontroller

1 is a block diagram showing the overall configuration of a microcontroller development system incorporating a microcontroller in a single chip in accordance with the present invention.

2 is a block diagram showing the detailed configuration of the one-chip type MS in FIG.

3 is a detailed circuit block diagram of an MS block of FIG. 2 as an embodiment of the present invention.

4 is a detailed circuit diagram of the trap command generation unit in FIG.

The present invention relates to a microcontroller development system (MDS), which is used in connection with a data processing device such as a microcontroller for program debugging and emulation functions. More specifically, the present invention relates to a microcontroller development apparatus capable of minimizing additional hardware required to implement a development support function.

In general, MDS is used in connection with data processing devices such as microcontrollers to assist in debugging hardware and software. These typical functions of MSDS include inserting and responding to breakpoints, stopping execution of the data processor for testing, changing contents of various system registers as necessary, and tracking the execution of software. includes tracing)

The MS has software and hardware, and externally executes an external command of a user to debug a program that fetches data loaded by the data processing apparatus and executes the program as a result by initially downloading program data into a program memory. In response to this, a breakpoint can be designated and the data processing of the data processing apparatus can be placed in the single step mode as necessary. In order to perform such an operation, the software of the MS is divided into a ghost for controlling the hardware and an assembler for converting an assembly language into a machine language, and the hardware is a central part of the data processing apparatus. It has a part that controls the processing unit and a part that monitors the state of the central processing unit.

Conventional MDSs used in this field are separated from data processing devices such as microcontrollers to be debugged. That is, since the conventional microcontroller design is not adapted to the function of the MS, the hardware of the MS for performing the functions related to the MS is installed separately from the outside of the microcontroller. Therefore, the conventional MS connected to the microcontroller through a specific interface port has to implement the MS function by using limited signals, and thus, additional hardware configuration is complicated and performance is deteriorated.

Therefore, simplifying the configuration of the hardware is directly related to lowering the manufacturing cost of the MS, which is tens to hundreds of times the price of the data processing apparatus. In order to achieve such a simplification, the design of a data processing device such as a microphone roll controller and the like to be suited to the functions of the MS is firstly entailed, and the hardware of the MS must be able to be operated by the instructions of the micro controller. do. In addition, it is necessary to make the memory control block of the microcontroller into a configuration that can interface with the MS.

Accordingly, an object of the present invention is to provide a development apparatus for a data processing apparatus which can solve the above problems of the conventional MS.

Another object of the present invention is to provide a microcontroller development apparatus capable of minimizing additional hardware required to implement a development support function.

It is still another object of the present invention to provide a microcontroller development system that can be integrated into a chip of a microcontroller to implement an MS function at a low cost.

In order to achieve the above objects, the present invention is to design the memory control block of the microcontroller considering the interface with the MS, and to implement the hardware of the MS to implement the functions of the MS using the microcontroller command. It is characterized by being incorporated in the chip of a microcontroller.

According to the present invention, a deployment device used in connection with a data processing system to support debugging of software and hardware via a parallel port for interfacing is: connected to the troop port via a control and data bus and externally to the troop A register section for storing external data applied to the coat and data provided from a memory connected with the data processing system; Program data of the data processing system so that a development support function is performed by the data processing system when the external data stored between the register unit and the data processing system and stored in the register unit is development related data. A trap instruction generator for generating a vector priority interrupt signal through the bus; A mode leveling portion for connecting an address, control, and data bus of said memory with one of said data processing system or said register portion in response to a selection signal provided through a control bus of said data processing system; Here, the register section, trap command generation section, and mode switching section are configured on the same chip as the data processing system to minimize additional hardware.

Hereinafter, the structure of the MS according to an embodiment of the present invention will be described with the accompanying drawings. In the following description, the detailed items for such configurations are described in detail in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

Moreover, the features and functions of well-known basic elements are not described in detail in order not to obscure the present invention. In addition, the same reference numbers appearing in the description refer to the same or equivalent elements wherever possible.

As used herein, the term debugging refers to finding and correcting an error part of a program in a diagnostic mode, and debugging is performed by the software of MS which performs a dump and trace. The term 'MSD' refers to various support systems for development provided by the maker when it is necessary to write a program that clarifies the contents of the processing in advance and store it in a memory block in order to do a specific task for a data processing device such as a microcontroller. Or software.

1 is a block diagram showing the overall configuration of a microcontroller development system integrated with a microcontroller in one chip in accordance with the present invention. Referring to FIG. 1, a circuit for implementing up-loading, down-loading, break point, and single step, which are functions of the MS according to the present invention, is micro-controlled. A one-chip type MDS 10 having the same chip as the controller chip, a program memory 20 and a data memory 30 connected through the one-chip type MDS, an address, data, and a control bus for access to programs and data, and the one chip. Interfacing between the reset circuit 40 for resetting the type MD 10, the clock generator 50 for providing a clock to the one chip type MD 10, and the one chip type MS 10 and an external personal computer in a support mode. A parallel port 70 for interfacing and an interface connector 60 for interfacing with an external device for microcontroller programmatic control. There is off. In the one-chip type MD 10 of FIG. 1, the memory control block of the microcontroller is designed in consideration of an interface with the MS, so that the function of the MS can be implemented using a command of the microcontroller. Therefore, the hardware of the MS can be incorporated into the chip of the microcontroller. The microcontroller as a data processing device applied in the embodiment of the present invention may be a microroll processor such as SAM 16, for example. The downloading refers to an operation of an external personal computer storing a program or a data file in the memories 20 and 30 through the MS, and the uploading refers to a program or data file downloaded to the memories 20 and 30. The computer fetches something. Also, the break point is the position of the program interrupted by the monitor routine during debugging when the function of the MS is executed, and the single step is a function set to facilitate the debugging of the user. The MDS may transmit a single step command to the microcontroller so that the microcontroller executes one command at a time.

FIG. 2 shows the detailed configuration of the one-chip type MD 10 of FIG. 1 with reference to the memory blocks 20 and 30 of FIG. Referring to FIG. 2, it can be seen that the one-chip type MS 10 includes a microcontroller 12 and an MS block 14 as outlined in the description of FIG. 1. The microcontroller 12 is connected to the interface connector 60 and is also connected to the MS block 14 through an address bus, a data bus, a control bus, an internal program data bus, and a program counter value signal line L1. The MS block 14 is connected to the parallel port 70 through an input data bus, a contlobus, and an output data bus, and also the memory blocks 20, 30 through a memory address bus, a memory data bus, and a memory control bus. Connected with. The detailed configuration of the MS block 14 incorporated on the same chip as the microcontroller 12 is shown in FIG.

3 is a detailed circuit block diagram of an MS block 14 in FIG. 2 as an embodiment of the present invention. Referring to FIG. 3, the register part including the first, second, and third registers 140, 141, and 142 is connected to the serial port 70 through a control and input and output data buses, and external data and the micro controller are externally applied to the parallel port 70. It is responsible for storing data provided from 12 memory blocks 20,30. The trap command generation unit 143 is connected between the register unit and the microcontroller 12, so that the development support function is performed by the microcontroller 12 when the external editor stored in the register unit is development related data. To this end, a function of generating a vector priority interrupt signal through the internal program data bus is performed during the support mode. The mode switching unit including first, second, third buffers 144, 145, and 146 transfers the address, control, and data buses of the memory blocks 20 and 30 to the micro controller 12 in response to a selection signal provided through the control buffer of the micro controller 12. It is responsible for the switching function of connecting with one of the register parts. In FIG. 3, external data is provided on the pass input data bus via the parallel port 70 at the time of downloading. The second register 141 receives the data, stores the data, and applies the data to the data bus connected to the third register 142. When the external data is applied to the data bus, the microcontroller 12 is already in a hardware stop state by the trap command generation unit 143. Accordingly, in this case, the selection signal applied through the control bus of the microcontroller 12 may be selected from the address bus, the control bus, and the data bus of the memory block. It is provided as a logic level signal which allows the three registers 141 and 142 to be connected to an address bus, a control bus, and a data bus, respectively. Thus, the external data is applied to the memory data bus via the input terminal A of the third buffer 146 and stored at the designated addresses of the memory blocks 20 and 30. During uploading, the data in the memory block is stored in the third register 142 as a read word through the third buffer 146 and then provided to the parallel port 70 through the output data wave bus of the register 142. In this case, the trap command generation unit 143 generates a software stop signal through the internal program data bus of the microcontroller 12. In order to download the initial user program and the MS program to the memory blocks 20 and 30, the hardware stop of the MS is used, and the software stop is used in the MS program routine. On the other hand, the single step and the break point function is also performed by the trap command generation unit 143 outputs the interrupt signal. When the data interfacing between the MS block 14 and the memory blocks 20 and 30 is completed, the MS block 14 releases the stop by the trap command generation unit 143. Accordingly, the logic level of the selection signal is inverted so that the microcontroller 12 is connected to the address bus, the control bus, and the data bus of the memory blocks 20 and 30, respectively, to the address bus, the control bus, and the data bus of the microcontroller 12. Interfacing data with memory blocks.

Accordingly, it can be seen that the MS block 14 having the register part, the trap command generation part 143, and the mode switching part are formed on the same chip as the chip of the microcontroller 12 without adding additional hardware. In addition, a user may perform a function related to the MS by using the command of the microcontroller 12.

4 is a detailed circuit diagram of the trap command generation unit 143 in FIG. Referring to FIG. 4, it can be seen in more detail that the corresponding interrupt signal for the break point and the single step belonging to the function of the MS is output by the trap command generator 143. In FIG. 4, the AND gate 401 is a first clock CLK1 divided by two system clock SCLKs, a fetch enable signal NBASE indicating whether the next state of the current state can fetch an instruction, a single-step enable signal SSON, And an inverted response of the signal BPWAKE indicating whether or not the break point or the single step has been activated. The output of the AND gate 401 is generated at the data input terminal D of the de-type flip-flop 405. The output of the AND gate 401 is provided at the clock stage CK of the de-type flip-flop 405 with the output of the inverter 402 inverting the system clock SCLK. An output of the AND gate 403 which AND gates the reset signal RESET and the inverted output of the AND gate 404 is provided to the reset terminal RN of the flip-flop 405. The output of the flip-flop 405, which latches the signal of the forgetting stage D to the output terminal Q in response to the clock applied to the clock terminal CK, is provided to one side input of the OR gate 408 and one of the three inputs of the AND gate 404 is provided. Provided as input. On the other hand, the other input of the OR gate 408 is provided from the output of the AND gate 407. The AND gate 407 receives the output of the comparator 406 as one of four inputs and receives the signals NBASE, BPWAKE and the break point enable signal BPON. The comparator 406 outputs a result of comparing the break point address signal BPA and the signal of the line L1. Here, SSON and BPON of the signals are provided from the first register 140 of FIG. 3, the signal BPA is provided from the second register 141, and the signal of the line L1 is provided from the microcontroller 12. Is the value of. The clocks CLK1 and SCLK are provided from the clock generator 50 of FIG. 1, and the reset signal RESET is provided from the reset circuit 40 of FIG. The remaining signals other than the above signals are provided through the control bus of the microcontroller 12. The output of OR gate 408 is applied to select stage S of multiplexer 409. In the present embodiment, when the signal of the selection terminal S is provided as logic level high, the signal of the input A is applied on the internal program data bus via the output terminal. In contrast, when the signal of the selection terminal S is provided low, the signal of the input B is connected to the internal program data bus. Accordingly, the mipro controller 12 preferentially performs a break point, which is one of the MS functions, if the data on the internal program data bus is zero while executing the program, and then performs a single step if the data is continuously zero. That is, when a breakpoint or a single step is taken, the instruction to be currently fetched through the data bus of the memory is blocked by the multiplexer 409 and replaced by a trap instruction, which is a software instruction, so that the microcontroller 12 performs an MS program routine. Here, the vector of the MS software interrupt, such as a break point or a single step, has the highest priority. The program of the MS is executed by using the interrupt of the mipro controller, and the microcontroller executes the original user program after completing the execution of the MS program.

As described above, the present invention can realize the MS with a simple configuration, thereby reducing the problems caused by the complexity of the hardware and reducing the manufacturing cost of the MS.

Claims (5)

A development apparatus for use in connection with a data processing system to support debugging of software and hardware through a parallel port for interfacing; A register unit for storing external data connected to the parallel port through a control and data bus and externally applied to the parallel port and data provided from a memory connected to the data processing system; A program of the data processing system connected to the register unit and the data processing system such that a development support function is performed by the data processing system when external data stored in the register unit is development related data. A trap command generator for generating a vector priority intercept signal through the data bus; A mode switching unit for connecting an address, a control, and a data bus of the memory with either the data processing system or the register unit in response to a selection signal provided through a control bus of the data processing system; Wherein the register unit, trap instruction generation unit, and mode switching unit are configured on the same chip as the data processing system to minimize additional hardware. The development apparatus of claim 1, wherein the register unit has first, second and third registers. The development apparatus of claim 1, wherein the trap command generation unit comprises a plurality of gate elements and a multiplexer. The development apparatus of claim 1, wherein the mode switching unit comprises first, second, third, and buffers. In a microcontroller development device used in conjunction with a microcontroller to support debugging of software and hardware through a parallel port for interfacing: A register unit for storing external data connected to the parallel coat through a control and data bus and externally applied to the parallel port and data provided from a memory connected to the microcontroller; A program data bus of the microcontroller to be executed by the microcontroller so that a development support function is performed by the microcontroller when the external data stored in the register unit is connected between the register unit and the microcontroller. A trap instruction generator for generating a vector priority interrupt signal through the signal generator; A mode switching unit for connecting an address, a control, and a data bus of the memory with one of the microcontroller or the register unit in response to a selection signal provided through a control bus of the microcontroller; Wherein the microcontroller development device is configured on the same chip as the data processing system to minimize additional hardware.