KR0175115B1 - 프로세서 시스템 및 디버그모드 실현방법 - Google Patents

프로세서 시스템 및 디버그모드 실현방법 Download PDF

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Publication number
KR0175115B1
KR0175115B1 KR1019950703428A KR19950703428A KR0175115B1 KR 0175115 B1 KR0175115 B1 KR 0175115B1 KR 1019950703428 A KR1019950703428 A KR 1019950703428A KR 19950703428 A KR19950703428 A KR 19950703428A KR 0175115 B1 KR0175115 B1 KR 0175115B1
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KR
South Korea
Prior art keywords
instruction
exception
floating point
floating
integer
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Expired - Lifetime
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KR1019950703428A
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English (en)
Korean (ko)
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KR960701398A (ko
Inventor
죠셉 피. 브라트
죤 브레난
피터 얀 텍 히스
챤드라 에스. 죠시
웰리암 에이. 하프만
모니카 알. 노활
파울 로드만
죠셉 티. 스캔론
맨 키트 탕
Original Assignee
윌리엄 더블유. 켈리
실리콘 그래픽스 인코오포레이티드
타쉬로 요시꾸니
가부시끼가이샤 도시바
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Application filed by 윌리엄 더블유. 켈리, 실리콘 그래픽스 인코오포레이티드, 타쉬로 요시꾸니, 가부시끼가이샤 도시바 filed Critical 윌리엄 더블유. 켈리
Publication of KR960701398A publication Critical patent/KR960701398A/ko
Application granted granted Critical
Publication of KR0175115B1 publication Critical patent/KR0175115B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/3698—Environments for analysis, debugging or testing of software
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Advance Control (AREA)
  • Treatments For Attaching Organic Compounds To Fibrous Goods (AREA)
KR1019950703428A 1993-12-15 1994-12-15 프로세서 시스템 및 디버그모드 실현방법 Expired - Lifetime KR0175115B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US8/166969 1993-12-15
US08/166,969 1993-12-15
US08/166,969 US5537538A (en) 1993-12-15 1993-12-15 Debug mode for a superscalar RISC processor
PCT/JP1994/002110 WO1995016953A1 (en) 1993-12-15 1994-12-15 Processor system and debug mode accomplishment method

Publications (2)

Publication Number Publication Date
KR960701398A KR960701398A (ko) 1996-02-24
KR0175115B1 true KR0175115B1 (ko) 1999-04-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950703428A Expired - Lifetime KR0175115B1 (ko) 1993-12-15 1994-12-15 프로세서 시스템 및 디버그모드 실현방법

Country Status (8)

Country Link
US (1) US5537538A (enExample)
EP (1) EP0684552B1 (enExample)
JP (1) JP2843152B2 (enExample)
KR (1) KR0175115B1 (enExample)
CN (1) CN1084496C (enExample)
DE (1) DE69428110T2 (enExample)
TW (1) TW274595B (enExample)
WO (1) WO1995016953A1 (enExample)

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US5748855A (en) * 1995-10-02 1998-05-05 Iinternational Business Machines Corporation Method and system for performance monitoring of misaligned memory accesses in a processing system
US6065106A (en) * 1996-12-20 2000-05-16 Texas Instruments Incorporated Resuming normal execution by restoring without refetching instructions in multi-word instruction register interrupted by debug instructions loading and processing
US6081885A (en) * 1996-12-20 2000-06-27 Texas Instruments Incorporated Method and apparatus for halting a processor and providing state visibility on a pipeline phase basis
US6112298A (en) * 1996-12-20 2000-08-29 Texas Instruments Incorporated Method for managing an instruction execution pipeline during debugging of a data processing system
US5878377A (en) * 1997-04-10 1999-03-02 International Business Machines Corporation Environmental and power error handling extension and analysis
US6425055B1 (en) 1999-02-24 2002-07-23 Intel Corporation Way-predicting cache memory
US6591361B1 (en) 1999-12-28 2003-07-08 International Business Machines Corporation Method and apparatus for converting data into different ordinal types
US6857061B1 (en) 2000-04-07 2005-02-15 Nintendo Co., Ltd. Method and apparatus for obtaining a scalar value directly from a vector register
US6859862B1 (en) 2000-04-07 2005-02-22 Nintendo Co., Ltd. Method and apparatus for software management of on-chip cache
US6701424B1 (en) 2000-04-07 2004-03-02 Nintendo Co., Ltd. Method and apparatus for efficient loading and storing of vectors
JP3855270B2 (ja) * 2003-05-29 2006-12-06 ソニー株式会社 アンテナ実装方法
US7703076B1 (en) 2003-07-30 2010-04-20 Lsi Corporation User interface software development tool and method for enhancing the sequencing of instructions within a superscalar microprocessor pipeline by displaying and manipulating instructions in the pipeline
US7200742B2 (en) 2005-02-10 2007-04-03 International Business Machines Corporation System and method for creating precise exceptions
US7734901B2 (en) * 2005-10-31 2010-06-08 Mips Technologies, Inc. Processor core and method for managing program counter redirection in an out-of-order processor pipeline
US7711934B2 (en) * 2005-10-31 2010-05-04 Mips Technologies, Inc. Processor core and method for managing branch misprediction in an out-of-order processor pipeline
US20070204139A1 (en) 2006-02-28 2007-08-30 Mips Technologies, Inc. Compact linked-list-based multi-threaded instruction graduation buffer
US7721071B2 (en) * 2006-02-28 2010-05-18 Mips Technologies, Inc. System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
US20080016326A1 (en) * 2006-07-14 2008-01-17 Mips Technologies, Inc. Latest producer tracking in an out-of-order processor, and applications thereof
US7370178B1 (en) * 2006-07-14 2008-05-06 Mips Technologies, Inc. Method for latest producer tracking in an out-of-order processor, and applications thereof
US7657708B2 (en) * 2006-08-18 2010-02-02 Mips Technologies, Inc. Methods for reducing data cache access power in a processor using way selection bits
US7650465B2 (en) 2006-08-18 2010-01-19 Mips Technologies, Inc. Micro tag array having way selection bits for reducing data cache access power
US8032734B2 (en) * 2006-09-06 2011-10-04 Mips Technologies, Inc. Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor
US7647475B2 (en) * 2006-09-06 2010-01-12 Mips Technologies, Inc. System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue
US7594079B2 (en) 2006-09-29 2009-09-22 Mips Technologies, Inc. Data cache virtual hint way prediction, and applications thereof
US9946547B2 (en) 2006-09-29 2018-04-17 Arm Finance Overseas Limited Load/store unit for a processor, and applications thereof
US8078846B2 (en) 2006-09-29 2011-12-13 Mips Technologies, Inc. Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated
US20080082793A1 (en) * 2006-09-29 2008-04-03 Mips Technologies, Inc. Detection and prevention of write-after-write hazards, and applications thereof
US8555039B2 (en) * 2007-05-03 2013-10-08 Qualcomm Incorporated System and method for using a local condition code register for accelerating conditional instruction execution in a pipeline processor
CN101174200B (zh) * 2007-05-18 2010-09-08 清华大学 一种具有五级流水线结构的浮点乘加融合单元
US20100153693A1 (en) * 2008-12-17 2010-06-17 Microsoft Corporation Code execution with automated domain switching
CN104793987B (zh) * 2014-01-17 2018-08-03 中国移动通信集团公司 一种数据处理方法及装置

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Also Published As

Publication number Publication date
KR960701398A (ko) 1996-02-24
US5537538A (en) 1996-07-16
EP0684552A4 (en) 1996-12-04
CN1117764A (zh) 1996-02-28
HK1018167A1 (en) 1999-12-10
DE69428110D1 (de) 2001-10-04
WO1995016953A1 (en) 1995-06-22
DE69428110T2 (de) 2002-04-25
EP0684552B1 (en) 2001-08-29
TW274595B (enExample) 1996-04-21
JP2843152B2 (ja) 1999-01-06
EP0684552A1 (en) 1995-11-29
CN1084496C (zh) 2002-05-08

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