KR0172723B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR0172723B1 KR0172723B1 KR1019950069453A KR19950069453A KR0172723B1 KR 0172723 B1 KR0172723 B1 KR 0172723B1 KR 1019950069453 A KR1019950069453 A KR 1019950069453A KR 19950069453 A KR19950069453 A KR 19950069453A KR 0172723 B1 KR0172723 B1 KR 0172723B1
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- tungsten
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본원에서는 반도체 소자의 금속배선 형성방법을 개시한다. 그 방법은 (가)게이트 전극, N영역 및 소오스/드레인 전극이 형성된 상태의 반도체 기판 상부에 평탄화된 형성하는 단계; (나)상기 산화막을 사진 식각법에 의해 선택적으로 식각하여 콘택홀을 형성하는 단계; (다)상기 콘택홀 내부에 텅스텐 플러그를 형성한 후, 텅스텐 클러그의 상부에 소정의 금속배선을 형성하는 단계; (라)전체 구조 상부에 질화막을 증착하는 단계; (마)전체 구조 상부에 텅스텐막을 전면 증착하는 단계; (바)상기 텅스텐막을 화할-기계 연마법으로 연마하여 상기 질화막을 노출시키는 단계를 포함한다.The present invention discloses a method for forming metal wiring of a semiconductor device. The method comprises the steps of (a) forming a planarized upper portion of the semiconductor substrate with the gate electrode, the N region and the source / drain electrodes formed; (B) selectively etching the oxide film by photolithography to form contact holes; (C) forming a tungsten plug in the contact hole, and then forming a predetermined metal wire on the tungsten plug; (D) depositing a nitride film over the entire structure; (E) depositing a tungsten film over the entire structure; (F) polishing the tungsten film by a chemical mechanical polishing method to expose the nitride film.
Description
제1도는 종래 기술에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 도면.1 is a view for explaining a metal wiring formation method of a semiconductor device according to the prior art.
제2도 (a) 내지 (c)는 본 발명의 실시예 1에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 도면.2 (a) to 2 (c) are views for explaining a method for forming metal wirings of a semiconductor device according to Embodiment 1 of the present invention.
제3도 (a) 내지 (c)는 실시예 2에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 도면.3A to 3C are diagrams for explaining a method for forming metal wirings of a semiconductor device according to Example 2. FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 11 : 반도체 기판 2, 12 : 게이트 산화막1, 11: semiconductor substrate 2, 12: gate oxide film
3, 13 : 게이트 전극 4, 14 : N 영역3, 13: gate electrode 4, 14: N region
5, 15 : 산화막 스페이서 6, 16 : 드레인 전극5, 15: oxide film spacer 6, 16: drain electrode
6A, 16A : 소오스 전극 7, 17 : 평탄화된 산화막6A, 16A: source electrode 7, 17: planarized oxide film
8, 18 : 텅스텐 플러그 9, 19, (19A) : 금속배선8, 18: tungsten plug 9, 19, (19A): metal wiring
20, 20A : 질화막 21, 21A, 21B : 텅스텐막20, 20A: nitride film 21, 21A, 21B: tungsten film
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 더욱 상세하게는 반도체 소자의 금속배선 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.
현재, 고집적 반도체 소자의 제조에 있어서, 채널과 드레인 전극사이에 형성되는 강한 전장을 분산시키기 위하여 LDD(lightly doped drain)구조를 채용하여 MOSFET를 제조하고 있다.At present, in the manufacture of highly integrated semiconductor devices, MOSFETs are manufactured by adopting a lightly doped drain (LDD) structure to disperse the strong electric field formed between the channel and the drain electrode.
제1도는 종래 기술에 따라, 반도체 소자의 금속배선이 형성된 상태까지를 보여주는 단면도이다. 제1도와 관련하여 종래의 금속배선 형성방법을 설명하면, 우선 반도체 기판(1)상에 소정 두께의 게이트 산화막(2)을 갖는 게이트 전극(3)을 형성하고, N-영역(4), 산화막 스페이서(5), 드레인 전극(6) 및 소오스 전극(6A)을 형성한다. 그리고나서, 콘택홀의 내부에 텅스텐 플러그(8)을 형성한 다음, 소정의 금속배선(9)을 형성하게 된다.1 is a cross-sectional view showing a state in which metal wirings of a semiconductor device are formed according to the related art. Referring to FIG. 1, a conventional metal wiring forming method is described. First, a gate electrode 3 having a gate oxide film 2 having a predetermined thickness is formed on a semiconductor substrate 1, and an N − region 4 and an oxide film are formed. The spacer 5, the drain electrode 6, and the source electrode 6A are formed. Then, the tungsten plug 8 is formed inside the contact hole, and then a predetermined metal wiring 9 is formed.
그러나, 상기의 종래 방법은 외부로부터 유입되는 Na, K 등의 유동전하(mobile charge)를 막기 위해서 드레인 전극(6)에 접속되는 금속배선(9)의 부분의 연장시켜 N영역(4)의 보호막으로 사용되도록 하였지만, 상기 평탄화된 산화막(7)이 노출된 상태에서는 Na, K등과 같은 유동 전하의 차단을 완전하게 이룰 수가 없었다. 따라서, 드레인 전극(6) 주위로 침입한 유동전하는 주위의 강한 전계에 의해 이동함으로써, 결국에는 출력 전류의 저하를 초래하는 문제점이 있었다.However, the conventional method described above extends a portion of the metal wiring 9 connected to the drain electrode 6 so as to prevent mobile charge of Na, K, etc. flowing from the outside, thereby protecting the protective film of the N region 4. However, the planarized oxide film 7 is not exposed, but it is not possible to completely block the flow charge such as Na, K, and the like. Therefore, the flow charge penetrated around the drain electrode 6 is moved by the strong electric field around, resulting in a problem that the output current is lowered eventually.
따라서, 본 발명의 목적은 상기의 종래 기술의 문제점을 해결하기 위하여 안출된 것으로, 유동전하의 침입을 방지함으로써 유동전하로 인한 출력 전류의 저하를 방지할 수 있는 반도체 소자의 금속배선 형성방법을 제공하는 데에 있다.Accordingly, an object of the present invention is to solve the problems of the prior art, to provide a method for forming a metal wiring of a semiconductor device that can prevent the fall of the output current due to the flow charge by preventing the intrusion of the flow charge. It's there.
상기의 목적을 달성하기 위하여, 본 발명의 반도체 소자의 금속배선 형성방법은 제1 특징으로서, (가) 게이트 전극, N-영역 및 소오스/드레인 전극이 형성된 상태의 반도체 기판상부에 평탄화된 산화막을 형성하는 단계; (나) 상기 산화막을 사진 식각법에 의해 선택적으로 식각하여 콘택홀을 형성하는 단계; (다) 상기 콘택홀 내부에 텅스텐 플러그를 형성한 후, 텅스텐 플러그의 상부에 소정의 금속배선을 형성하는 단계; (라) 전체 구조 상부에 질화막을 증착하는 단계; (마) 전체 구조 상부에 텅스텐막을 전면 증착하는 단계; (바) 상기 텅스텐막을 화학-기계 연마법으로 연마하여 상기 질화막을 노출시키는 단계를 포함한다.In order to achieve the above object, a metal wiring forming method of the semiconductor device of the present invention is a first feature, (A) a planarized oxide film on the semiconductor substrate in the state where the gate electrode, the N - region and the source / drain electrode is formed Forming; (B) selectively etching the oxide film by photolithography to form contact holes; (C) forming a tungsten plug in the contact hole and then forming a predetermined metal wire on the tungsten plug; (D) depositing a nitride film over the entire structure; (E) depositing a tungsten film over the entire structure; (F) polishing the tungsten film by chemical-mechanical polishing to expose the nitride film.
또한, 본 발명의 반도체 소자의 금속배선 형성방법은 (가) 게이트 전극, N-영역 및 소오스/드레인 전극이 형성된 상태의 반도체 기판상부에 평탄화된 산화막을 형성하는 단계; (나) 상기 산화막을 사진 식각법에 의해 선택적으로 식각하여 콘택홀을 형성하는 단계; (다) 상기 콘택홀 내부에 텅스텐 플러그를 형성한 후, 텅스텐 플러그의 상부에 소정의 금속배선을 형성하는 단계; (라) 전체 구조상부에 질화막을 증착하는 단계; (마) 상기 드레인 전극에 접속된 금속배선 상부의 질화막 부분을 제외한 나머지 질화막 부분을 사진식각법으로 제거하는 단계; (바) 전체 구조 상부에 텅스텐막을 전면 증착하는 단계; 및 (사) 상기 텅스텐막을 화학-기계 연마법으로 연마하여 상기 질화막 부분을 노출시키는 단계를 포함한다.In addition, the method for forming metal wiring of the semiconductor device of the present invention comprises the steps of: (a) forming a planarized oxide film on the semiconductor substrate in a state where the gate electrode, the N − region and the source / drain electrodes are formed; (B) selectively etching the oxide film by photolithography to form contact holes; (C) forming a tungsten plug in the contact hole and then forming a predetermined metal wire on the tungsten plug; (D) depositing a nitride film over the entire structure; (E) removing the remaining nitride film portion except for the nitride film portion on the upper metal wiring connected to the drain electrode by photolithography; (F) depositing a tungsten film over the entire structure; And (g) polishing the tungsten film by chemical-mechanical polishing to expose the nitride film portion.
본 발명에 의하면, 금속배선 상부에 질화막 및 텅스텐막을 형성함으로서 Na, K등과 같은 유동 전하의 침입을 방지할 수 있다. 따라서, 유동 전하의 침입으로 인한 출력 전류의 저하와 같은 소자의 전기적 특성의 저하가 초래되지 않는다.According to the present invention, by forming a nitride film and a tungsten film on the upper portion of the metal wiring, it is possible to prevent intrusion of flow charges such as Na and K. Thus, no degradation of the electrical characteristics of the device, such as a decrease in the output current due to the intrusion of the flow charge, is caused.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명하기로 하며, 도면에서 동일 부분에 대하여는 동일 도면 부호를 사용하기로 한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, and the same reference numerals will be used for the same parts in the drawings.
[실시예 1]Example 1
제2도는 (a) 내지 (c)는 본 발명의 실시예1에 따른 반도체 소자의 금속배선형성 방법을 설명하기 위한 도면이다.2A to 2C are diagrams for explaining a method for forming metal wirings of a semiconductor device according to Embodiment 1 of the present invention.
우선, 제2도 (a)에서 도시된 바와 같이, 반도체 기판(11)의 상부에 소정 두께의 게이트 산화막(12)을 갖는 게이트 전극(13)을 형성하고, N-영역(14), 산화막 스페이서(15), 드레인 전극(16) 및 소오스 전극(16A)을 통상의 방법에 따라 형성한다. 그런다음, 전체 구조 상부에 화학-기계 연마법에 의한 평탄화된 산화막(17)을 형성하고, 드레인 전극(16) 및 소오스 전극(16A)의 소정 부분이 노출되도록 산화막(17)의 소정 부분을 사진 식각법으로 선택적으로 식각하여 상부전극과 하부 전극간의 전기적 연결을 위한 콘택홀(미도시)을 형성한다. 그런다음, 콘택홀의 내부에 텅스텐 플러그(18)을 형성하고 알루미늄 합금막으로 구성된 소정의 금속배선(19)을 형성한다. 그리고나서, 전체 구조상부에 질화막(20)을 약 500℃이하의 저온에서 약 500~1000Å의 두께로 증착한다.First, as shown in FIG. 2A, a gate electrode 13 having a gate oxide film 12 having a predetermined thickness is formed on the semiconductor substrate 11, and an N − region 14 and an oxide film spacer are formed. (15), the drain electrode 16 and the source electrode 16A are formed in a conventional manner. Then, a planarized oxide film 17 is formed on the entire structure by chemical-mechanical polishing, and a predetermined portion of the oxide film 17 is photographed so that predetermined portions of the drain electrode 16 and the source electrode 16A are exposed. Etching is selectively performed to form a contact hole (not shown) for electrical connection between the upper electrode and the lower electrode. Then, a tungsten plug 18 is formed inside the contact hole, and a predetermined metal wiring 19 made of an aluminum alloy film is formed. Then, the nitride film 20 is deposited on the entire structure at a thickness of about 500 to 1000 Pa at a low temperature of about 500 ° C or less.
이어서, (b)에서 도시된 바와 같이, 전체 구조 상부에 약 3000~7000Å두께의 텅스텐막(21)을 전면 증착한다.Subsequently, as shown in (b), a tungsten film 21 having a thickness of about 3000 to 7000 Å is deposited on the entire structure.
그후, (c)에서 도시된 바와 같이 통상의 화학-기계 연마법으로 질화막(20)의 표면이 노출되도록 텅스텐막(21)을 연마하여 평탄화시킨다.Thereafter, as shown in (c), the tungsten film 21 is polished and planarized so that the surface of the nitride film 20 is exposed by a conventional chemical-mechanical polishing method.
실시예 1에 의하면, 금속배서(19)의 상부에 질화막(20) 및 텅스텐막(21A)을 형성함으로서, K, Na등과 같은 유동 전하가 침입하는 것을 방지할 수 있다.According to the first embodiment, by forming the nitride film 20 and the tungsten film 21A on the metal end 19, it is possible to prevent the inflow of flow charges such as K and Na.
[실시예 2]Example 2
제3도 (a) 내지 (c)는 본 발명의 실시예 2에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 도면이다.3A to 3C are diagrams for explaining a method for forming metal wirings of a semiconductor device according to Embodiment 2 of the present invention.
우선, 제3도 (a)에서 도시된 바와 같이, 반도체 기판(11)의 상부에 소정 두께의 게이트 산화막(12)을 갖는 게이트 전극(13)을 형성하고, N-영역(14), 산화막 스페이서(15), 드레인 전극(16) 및 소오스 전극(16A)을 통상의 방법에 따라 형성한다. 그런다음, 전체구조 상부에 화학-기계 연마법에 의한 평탄화된 산화막(17)을 형성하고, 드레인 전극(16) 및 소오스전극(6A)의 소정 부분이 노출되도록 산화막(17)의 소정부분을 사진 식각법으로 선택적으로 식각하여 상부 전극과 하부 전극간의 전기적 연결을 위한 콘택홀(미도시)을 형성한다.First, as shown in FIG. 3A, a gate electrode 13 having a gate oxide film 12 having a predetermined thickness is formed on the semiconductor substrate 11, and an N − region 14 and an oxide film spacer are formed. (15), the drain electrode 16 and the source electrode 16A are formed in a conventional manner. Then, a planarized oxide film 17 is formed on the entire structure by chemical-mechanical polishing, and a predetermined portion of the oxide film 17 is photographed to expose a predetermined portion of the drain electrode 16 and the source electrode 6A. Etching is selectively performed to form a contact hole (not shown) for electrical connection between the upper electrode and the lower electrode.
그런다음, 콘택홀 내부에 텅스텐 플러그(18)를 형성하고 알루미늄 합금막으로 구성된 소정의 금소배선(19) 및 (19A)을 형성한다. 그리고나서 전체 구조상부에 질화막(20)을 약 500℃이하의 저온에서 약 500~1000Å의 두께로 증착한다.Then, a tungsten plug 18 is formed inside the contact hole, and predetermined copper wirings 19 and 19A made of an aluminum alloy film are formed. Then, the nitride film 20 is deposited on the entire structure at a thickness of about 500 to 1000 Pa at a low temperature of about 500 ° C. or less.
이어서, (b)에서 도시된 바와 같이, 드레인 전극(14)에 접속된 금속배선(19) 상부의 질화막 부분(20A)을 제외한 나머지 질화막 부분을 사진 식각법으로 제거한 다음, 전체 구조 상부에 약 3,000~7000Å의 두께의 텅스텐막(21)을 전면 증착한다.Subsequently, as shown in (b), the remaining portion of the nitride film except for the nitride film portion 20A on the upper portion of the metal wiring 19 connected to the drain electrode 14 is removed by photolithography, and then about 3,000 over the entire structure. A tungsten film 21 having a thickness of ˜7000 mm 3 is deposited on the entire surface.
상부에 소정 두께의 게이트 산화막(12)을 갖는 게이트 전극(13)을 형성하고, N-영역(14), 산화막 스페이서(15), 드레인 전극(16) 및 소오스 전극(16A)을 통상의 방법에 따라 형성한다. 그런다음, 전체구조 상부에 화학-기계 연마법에 의한 평탄화된 산화막(17)을 형성하고, 드레인 전극(16) 및 소오스 전극(16A)의 소정부분이 노출되도록 산화막(17)의 소정부분을 사진식각법으로 선택적으로 식각하여 상부전극과 하부 전극간의 전기적 연결을 위한 콘택홀(미도시)을 형성한다.A gate electrode 13 having a gate oxide film 12 having a predetermined thickness is formed thereon, and the N − region 14, the oxide spacer 15, the drain electrode 16, and the source electrode 16A are formed in a conventional method. To form. Then, a planarized oxide film 17 is formed on the entire structure by chemical-mechanical polishing, and a predetermined portion of the oxide film 17 is photographed so that predetermined portions of the drain electrode 16 and the source electrode 16A are exposed. Etching is selectively performed to form a contact hole (not shown) for electrical connection between the upper electrode and the lower electrode.
그런다음, 콘택홀 내부에 텅스텐 플러그(18)를 형성하고 알루미늄 합금막으로 구성된 소정의 금속배선(19) 및 (19A)을 형성한다. 그리고나서, 전체 구조 상부에 질화막(20)을 약 500℃이하의 저온에서 약 500~1000Å의 두께로 증착한다.Then, a tungsten plug 18 is formed inside the contact hole, and predetermined metal wirings 19 and 19A made of an aluminum alloy film are formed. Then, the nitride film 20 is deposited on the entire structure at a thickness of about 500 to 1000 Pa at a low temperature of about 500 ° C. or less.
이어서, (b)에서 도시된 바와 같이 드레인 전극(14)에 접속된 금속배선(19)상부의 질화막 부분(20A)을 제외한 나머지 질화막 부분을 사진 식각법으로 제거한 다음, 전체 구조상부에 약 3000~7000Å의 두께의 텅스텐막(21)을 전면 증착한다.Subsequently, as shown in (b), the remaining nitride film portion except for the nitride film portion 20A on the upper portion of the metal wiring 19 connected to the drain electrode 14 is removed by photolithography, and then about 3000 to about the entire structure. The tungsten film 21 having a thickness of 7000 kPa is deposited on the entire surface.
그후, (c)에서 도시된 바와 같이, 질화막(20A)의 표면이 노출되도록 통상의 화학-기계 연마법으로 텅스텐막을 연마하여 평탄화시킨다.Thereafter, as shown in (c), the tungsten film is polished and planarized by a conventional chemical-mechanical polishing method so that the surface of the nitride film 20A is exposed.
실시예 2에 의하면, 금속배선(19)의 상부에는 질화막(20A)을 형성하고, 금속배선(19A) 및 산화막(17)의 노출부위에는 텅스텐막(21B)를 형성함으로써, K, Na등과 같은 유동 전하가 침입하는 것을 방지할 수 있다. 따라서, 소자의 전기적 특성을 개선시킬 수 있다.According to the second embodiment, the nitride film 20A is formed on the metal wiring 19, and the tungsten film 21B is formed on the exposed portions of the metal wiring 19A and the oxide film 17, such as K, Na, or the like. It is possible to prevent the inflow of flow charges. Therefore, the electrical characteristics of the device can be improved.
또한, 본 발명은 상기의 실시예들로 한정되는 것은 아니면, 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention is not limited to the said Example, It can implement in various changes in the range which does not deviate from the summary.
Claims (8)
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