KR0170700B1 - Nand-type non-volatile memory device - Google Patents

Abstract

In a nonvolatile memory device having a cell array structure of NAND type, a NAND type nonvolatile memory cell having a minimum cell string current distribution is disclosed. The present invention adjusts the width and length of the ground select transistor appropriately, that is, the current driving force of the ground select transistor is equal to the current when the current in the drain region of the ground select transistor is minimized according to the state of each memory cell. By adjusting a little higher than this, the distribution of cell current can be made uniform without reducing string current. As a result, it is possible to reduce the malfunction of the data and to reduce the sensing time of the data, thereby improving the performance of the device.

Description

NAND Nonvolatile Memory Devices

1 is a plan view of a NAND type memory cell according to the prior art.

FIG. 2 is an equivalent circuit diagram of the NAND type memory cell of FIG.

3 is a plan view of a NAND type memory cell according to an embodiment of the present invention.

4 is a plan view of a NAND memory cell according to another embodiment of the present invention.

5A is a graph showing the cell string current according to the data state according to the prior art.

5B is a graph showing the cell string current according to the data state according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device having a NAND type structure of a cell array of a semiconductor memory device, and more particularly, to a NAND type nonvolatile memory cell having a minimum cell string current distribution.

Non-volatile memory device, for example, the cell array structure of flash EEPROM is divided into NOR type and NAND type, NOR type structure is disadvantageous for high integration, while high cell current has the advantage of easy high speed, and NAND type structure is highly integrated. It is generally known that there is an advantage in terms of speeding up due to the low cell current.

In a typical NAND cell structure, a plurality of cell transistors and select transistors are connected in series between a bit line and a source line to form one string. A plan view of a memory cell having such a structure is shown in FIG. 1, and an equivalent circuit diagram thereof is shown in FIG. 2 (Ref. A New Nand Cell for Ultra High Density 5V-only EEPROMs, Symposium on VLSI Tech. Digest. 1988, pp. 33-34).

The memory cell includes a string select transistor SSL11 for selecting a string in one bit line contact BC1, N cell transistors M11... Mn1 connected to respective word lines, and a ground (or Ground select transistors GSL11 for selecting the source are connected in series via active.

In addition, each of the memory cell transistors M11... Mn1 has a structure in which a floating gate and a control gate are stacked, and data storage and erasing are performed to inject or remove electrons into the floating gate. It is possible by. On the other hand, the state reading of the cell detects whether the cell is on or off by sensing the current of the cell according to the change of the threshold voltage seen at the control gate according to the charge injected into the floating gate.

Each memory cell has a different threshold voltage (typically about -3V for on-cell and + 1V for off-cell) according to data, and according to the characteristics of the memory cell even if they have the same data (on or off). It will have a slightly different threshold voltage. The reading of the NAND cell in which N memory cell transistors are connected in series is performed in units of bit lines. For example, in FIG. 1, in order to read the state of the memory cell M31, a voltage specific to the bit line BL1 connected to the memory cell is read. (For example, VCC or VCC / 2, etc.), a word line connected to the gate of the string select transistor SSL11, the control gate of the unselected cell (except for the cell cell M31), and the gate of the ground select transistor GSL11. When VCC is applied and 0V is applied to the word line of the selection cell M31, all the portions except the selection cell are turned on, so that when the selection cell is off, no current flows in the bit line. Current flows and data is read by sensing the current at this time.

However, in the NAND type cell, since N memory cells are connected in series between the bit line and the ground line, the difference in the current flowing through the bit line varies depending on the state of each memory cell threshold voltage.

For example, when the cell connected to the bit line BL1 is on only in case of M11 and the remaining cells are off, and when all the cells are on, a significant difference occurs between the current flowing through the bitline.

As can be easily seen from the graph of FIG. 5A in which the cell string current difference is actually measured according to the data state, it can be seen that the maximum string current difference according to the data state is about 10 mA or more.

The cell string current difference causes the following problem.

In general, in a sensing operation of determining a state of a memory cell, a specific voltage is charged in a bit line, so that when the cell is read during the read operation of the cell, the bit line level does not change. When the cell is read, current flows to ground, which lowers the bitline level. Therefore, the sense amplifier senses such a voltage difference. Typically, when a change in the bit line level after a specific time elapses is smaller than ΔVBL determined as a reference, the sense cell is sensed as an off cell. Therefore, the large current difference for each cell string means that ΔVBL is over a wide range. For example, when ΔVBL is 0.1V to 0.5V, when the sensing is based on ΔVBL = 0.3V, the on cell is turned off. There is a problem of incorrect detection with a cell. In addition, when the sensing margin is set to ΔVBL = 0.5V to prevent malfunction, the sensing speed may be slowed because a large amount of time must pass before the bit line level of the cell string through which the current flows is small is 0.5V or less. .

Ideally, if the cell string current is constant regardless of the state of the memory cell, malfunctions can be prevented and sensing speed can be increased by sensing? VBL at a small value.

Another problem caused when the current difference occurs is a conventional non-volatile device has a process of verifying when storing / erasing data to prevent over erasing and over program.

In other words, it is to check whether the data storage and erasing has been normally performed. This program / erases a predetermined time and reads the state of the cell in the same operation as the read time. Since the reference of this reading is also determined by the current, the string cell through which a large amount of current flows when the specific cell is programmed is determined to be not programmed at the time of verification, and the program is continuously executed, thereby over-programming.

In particular, in the case of a flash memory which writes data several times in units of pages without erasing a back pattern (each cell program state connected to a string), each memory cell This is a factor of increasing the threshold voltage distribution, and as a result, a vicious cycle in which the current difference of the cell string increases as the distribution of the threshold voltage increases, causes the aforementioned problems to accumulate.

Therefore, ideally, a constant cell string current flows irrespective of the threshold voltage of the memory cell transistor connected to one string, and the present invention is based on the change in the data state and threshold voltage of the memory cell, which is a problem of the prior art. In order to provide a NAND type nonvolatile memory device which solves the problem of degrading the performance of the device by increasing the cell current dispersion causing a malfunction of the memory cell or increasing the sensing speed and increasing the threshold voltage distribution of the memory cell. It is.

An object of the present invention is to provide a NAND type nonvolatile memory device capable of improving device performance by minimizing a string current difference of a cell according to a data state.

The NAND type nonvolatile memory device of the present invention for achieving the above object is a plurality of string selection transistors for selecting a specific cell, a plurality of pairs of memory cell transistors for data storage, and a defect in the standby state ( ground selection transistors for relief are configured in series circuits between the bit line and the ground voltage terminal, and the width of the ground selection transistor is configured to have a width smaller than that of the string selection transistor. It features.

According to another aspect of the present invention, a NAND type nonvolatile memory cell includes a plurality of string select transistors for selecting a specific cell, a plurality of memory cell transistors for data storage, and a fail relief in a standby state. The ground selection transistors are configured in series circuits between the bit line and the ground voltage terminal, and the gate length of the ground selection transistor is longer than the gate length of the string selection transistor.

According to a preferred embodiment of the present invention, the string current is adjusted by appropriately adjusting the width and length of the ground select transistor, that is, by adjusting the current at the drain region of the ground select transistor to a minimum or slightly higher than that. The cell current distribution can be made uniform without lowering Therefore, the malfunction of the data and the sensing time of the data are reduced, thereby improving the performance of the device.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a plurality of memory cell transistors in the string select transistor and the memory device, the amount of current injected into the bit line to maintain a constant amount of current flowing from the bit line to ground regardless of the respective memory cell state and threshold voltage Without limiting, the width of the ground select transistor is set to be narrower than the width of the string select transistor so that the ground select transistor located at the last stage of the current passing through each memory cell transistor is limited to the limit current. The gate length of the ground select transistor is longer than that of the string select transistor.

1 and 2, the width WSL of the string select transistor connected to the selected bit line and the width WGL of the ground select transistor are the same, so that the current driving capability of the two transistors is the same.

Accordingly, the amount of current passing through the select transistors in the different bit lines BL1 and BL2 is the same at the nodes S1 and S2, but when the data is different when passing through the memory cell transistor, the channel resistance according to the threshold voltage of the memory cell is different. The effect is that the amount of current reaching the G1 and G2 nodes will be different. As a result, the current amounts at the G1 and G2 nodes are smaller than the S1 and S2 nodes and differ from each other.

Therefore, the current flowing through the ground selection transistor whose current driving force is the same as that of the string selection transistor and flowing to ground is G1, and the current difference seen from the bit lines BL1 and BL2 is not limited to the ground selection transistor. It is equal to the current difference at the G2 node.

On the other hand, referring to the plan view of FIG. 3 showing the first embodiment of the present invention, the NAND type nonvolatile memory cell according to the present invention has the width WSL of the string select transistor and the width WGL of the ground select transistor. Configured differently.

In the case of the present invention, since the equivalent circuit diagram is the same as that of FIG. 2, the current reaching G1 and G2 is limited by the ground selection transistor, so that the difference in the current reaching the ground is reduced, as in the aforementioned conventional technique. Lift or become constant.

For example, when the current corresponding to 10 flows in each of the bit lines BL1 and BL2 and the amount of current reaching G1 and G2 is 9 and 5, respectively, according to the state of the memory cell, the current driving force of the ground selection transistor is Since it is 10, the amount of current reaching ground will be 9 and 5, respectively. On the other hand, when the current driving force of the ground select transistor is 5 as in the present invention, the amount of current reaching the ground will be equal to 5 and 5, respectively.

4 is a plan view illustrating another embodiment of the present invention, and unlike the first embodiment, the gate length LGL of the ground select transistor and the gate length LSL of the string select transistor are different from each other (ie, LGLLSL). .

Also in the case of this embodiment, it becomes possible to reduce the spread of the cell string current.

The effect of the present invention will be further clarified by the graph of FIG. 5, which summarizes the simulated data of cell string current distribution according to the state of the data.

FIG. 5A shows a string current scatter diagram according to a data state according to the prior art, and FIG. 5B shows a string current scatter diagram according to the present invention, and it can be seen that the string current difference in the memory cell according to the present invention is significantly reduced.

As described above, according to the present invention, the width and length of the ground select transistor are properly adjusted, that is, the current driving force of the ground select transistor is minimized according to the state of each memory cell. By adjusting the current at or slightly higher than the current, it is possible to make the distribution of the cell current uniform without lowering the string current. As a result, it is possible to reduce the malfunction of the data and to reduce the sensing time of the data, thereby improving the performance of the device.

Claims (6)

A plurality of string select transistors for selecting a specific cell, a plurality of memory cell transistors for data storage, and ground selection transistors for fail relief in a standby state include a bit line and a ground voltage terminal. And a NAND type nonvolatile memory device, wherein the NAND type nonvolatile memory device is configured to have a width smaller than that of the string select transistor. The NAND type nonvolatile memory device of claim 1, wherein the width of the ground select transistor is about 0.1 μm to about 0.2 μm smaller than the width of the string select transistor. The NAND type nonvolatile memory device of claim 1, wherein a current driving force of the ground select transistor is smaller than a current driving force of the string select transistor. A plurality of string select transistors for selecting a specific cell, a plurality of memory cell transistors for data storage, and ground selection transistors for fail relief in a standby state include a bit line and a ground voltage terminal. NAND type non-volatile memory device, characterized in that formed in a series circuit between each other, the gate length (Length) of the ground select transistor is longer than the gate length of the string select transistor. The nonvolatile memory device of claim 4, wherein a gate length of the ground select transistor is about 0.1 to 0.2 μm longer than a gate length of the string select transistor. The nonvolatile memory device of claim 4, wherein a current driving force of the ground select transistor is smaller than a current driving force of a string select transistor.