KR100894788B1 - Programming method and erasing method of non volatile memory device - Google Patents

Abstract

A programming method and erasing method of a non-volatile memory device is provided to increase the reliability of the memory device without increase of erase voltage by compensating for the difference of program speed and erase speed. The gate length of memory cells(510,530) positioned in the end part of a cell string is set to be shorter than the gate length of the memory cell(520) positioned at the central part of the cell string. The first program start voltage in relation to the memory cells positioned in the central part of the cell string is set. The second program start voltage in relation to the memory cell positioned in the end part of the cell string is set. The second program start voltage is higher than that of the first program.

Description

Programming method and erasing method of non volatile memory device

The present invention relates to an improved program method and an erase method of a nonvolatile memory device.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The cell of the nonvolatile memory device may be programmed and erased according to a potential difference applied to the floating gate. In other words, when a strong electric field is applied to the thin tunnel oxide film of about 80 kHz, the program or erase operation occurs by the FN tunneling operation.

On the other hand, these cells are manufactured to have the same characteristics, but a difference occurs in the program speed or the erase speed depending on the location thereof. In particular, in the cell string, the neighboring cells of the drain select transistor or the source select transistor have a difference in program speed or erase speed due to the difference in parasitic capacitance.

Measures to compensate for such a difference are being performed, but this measure increases the erase voltage, which causes a problem in that reliability is deteriorated.

In order to solve the above-mentioned problems, it is an object of the present invention to provide a program method and an erase method in which the program speed or the erase speed of the cells positioned at the end of the cell string are not decreased while the erase voltage is reduced.

A method of programming a nonvolatile memory device of the present invention for achieving the above object is the step of providing a nonvolatile memory device in which the original threshold voltage of the cells located at the end of the cell string is lower than the original threshold voltage located at the center of the cell string And setting a first program start voltage for the cells located at the center of the cell string and setting a second program start voltage greater than the first program start voltage for the cells located at the end of the cell string. Characterized in that it comprises a step.

In addition, the erase method of the nonvolatile memory device of the present invention provides a nonvolatile memory device in which the original threshold voltage of the cells located at the end of the cell string is lower than the original threshold voltage located at the center of the cell string, and Compensating for a voltage equal to the erase rate difference between cells located at the center of the cell string and cells located at the distal end of the cell string, and lowered original threshold of cells for the end of the cell string with respect to the compensated erase voltage. And reducing and setting the erase voltage by the voltage, and erasing all cells according to the set erase voltage.

According to the above-described configuration of the present invention, while compensating for the difference between the program speed and the erase speed of cells located at the end of the cell string, the entire erase voltage is not greatly increased, thereby improving reliability of the nonvolatile memory device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

FIG. 1A illustrates a voltage application condition during a program operation for a cell string of a conventional nonvolatile memory device, and FIG. 1B illustrates a voltage application condition during an erase operation.

First, the configuration of the cell string will be briefly described. The unit memory cell includes one control gate C.G and one floating gate F.G, and each control gate receives a voltage of a word line.

A plurality of such memory cells (32 in the figure) are connected in series to form one cell string. On the other hand, a drain select transistor DST for selectively connecting the cell string and the bit line and a source select transistor SST for selectively connecting the cell string and the common source line are connected to the end of the cell string. In this case, the drain select transistor and the source select transistor are composed of a general MOS transistor.

The voltage condition applied during the program operation will be described.

The program operation is typically performed in units of pages including a plurality of cells connected to a specific cell in a word line direction. Therefore, a high voltage (18V) is applied to the word line WL1 connected to the page including the cell to be programmed, and a relatively low pass voltage (for the word line (rest word line) connected to the page not to be programmed). 10V), and a voltage of 0V is applied to the P well. In addition, the source select transistor is turned off to disconnect the common source line and the cell string, and the drain select transistor is turned on to apply the data applied to the bit line to the cell string.

According to such a configuration, the high voltage is applied only to the page including the cell to be programmed. Accordingly, FN tunneling occurs to perform a program operation in which charge is charged to the floating gate.

The erase operation will now be described with reference to FIG. 1B.

The erase operation is typically done for the entire block. Therefore, the same low level voltage (0V) is applied to all word lines. On the other hand, a high voltage of 20V is applied to the P well. As a result, FN tunneling occurs and an erase operation occurs in which all charges charged to the floating gate are released.

On the other hand, the numerical values set forth above are provided for ease of understanding and do not limit the content of the present invention.

In addition, the voltage condition is only one example, and may vary continuously according to the embodiment. For example, this is the case with the Incremental Step Pulse Program (ISPP) program method or the Incremental Step Pulse Erase (ISPE) erase method.

On the other hand, the illustrated case is shown to operate only by coupling between the ONO (oxide / nitride / oxide) and the tunnel oxide (Tunnel Oxide, Tox) capacitance of the ideal flash cell, the parasitic capacitance actually exists.

2A to 2D are diagrams showing parasitic capacitances in a program / erase operation of a conventional nonvolatile memory device.

FIG. 2A shows parasitic capacitance occurring in a cell adjacent to the source select transistor during a program operation. Parasitic capacitance C1 generated between the floating gate of the cell WL0 and the control gate of the adjacent cell WL1, parasitic capacitance C2 generated between the floating gate of the cell WL0 and the floating gate of the adjacent cell WL1, The parasitic capacitance C5 occurring between the floating gate of the cell WL0 and the source select transistor is shown.

The parasitic capacitances appear almost the same in the cell adjacent to the drain select transistor.

2B illustrates parasitic capacitances occurring in typical cells during program operation. Parasitic capacitance C1 generated between the floating gate of the cell WLn and the control gate of the adjacent cell WLn + 1, and parasitic capacitance generated between the floating gate of the cell WLn and the floating gate of the adjacent cell WLn + 1. (C2), between the parasitic capacitance C3 occurring between the floating gate of the cell WLn and the control gate of the adjacent cell WLn-1, between the floating gate of the cell WLn and the floating gate of the adjacent cell WLn-1. The parasitic capacitance C4 that occurs at is shown.

FIG. 2C illustrates parasitic capacitance occurring in a cell adjacent to the source select transistor during an erase operation, and the parasitic capacitance of the same type as that of FIG. 2A is generated.

FIG. 2D illustrates parasitic capacitance occurring in a typical cell during an erase operation, and the parasitic capacitance of the same type as that of FIG. 2B is generated.

Considering such parasitic capacitance, it is known that the voltage applied to the tunnel oxide film is determined by the following equation.

Equation 1 is a formula for obtaining a voltage applied to a tunnel oxide film of a cell adjacent to a source select transistor or a drain select transistor.

Equation 2 is a formula for obtaining a voltage applied to the tunnel oxide film of a conventional cell.

On the other hand, the voltage applied to the tunnel oxide film during the program and erase operations is obtained by substituting a value necessary for calculating the above equation.

FIG. 3A is a table showing values of capacitances and parasitic capacitances of the ONO film and the tunnel oxide film that existed originally. FIG. 3B is a diagram illustrating voltages applied to each node and voltages applied to the tunnel oxide film during program and erase operations. Table.

As a result, in the program operation, the voltage applied to the tunnel oxide film of the cell adjacent to the source select transistor (or the drain select transistor) is 8.4V, but the voltage applied to the tunnel oxide film of the other cell is 8.7V. As a result of this difference, the program speed of the cell adjacent to the source select transistor (or drain select transistor) is slower than that of other cells. According to the above numerical value, it is known that a difference of about 0.6V appears.

In the erase operation, the voltage applied to the tunnel oxide film of the cell adjacent to the source select transistor (or drain select transistor) is 10V, but the voltage applied to the tunnel oxide film of the other cell is 9V. As a result of this difference, the erase speed of the cell adjacent to the source select transistor (or drain select transistor) is slower than that of other cells. According to the above numerical value, it is known that a difference of about 2V appears.

In order to compensate for such a difference in program speed and erase speed, a method of increasing the original threshold voltage (UV vt or natural vt) of a cell adjacent to a source select transistor or a drain select transistor is known compared to a neighboring cell.

In this case, the original threshold voltage is ideally 0V as a threshold voltage without any charge in the floating gate.

Originally, the method of increasing the threshold voltage has a method of increasing the gate length of the cell compared to the neighboring cells. For example, increase the threshold voltage by 0.6V to compensate for program speed.

However, this method has the following problems.

In the case of a nonvolatile cell, the deterioration of the cell occurs when the program / erase operation is performed. As a result, the program / erase operation characteristic or the data retention characteristic is deteriorated. However, this deterioration phenomenon is closely related to the erase voltage.

4 is a graph illustrating a change state of a threshold voltage according to an erase voltage during a program / erase operation.

As can be seen from the graph, it can be seen that the change of the threshold voltage increases as the erase voltage increases, and accordingly, the data retention characteristic deteriorates rapidly.

On the other hand, in the case of a cell adjacent to the source select transistor or the drain select transistor, when the original threshold voltage is increased by 0.6V to compensate for the program speed difference, the erase speed is reduced by up to 2.6V. The erase voltage should be increased.

As such, since the erase voltage is increased, reliability characteristics are deteriorated.

In order to solve the above-mentioned problem, it is necessary to select a configuration that can lower the total erase voltage.

To this end, the present invention proposes a method of lowering the original threshold voltage of the cells adjacent to the source select transistor or the drain select transistor. However, in this case, there is a problem in that the program speed of the corresponding cells is slowed. Therefore, in order to solve the problem, a method of increasing the program start voltage during ISPP programming of the corresponding cells is also used in parallel.

First, a method of lowering an original threshold voltage of cells adjacent to the source select transistor or the drain select transistor will be described in detail.

The first method is to shorten the gate length of the cell.

5 is a cross-sectional view illustrating a cell string structure according to an embodiment of the present invention.

As shown, the gate length w0 of the cell 510 adjacent to the source select transistor and the gate length w31 of the cell 530 adjacent to the drain select transistor are equal to each other and smaller than the gate lengths of the remaining cells 520.

Ideally, we have the following mathematical relationship:

w0 = w31 <w1 = w2 ..... = w30

If the gate length is shortened, its slope increases in the Vg-Id characteristic, thereby reducing the original threshold voltage.

In this case, the gate lengths of the cells 510 and 530 correspond to 50 to 95% of the gate lengths of the other cells.

In addition, the reduction amount of the original threshold voltage is set to 0.1 ~ 3.0V. That is, the original threshold voltages of the cells 510 and 530 are -3.0 to -0.1V.

As such, as the original threshold voltages of the cells 510 and 530 are lowered, the total erase voltage is lowered. That is, as the original threshold voltage is lowered, the overall erase voltage is lowered.

In this state, the program start voltage is further increased for the cells 510 and 530 during the program operation.

Preferably, a program start voltage further increased by 0.2 to 6.0 V corresponding to twice the decrease amount of the original threshold voltage is applied.

Or as another embodiment, it is configured to have the following relationship.

w0 <w31 <w1 = w2 ..... = w30

In general, when the cells adjacent to the drain select transistor are programmed, the cells below the cell have a high probability of being programmed, and therefore, these cells have a slightly lower programming speed than the source select transistor and the adjacent cells. To compensate for this, the gate length of the cells adjacent to the drain select transistor is made longer than the gate length of the cells adjacent to the source select transistor.

The second method further reduces the amount of impurity implanted into the channel region for cells adjacent to the source select transistor and cells adjacent to the drain select transistor.

A group 3 element, such as B or BF3, is injected into the N-type memory cell, and a group 5 element, such as P, is injected into the P-type memory cell.

Preferably, impurities are first injected into the channel region of the entire cell, and additional impurities are sequentially added to the remaining regions except for the memory cell 510 adjacent to the source select transistor and the memory cell 530 adjacent to the drain select transistor. Inject

By such a configuration, the reduction of the original threshold voltage is 0.1 to 3.0V. That is, the original threshold voltage of the memory cell 510 adjacent to the source select transistor and the memory cell 530 adjacent to the drain select transistor is set to be -3.0 to -0.1V.

As such, as the original threshold voltage is lowered, the total erase voltage is lowered. That is, as the original threshold voltage is lowered, the overall erase voltage is lowered.

In this state, the program start voltage is further increased to be applied to the memory cell adjacent to the source select transistor and the memory cell adjacent to the drain select transistor during a program operation.

Preferably, a program start voltage further increased by 0.2 to 6.0 V corresponding to twice the decrease amount of the original threshold voltage is applied.

FIG. 1A illustrates a voltage application condition during a program operation for a cell string of a conventional nonvolatile memory device, and FIG. 1B illustrates a voltage application condition during an erase operation.

2A to 2D are diagrams showing parasitic capacitances in a program / erase operation of a conventional nonvolatile memory device.

FIG. 3A is a table showing values of capacitances and parasitic capacitances of the ONO film and the tunnel oxide film that existed originally, and FIG. 3B is a table of voltages applied to the nodes and voltages applied to the tunnel oxide film during program and erase operations. to be.

4 is a graph illustrating a change state of a threshold voltage according to an erase voltage during a program / erase operation.

5 is a cross-sectional view illustrating a cell string structure according to an embodiment of the present invention.

Claims (6)

Setting the gate length of the memory cells positioned at the end of the cell string to be shorter than the gate length of the memory cells positioned at the center of the cell string; Set a first program start voltage for memory cells located at the center of the cell string, and set a second program start voltage greater than the first program start voltage for memory cells located at the end of the cell string. And programming a nonvolatile memory device. Setting the amount of impurities doped in the memory cells located at the end of the cell string to be less than the amount of impurities doped in the memory cells located at the center of the cell string; Set a first program start voltage for memory cells located at the center of the cell string, and set a second program start voltage greater than the first program start voltage for memory cells located at the end of the cell string. And programming a nonvolatile memory device. Providing a nonvolatile memory device in which an original threshold voltage of memory cells positioned at an end of a cell string is lower than an original threshold voltage of memory cells positioned at a center of the cell string; Compensating for the erase voltage by the erase speed difference between the memory cells positioned at the center of the cell string and the memory cells positioned at the distal end of the cell string; Reducing and setting the erase voltage by the lowered original threshold voltage of the memory cells for the distal end of the cell string with respect to the compensated erase voltage; And erasing all memory cells according to the set erase voltage. The method of claim 3, wherein the providing of the nonvolatile memory device comprises setting the gate length of the memory cells positioned at the distal end of the cell string to be shorter than the gate length of the memory cells positioned at the center of the cell string. A method of erasing a nonvolatile memory device. The method of claim 3, wherein the providing of the nonvolatile memory device comprises setting the amount of impurities doped in the memory cells positioned at the distal end of the cell string to be less than the amount of the impurities doped in the memory cells positioned at the center of the cell string. Erasing method of a nonvolatile memory device comprising a. A nonvolatile memory device in which a gate length of a memory cell adjacent to a source select transistor is shorter than a gate length of a memory cell adjacent to a drain select transistor, and a gate length of the memory cells is shorter than a gate length of memory cells positioned at the center of a cell string. The steps provided, Set a first program start voltage for memory cells positioned in the center of the cell string, and set a second program start voltage greater than the first program start voltage for memory cells adjacent to the drain select transistor, and the source. And setting and programming a third program start voltage greater than the second program start voltage for a memory cell adjacent to a selection transistor.

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