KR970029867A - NAND Nonvolatile Memory Devices - Google Patents
NAND Nonvolatile Memory Devices Download PDFInfo
- Publication number
- KR970029867A KR970029867A KR1019950040257A KR19950040257A KR970029867A KR 970029867 A KR970029867 A KR 970029867A KR 1019950040257 A KR1019950040257 A KR 1019950040257A KR 19950040257 A KR19950040257 A KR 19950040257A KR 970029867 A KR970029867 A KR 970029867A
- Authority
- KR
- South Korea
- Prior art keywords
- select transistor
- nonvolatile memory
- ground
- memory device
- nand type
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
셀 어레이(Cell Array)의 구조가 낸드(NAND)형으로 구성된 불휘발성 메모리 장치에서, 셀 스트링 잔류산포를 최소화한 낸드형 불휘발성 메모리 셀이 개시된다. 본 발명은 접지 선택 트랜지스터의 폭과 길이를 적절히 조절하여, 다시 말해 전비 선택 트랜지스터의 잔류 구동력을 각각의 메모리 셀의 상태에 따라 접지 선택 트랜지스터의 드레인 영역의 전류가 최소로 되는 때의 전류와 같거나 이보다는 조금 높게 조절함으로써, 스트링 전류를 저하시키지 않으면서 셀 전류의 분포를 균일하게 할 수 있다. 그 결과, 데이터의 오동작을 줄이고 데이터의 센싱 시간을 감소시켜 소자의 성능을 향상시키는 효과를 발휘한다.In a nonvolatile memory device having a cell array structure of a NAND type, a NAND type nonvolatile memory cell in which cell string residual dispersion is minimized is disclosed. The present invention adjusts the width and the length of the ground select transistor appropriately, that is, the residual driving force of the power select transistor is equal to the current when the current in the drain region of the ground select transistor is minimized according to the state of each memory cell. By adjusting a little higher than this, the distribution of cell current can be made uniform without reducing string current. As a result, it is possible to reduce the malfunction of the data and to reduce the sensing time of the data, thereby improving the performance of the device.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제3도는 본 발명의 일실시예에 의한 NAND형 메모리 셀의 평면도이다.3 is a plan view of a NAND type memory cell according to an embodiment of the present invention.
제4도는 본 발명의 다른 실시예에 의한 NAND형 메모리 셀의 평면도이다.4 is a plan view of a NAND memory cell according to another embodiment of the present invention.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950040257A KR0170700B1 (en) | 1995-11-08 | 1995-11-08 | Nand-type non-volatile memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950040257A KR0170700B1 (en) | 1995-11-08 | 1995-11-08 | Nand-type non-volatile memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970029867A true KR970029867A (en) | 1997-06-26 |
KR0170700B1 KR0170700B1 (en) | 1999-03-30 |
Family
ID=19433369
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950040257A KR0170700B1 (en) | 1995-11-08 | 1995-11-08 | Nand-type non-volatile memory device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0170700B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100894788B1 (en) * | 2007-11-30 | 2009-04-24 | 주식회사 하이닉스반도체 | Programming method and erasing method of non volatile memory device |
-
1995
- 1995-11-08 KR KR1019950040257A patent/KR0170700B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100894788B1 (en) * | 2007-11-30 | 2009-04-24 | 주식회사 하이닉스반도체 | Programming method and erasing method of non volatile memory device |
Also Published As
Publication number | Publication date |
---|---|
KR0170700B1 (en) | 1999-03-30 |
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