KR0170478B1 - Fabrication method of metal wire by multiple annealing method - Google Patents
Fabrication method of metal wire by multiple annealing method Download PDFInfo
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- KR0170478B1 KR0170478B1 KR1019950051474A KR19950051474A KR0170478B1 KR 0170478 B1 KR0170478 B1 KR 0170478B1 KR 1019950051474 A KR1019950051474 A KR 1019950051474A KR 19950051474 A KR19950051474 A KR 19950051474A KR 0170478 B1 KR0170478 B1 KR 0170478B1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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Abstract
본 발명은 반도체 제조공정에서 다중열처리에 의한 금속배선의 형성방법에 관한 것이다.The present invention relates to a method of forming metal wiring by multiple heat treatment in a semiconductor manufacturing process.
좀 더 구체적으로, 본 발명은 반도체 제조공정에서 증착된 금속막에 대해 다중열처리를 수행하여 금속배선이 받는 스트레스를 완화시킴으로써, 금속 배선의 수명을 연장시킬 수 있는 금속배선의 형성방법에 관한 것이다.More specifically, the present invention relates to a method of forming a metal wiring that can extend the life of the metal wiring by reducing the stress applied to the metal wiring by performing a multiple heat treatment on the metal film deposited in the semiconductor manufacturing process.
본 발명의 금속 선 형성방법은, 반도체 소자 제조공정에서 실리콘 기판 위에 산화막을 성장시키고 금속막을 증착시킨 후 열처리에 의해 금속 배선을 형성하는 방법에 있어서, 상기한 금속막을 1차 열처리온도(T1)인 420~460℃에서 1차 열처리한 후, 상기한 1차 열처리온도(T1)보다 낮은 열처리 온도 (T2) 에서 2차 이상의 다중 열처리를 수행하는 것을 특징으로 한다.The metal line forming method of the present invention is a method of forming a metal wiring by growing an oxide film on a silicon substrate and depositing a metal film in a semiconductor device manufacturing process and then heat treatment, wherein the metal film is subjected to a primary heat treatment temperature (T 1 ). After the first heat treatment at 420 ~ 460 ℃ is characterized in that the second or more multiple heat treatment at a heat treatment temperature (T 2 ) lower than the first heat treatment temperature (T 1 ).
Description
제 1도는 본 발명의 금속배선 형성공정에 대한 전체적인 공정도.1 is a general process diagram for the metallization process of the present invention.
본 발명은 반도체 제조공정에서 다중열처리에 의한 금속배선의 형성방법에 관한 것이다.The present invention relates to a method of forming metal wiring by multiple heat treatment in a semiconductor manufacturing process.
좀 더 구체적으로 , 본 발명은 반도체 제조공정에서 증착된 금속막에 대해 다중열처리를 수행하여 금속배선이 받는 스트레스를 완화시킴으로써, 금속 배선의 수명을 연장시킬 수 있는 금속배선의 형성방법에 관한 것이다.More specifically, the present invention relates to a method of forming a metal wiring that can extend the life of the metal wiring by performing a multi-thermal treatment on the metal film deposited in the semiconductor manufacturing process to relieve the stress of the metal wiring.
통상적으로 금속배선을 형성하기 위해서는 실리콘 기판 위에 산화막을 성장시키고 금속막을 증착시킨 후, 금속배선 식각용 메탈마스크(metal mask)로 금속배선을 정의하는 과정을 거친다.In general, in order to form a metal wire, an oxide film is grown on a silicon substrate, a metal film is deposited, and then a metal wire is defined by a metal mask for etching the metal wire.
이렇게 형성된 금속배선은 단지 산화막 위에 금속막이 얹혀있는 상태로서 접착력이 좋지 않기 때문에, 접착력을 향상시키기 위하여 금속막 증착후 약 420℃이상의고온에서 1회의 열처리(annealing)과정을 필수적으로 거치게 된다.The metal wiring thus formed has only a metal film on the oxide film, and thus the adhesion is not good. Therefore, in order to improve the adhesion, the metal wiring is essentially subjected to one annealing process at a high temperature of about 420 ° C. or more after the deposition of the metal film.
그러나, 상기한 공정에 의해 형성된 반도체 소자의 금속배선은 공정 과정중과 공정후에 다양한 형태의 스트레스를 받게 된다.However, the metal wiring of the semiconductor device formed by the above process is subjected to various types of stresses during and after the process.
이러한 스트레스는 금속막 증착과정에서 발생하는 내적 (intrinsic) 스트레스와 열적(thermal)영향으로 발생하는 외적(extrinsic)스트레스로 구분할 수 있다.These stresses can be classified into intrinsic stresses generated during metal film deposition and extrinsic stresses caused by thermal effects.
상기한 스트레스에 의하여 금속배선은 점진적으로 손상을 받게 되는데, 손상의 형태로는 전기적으로는 저항값이 증가하며, 물리적으로는 금속배선의 선폭이 줄어드는 것으로 나타나게 된다.Due to the stress, the metal wiring is gradually damaged. In the form of the damage, the resistance value is increased electrically, and the line width of the metal wiring is physically reduced.
따라서, 금속배선의 손상이 진행될수록, 금속배선의 폭은 점점 더 줄어들고 전기저항은 매우 크게 증가하여, 반도체 소자의 성능은 점차 나빠지게 되며, 결국에는 금속배선의 단락(open)으로 까지 발전하여 금속배선의 수명을 단축시키게 된다.Therefore, as the damage of the metal wiring progresses, the width of the metal wiring decreases and the electrical resistance increases very much, and the performance of the semiconductor device gradually worsens, and eventually the metal wiring develops to an open short circuit. It shortens the life of the wiring.
결국, 본 발명은 상기한 종래기술의 문제점을 해결하기 위한 것으로, 본 발명의 목적은 반도체 제조공정에서 증착된 금속막에 대해 다중열처리를 수행하여 금속배선이 받는 스트레스를 완화시킴으로써, 금속배선의 수명을 연장시킬 수 있는 금속배선의 형성방법을 제공함에 있다.After all, the present invention is to solve the above problems of the prior art, an object of the present invention is to perform a multi-thermal treatment for the metal film deposited in the semiconductor manufacturing process to relieve the stress of the metal wiring, the life of the metal wiring It is to provide a method of forming a metal wiring that can be extended.
상기한 목적을 달성하는 본 발명의 다중열처리에 의한 금속배선의 형성방법은`반도체 소자 제조공정에서 실리콘 기판 위에 산화막을 성장시키고 금속막을 증착시킨 후 열처리에 의해 금속 배선을 형성하는 방법에 있어서,In the method of forming a metal wiring by the multiple heat treatment of the present invention to achieve the above object, in the method of forming a metal wiring by growing an oxide film on a silicon substrate and depositing a metal film in a semiconductor device manufacturing process, and then heat treatment,
상기한 금속막을 1차 열처리온도(T1)인 420~460℃에서 1차 열처리한 후, 상기한 1차 열처리온도 (T1)보다 낮은 열처리 온도(T2)에서 2차 이상의 다중 열처리를 수행하는 것을 특징으로 한다.Film wherein a metal primary heat treatment temperature (T 1) of after the primary heat treatment at 420 ~ 460 ℃, the above-described primary heat treatment temperature (T 1) lower heat treatment temperature than (T 2) in performing the second or multiple heat treatment Characterized in that.
이때, 상기한 열처리온도(T2)는 150~180℃로 유지하는 것이 바람직하다.At this time, the heat treatment temperature (T 2 ) is preferably maintained at 150 ~ 180 ℃.
또한, 상기한 1차 이상의 다중 열처리과정은 1차 열처리가 완료된 웨이퍼 상태 또는 패키징 후에 수행할 수 있다.In addition, the first or more multiple heat treatment processes may be performed after the wafer state or packaging in which the first heat treatment is completed.
이하, 본 발명에 따른 금속배선 형성방법을 첨부도면을 참조하여 보다 상세히 설명한다.Hereinafter, a method of forming metal wirings according to the present invention will be described in more detail with reference to the accompanying drawings.
일반적으로, 금속배선이 받는 스트레스는 온도와 밀접한 관련이 있으며, 열처리 방법에 따라 금속배선이 받는 스트레스는 달라진다.In general, the stress on metal wiring is closely related to temperature, and the stress on metal wiring varies depending on the heat treatment method.
금속배선이 받는 스트레스 중에서, 열적 영향으로 발생하는 외적 스트레스는 열팽창계수 차이와 온도 차이의 곱에 비례하는 것으로 알려져 있으며, 하기 식(1)과 같이 표현된다.Among the stresses in the metal wiring, the external stress caused by the thermal effect is known to be proportional to the product of the thermal expansion coefficient difference and the temperature difference, and is expressed as in Equation (1) below.
상기 식에서, σ는 스트레스(N/㎠), E는 영률 (young's modules)(N/㎠), α1및 αs는 금속막과 기판의 열팽창계수(/℃), △T는 열처리온도와 사용온도의 차이, k는 상수를 나타낸다.Where σ is stress (N / cm 2), E is young's modules (N / cm 2), α 1 and α s are thermal expansion coefficients (/ ° C.) of the metal film and substrate, and ΔT is used with the heat treatment temperature. The difference in temperature, k, represents a constant.
이때 사용 온도라 함은 실제 반도체 소자를 사용할 때 소자내부에서 발열되는 열로 인하여 소자의 접합부(junction) 온도가 상승하는데 , 이 상승된온도를 지칭하며, 보통 70~90℃의 온도범위를 지닌다.In this case, the use temperature is the junction temperature of the device is increased due to the heat generated inside the device when using the actual semiconductor device, and refers to the elevated temperature, usually has a temperature range of 70 ~ 90 ℃.
상기 식(1)을 살펴보면, △T항을 제외한 항은 물질의 고유값으로 이미 정해져 있는 값이므로, 스트레스 변화에 영향을 줄 수 없지만, △T 항은 열처리온도 변화에 따라 변하므로 열처리 온도를 낮추어 △T항을 작게 한다면, 스트레스를 줄일 수 있다.Looking at the equation (1), except for the term ΔT is a value that is already determined as the intrinsic value of the material, it can not affect the change in stress, but the ΔT term is changed according to the change in the heat treatment temperature to lower the heat treatment temperature If the ΔT term is made small, the stress can be reduced.
종래의 열처리 방법은 금속막 증착후 420℃ 부근에서의 1회 열처리 공정을 거치므로, 사용온도를 70~90℃라 할때 △T는 330~350℃이다.In the conventional heat treatment method, since the metal film is deposited and undergoes one heat treatment at around 420 ° C., when the use temperature is 70 to 90 ° C., ΔT is 330 to 350 ° C.
그러나 상기 식(1)에 따라 스트레스를 줄이기 위하여, 열처리 온도를 420℃이하로 낮출 수는 없는데, 이것은 420℃ 부근에서 열처리를 수행하여야 금속막과 산화막의 접착력이 좋아지기 때문이다.However, in order to reduce the stress according to Equation (1), the heat treatment temperature cannot be lowered below 420 ° C., because the adhesion between the metal film and the oxide film is improved only by performing heat treatment at around 420 ° C.
본 발명에서는 상기한 문제점을 해결하기 위하여, 반도체 제조공정에서 금속막 형성후 수행하는 열처리 공정을 여러번 수행하여 금속배선이 받는 스트레스를 완화시킴으로써 , 실제 사용중에 받는 열적 전기적 스트레스에 의하여 금속배선이 받는 스트레스를 완화시킴으로써, 실제 사용중에 받는 열적 전기적 스트레스에 의하여 금속배선이 받는 스트레스를 줄여, 궁극적으로 금속배선의 수명을 연장시킨다.In the present invention, in order to solve the above problems, by performing a heat treatment process performed after the formation of a metal film in the semiconductor manufacturing process several times to relieve the stress of the metal wiring, the stress of the metal wiring by the thermal electrical stress received during actual use By mitigating, the stress of metal wiring due to the thermal and electrical stress during actual use is reduced, and ultimately the life of metal wiring is extended.
즉, 420~460℃에서의 1차 열처리후, 1차 열처리온도 보다 낮은 온도에서 다중 열처리를 수행하여 △T를 줄임으로써, 스트레스를 낮추게 된다.That is, after the first heat treatment at 420 ~ 460 ℃, by performing a multiple heat treatment at a temperature lower than the first heat treatment temperature by reducing ΔT, the stress is lowered.
제 1도는 본 발명의 금속배선 형성공정에 대한 전체적인 공정도로서, 제 1도에 도시된 바와 같이, 본 발명에서는 금속막 증착후 420~460℃의 온도에서 1차 열처리를 거친 후, 1차 열처리온도보다 낮은 온도에서 2차 열처리공정을 수행한다.1 is an overall process diagram of the metallization process of the present invention, as shown in FIG. 1, in the present invention, after the first heat treatment at a temperature of 420 ~ 460 ℃ after metal film deposition, the first heat treatment temperature The secondary heat treatment process is carried out at lower temperatures.
즉, 상기 식 (1)에서 △T를 작게 하면 금속배선이 받게되는 스트레스를 줄일 수 있다는 점에 착안하여, 1차 열처리는 종래의 열처리 공정인 420~460℃부근에서 수행한 후, 2차 열처리공정은 420~460℃보다 낮은 온도에서 수행하면, 금속배선이 받게되는 스트레스는 작아지는데 그 이유는 다음과 같다.In other words, in view of the fact that by reducing the ΔT in the formula (1) can reduce the stress to the metal wiring, the first heat treatment is performed in the vicinity of 420 ~ 460 ℃ conventional heat treatment process, the second heat treatment If the process is carried out at a temperature lower than 420 ~ 460 ℃, the stress to the metal wiring is reduced for the following reasons.
상기 식(1)으로부터, 일반적인 1차 열처리 공정(열처리온두 T1)으로 증착된 금속배선이 사용중에 받게되는 스트레스 (σ1)는 하기 식(2)로 나타낼 수 있으며, 본 발명에 따라 일반적인 1차 열처리공정(열처리온도 T1)을 거친 후 전기한 열처리온도(T1)보다 낮은 온도 (T2)에서 2차 열처리공정을 수행할 경우 금속배선이 사용중에 받게되는 스트레스(σ2)는 하기 식 (3)으로 표현된다.From the above formula (1), the stress (σ 1 ) that the metal wiring deposited in the general primary heat treatment process (heat treatment hot water T 1 ) is in use may be represented by the following formula (2), When the secondary heat treatment process is performed at the temperature (T 2 ) lower than the electric heat treatment temperature (T 1 ) after the second heat treatment process (heat treatment temperature T 1 ), the stress (σ 2 ) that the metal wiring receives during use is It is represented by Formula (3).
상기 식에서 T1은 1차 열처리온도를 나타내고, T2는 2차 열처리온도를 나타내며, TU는 소자의 사용시 온도를 나타낸다.In the above formula, T 1 represents the primary heat treatment temperature, T 2 represents the secondary heat treatment temperature, and T U represents the temperature during use of the device.
상기 식 (2) 및 (3) 에서, △T항목을 비교하면,In the above formulas (2) and (3), when ΔT items are compared,
로 표시되며, T1T2TU이므로,Denoted by T 1 T 2 T U ,
가 되어,Become,
이므로, 다중열처리를 수행하면 스트레스를 줄일 수 있다.Therefore, the multiple heat treatment can reduce the stress.
이때, 본 발명에 따른 2차 또는 다중열처리시. 최종 열처리 온도(T2)는 150~180℃에서 수행하는 것이 바람직하며, 웨이퍼 상태에서나 패키징 후에 금속막을 열처리할 수 있다.At this time, when the secondary or multiple heat treatment according to the present invention. The final heat treatment temperature (T 2 ) is preferably performed at 150 to 180 ° C., and the metal film may be heat treated in a wafer state or after packaging.
예를 들어 , T1및 T2가 각각 420℃ 및 180℃일 경우에,For example, when T 1 and T 2 are 420 ° C. and 180 ° C., respectively,
로서, 2차 열처리를 수행하면, 금속배선이 받는 스트레스는 1/3이하로 줄어 들어 금속배선의 수명이 향상된다.As a secondary heat treatment, the stress applied to the metal wiring is reduced to 1/3 or less, thereby improving the life of the metal wiring.
이상에서 상세히 설명한 바와 같이, 본 발명의 금속배선 형성방법에 따르면, 반도체 제조공정에서 증착된 금속막에 대해 다중열처리를 수행하여 금속배선이 받는 스트레스를 완화시킴으로써, 금속배선의 수명을 연장시킬 수 있다는 것이 확인 되었다.As described in detail above, according to the metallization method of the present invention, by performing a multiple heat treatment on the metal film deposited in the semiconductor manufacturing process to relieve the stress of the metallization, it is possible to extend the life of the metallization It was confirmed.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950051474A KR0170478B1 (en) | 1995-12-18 | 1995-12-18 | Fabrication method of metal wire by multiple annealing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950051474A KR0170478B1 (en) | 1995-12-18 | 1995-12-18 | Fabrication method of metal wire by multiple annealing method |
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| Publication Number | Publication Date |
|---|---|
| KR970052936A KR970052936A (en) | 1997-07-29 |
| KR0170478B1 true KR0170478B1 (en) | 1999-03-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950051474A KR0170478B1 (en) | 1995-12-18 | 1995-12-18 | Fabrication method of metal wire by multiple annealing method |
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| KR (1) | KR0170478B1 (en) |
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| KR102168622B1 (en) | 2018-12-05 | 2020-10-21 | 경북대학교 산학협력단 | Method and probe card for selective thermal process using local breakdown currents |
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| KR970052936A (en) | 1997-07-29 |
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