KR0161883B1 - Method of fabricating metal wire of semiconductor device - Google Patents
Method of fabricating metal wire of semiconductor device Download PDFInfo
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- KR0161883B1 KR0161883B1 KR1019950012903A KR19950012903A KR0161883B1 KR 0161883 B1 KR0161883 B1 KR 0161883B1 KR 1019950012903 A KR1019950012903 A KR 1019950012903A KR 19950012903 A KR19950012903 A KR 19950012903A KR 0161883 B1 KR0161883 B1 KR 0161883B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
Abstract
본 발명은 반도체장치의 금속배선 형성방법에 관한 것으로, CMP에 의한 상감법의 단점을 배제하고, 실제 공정에 적용할 수 있는 구리배선 형성을 위한 구리박막 패터닝 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device, and to a method for patterning a copper thin film for forming a copper wiring that can be applied to an actual process, without the disadvantage of the damascene method by CMP.
본 발명은 절연층을 선택적으로 식각하여 구리배선이 형성될 소정 영역에 소정 깊이의 트랜치를 형성하는 공정과, 상기 트렌치가 형성된 절연층 전면에 확산장벽층을 형성하는 공정, 상기 확산장벽층이 형성된 절연층 전면에 구리를 증착하는 공정, 상기 구리층을 상기 절연층 표면에 이르는 부분까지 산화시켜 구리산화층을 형성하는 공정, 상기 구리산화층을 선택적으로 제거하는 공정 및 상기 절연층 전면에 확산 방지용 절연층을 형성하는 공정을 포함하여 이루어지는 반도체장치의 금속배선 형성방법을 제공한다.The present invention provides a method of selectively etching an insulating layer to form a trench having a predetermined depth in a predetermined region where a copper wiring is to be formed, a process of forming a diffusion barrier layer on the entire surface of the insulating layer on which the trench is formed, and the diffusion barrier layer is formed. Depositing copper on the entire surface of the insulating layer, oxidizing the copper layer to a portion reaching the surface of the insulating layer, forming a copper oxide layer, selectively removing the copper oxide layer, and a diffusion preventing insulating layer on the entire insulating layer It provides a method for forming metal wiring of a semiconductor device comprising a step of forming a.
Description
제1도는 온도에 따른 CuCl의 증기압을 나타낸 도면.1 shows the vapor pressure of CuCl with temperature.
제2도는 종래기술에 의한 구리배선 형성방법을 도시한 공정 순서도.2 is a process flowchart showing a copper wiring forming method according to the prior art.
제3도는 종래기술에 의한 구리배선시의 문제점을 나타내는 도면.3 is a view showing a problem in the copper wiring according to the prior art.
제4도는 본 발명에 의한 구리배선 형성방법을 도시한 공정 순서도.4 is a process flowchart showing a method for forming a copper wiring according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 산화막 2 : 포토레지스트1: oxide film 2: photoresist
3 : 트렌치 4 : 확산장벽층3: trench 4: diffusion barrier layer
5 : 구리 5-1 : 구리산화층5: copper 5-1: copper oxide layer
6 : 확산방지용 절연층6: diffusion prevention insulating layer
본 발명은 반도체장치의 금속배선 형성방법에 관한 것으로, 특히 구리(Cu) 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device, and more particularly, to a method for forming copper (Cu) wiring.
구리는 Al-Si-Cu 합금보다 낮은 비저항을 갖는다. 이러한 이유로 구리는 테플론(Teflon)과 같은 폴리머 기판위에 배선물질로 사용되고 있으며, 이는 프린트기판 제조분야에서는 기초가 되는 공정이다.Copper has a lower resistivity than Al-Si-Cu alloys. For this reason, copper is used as a wiring material on polymer substrates such as Teflon, which is a basic process in printed board manufacturing.
구리는 쉽게 산화가 일어나며, 집적회로에서 사용되는 다른 재료와의 상호작용 가능성(이는 구리의 Si 이나 SiO2에 대한 확산계수가 매우 높기 때문이다)이 있음으로 해서 고집적회로 제조에서는 배제되어 왔다.Copper is easily oxidized and has been ruled out in the manufacture of highly integrated circuits because of its potential for interaction with other materials used in integrated circuits (because copper has a very high diffusion coefficient for Si or SiO 2 ).
그러나 집적도의 증가와 확산장벽기술의 진보가 계속됨에 따라 구리는 점차 향후 IC제조 공정에서 적용될 수 있을 것으로 고려되고 있다.However, with increasing integration and advances in diffusion barrier technology, copper is increasingly being considered for future IC manufacturing processes.
구리 박막이 집적회로의 배선으로 적용되기 위해서는 구리의 확산을 제어할 수 있어야 하며, 무엇보다도 패턴 형성이 먼저 이루어져야 한다.In order for the copper thin film to be applied to the wiring of the integrated circuit, it is necessary to control the diffusion of copper and, first of all, to form a pattern.
구리의 식각방법은 크게 두 가지, 즉, 습식과 건식 식각으로 나뉘어지며, 이를 식각 케미스트리(chemistry)별로 나누어 보면 다음의 표와 같다.There are two ways of etching copper, that is, wet and dry etching, which are divided by etching chemistry as shown in the following table.
습식 식각방법은 식각하고자 하는 재료와 가장 화학적 반응 특성이 우수한 화학 용액을 이용하여 식각하는 방법으로 선택비(selectivity)를 거의 무한대로 높일 수 있고, 사용이 간단한 장점이 있다.The wet etching method is a method of etching using a chemical solution having the most chemical reaction property with the material to be etched to increase the selectivity to almost infinity, and has the advantage of being simple to use.
그러나 등방성(isotropic)의 식각 특성으로 인해 작은 임계치수(critical domension)를 요구하는 초고집적 회로에 있어서는 적용상에 문제가 있기 때문에 대개 분해능(resolution)이 여유가 있는 프린트 기판에서의 와이어링(wiring)등에 사용이 제한되고 있다.However, because of the isotropic etching characteristics, there is a problem in the application of the ultra-high density circuit which requires a small critical domension. Usage is limited to the back.
이와는 반대로 건식 식각은 플라즈마를 이용하여 높은 이방성(anisotropic) 식각을 수행함과 동시에 높은 선택비 특성을 얻을 수 있는 장점이 있으므로, 반도체 소자의 제조 공정에 매우 적합한 것으로 여겨진다.On the contrary, dry etching has a merit that high anisotropic etching can be performed using plasma and high selectivity characteristics can be obtained.
상기의 표에서 알 수 있듯이 구리의 건식 식각에는 주로 염화물(chloride) 화합물을 사용하게 된다.As can be seen from the above table, the dry etching of copper mainly uses chloride compounds.
이 경우에 CuClx의 형성을 피할 수 없으며, CuClx의 거동이 구리 식각의 중요한 변수가 된다.In this case, the formation of CuClx is unavoidable, and the behavior of CuClx becomes an important parameter of copper etching.
염소(chlorine)에 의한 구리의 산화는 다음 식과 같은 반응으로 설명된다.The oxidation of copper by chlorine is explained by the reaction
여기서 반응 생성물인 Cu(I) 염화물은 폴리머 형태의 고체이며, 매우 낮은 증기압(vapor pressure)을 갖는다.The reaction product Cu (I) chloride here is a solid in polymer form and has a very low vapor pressure.
제1도는 온도에 따른 CuCl의 증기압을 도시한 것이다.Figure 1 shows the vapor pressure of CuCl with temperature.
몇몇 연구자들이 염소화된 구리 표면으로부터 가열에 따른 탈착(desorption) 특성을 조사한 바 있는데 (H. E. Winters, J.Vac. Sci. Technol., A3, pp.786, 1985 ; H.M. Rosenstock, et al., J. Chem. Phys., 23, pp. 2442, 1955 ; C. Wong and V. Schomaker, J. Phys. Chem. 61,pp. 357, 1957), 염소화된 구리 표면으로부터 구리-염화물(copper-chloride)가 탈착되는 것은 약 150oC부터 시작되어 580oC 이하의 온도에서는 Cu3Cl3 형태로 탈착되다가 650oC 이상의 온도에서는 CuCl 형태로 주로 탈착 된다고 보고하였다.Several researchers have investigated the desorption characteristics of heating from chlorinated copper surfaces (HE Winters, J. Vac. Sci. Technol., A3, pp. 786, 1985; HM Rosenstock, et al., J. Chem. Phys., 23, pp. 2442, 1955; C. Wong and V. Schomaker, J. Phys. Chem. 61, pp. 357, 1957), copper-chloride from chlorinated copper surfaces Desorption starts from about 150 o C and decomposes in the form of Cu 3 Cl 3 at temperatures below 580 o C and then mainly in the form of CuCl at temperatures above 650 o C.
제1도에 도시된 바와 같이 CuCl은 960oC에서 약 100mTorr의 매우 낮은 증기압을 나타내므로, 표면으로부터의 탈착이 매우 느리기 때문에 식각시에 온도를 높이지 않으면 식각되지 않는다는 것을 알 수 있다.As shown in FIG. 1, since CuCl exhibits a very low vapor pressure of about 100 mTorr at 960 ° C., it can be seen that since desorption from the surface is very slow, it is not etched unless the temperature is increased during etching.
따라서 구리를 패터닝하기 위해서는 기존의 폴리머 마스크는 적합하지 않게 된다.Thus, conventional polymer masks are not suitable for patterning copper.
이에 따라 포토레지스트가 아닌 마스크 물질을 이용하여 식각하는 방법이 제시된 바 있는데, 거의 모든 경우 약 200-280oC의 고온 식각에 견디는 마스크 (폴리이미드, 플라즈마-경화 포토레지스트, MgO, Ta등)을 사용하는 법으로 일관되어 있다(P. Gulde and C, Scholtz, U.S.Patent 4,838,994 ; G.C.Schwartz and P.M.Schaible, J. Electrochem. Soc., 130, pp.1777, 1983 ; P.M.Schaible and G.C.schwartz, U.S.patent 4,352,716,1982 ; B.J.Howard, et al., in surface chemistry and beam-solid Interactions, Mater. Res. Soc. Symp. Proc., 201, Pittsburgh, PA, 1991 ; Y. Arita, Proc, SEMICON/KOREA 91 pp.Ⅱ-3, 1991).Accordingly, a method of etching using a mask material rather than a photoresist has been proposed. In almost all cases, a mask (polyimide, plasma-cured photoresist, MgO, Ta, etc.) that can withstand high temperature etching of about 200-280 ° C. is used. Consistent with the method used (P. Gulde and C, Scholtz, US Pat. 4,838,994; GCSchwartz and PMSchaible, J. Electrochem. Soc., 130, pp. 1777, 1983; al., in surface chemistry and beam-solid Interactions, Mater.Res. Soc.Symp. Proc., 201, Pittsburgh, PA, 1991; Y. Arita, Proc, SEMICON / KOREA 91 pp. II-3, 1991).
한편, 90년대초에 이르러 CMP(Chemnical Mechanical Polishing)법은 구리 패터닝에 적용하는 상감법(Dual Damascene)이 발표된바 있다(C.W.Kaanta, et al., Proceedings of 8th VMIC, pp. 144, 1991 ; M.Misawa, et al., Proceedings of 10th VMIC, pp.353, 1993).On the other hand, in the early 90's, the chemical mechanical polishing (CMP) method has been published with a dual damascene method applied to copper patterning (CWKaanta, et al., Proceedings of 8th VMIC, pp. 144, 1991; M. Misawa, et al., Proceedings of 10th VMIC, pp. 353, 1993).
이 방법을 공정 순서에 따라 살펴보면, 먼저 제2a도에 도시된 바와 같이 산화막(1)을 포토레지스트(2)를 이용하여 기존의 포토리소그래피에 의해 디파인(define)하고 제2b도와 같이 건식 식각 방법으로 금속선이 지나갈 부분을 식각하여 트랜치를 형성한 후, 확산장벽층(4)을 증착하고, 그 위에 구리(5)를 증착한다. 이 때, 구리의 증착은 블랭킷(blanket) 증착이 적용된다.Referring to this method in the order of the process, first, as shown in FIG. 2A, the oxide film 1 is defined by photolithography using photoresist 2, and then dry etching is performed as shown in FIG. 2B. After forming the trench by etching the portion through which the metal line will pass, the diffusion barrier layer 4 is deposited, and copper 5 is deposited thereon. In this case, blanket deposition is applied to the deposition of copper.
이어서 제2c도와 같이 CMP에 의해 구리(5)를 식각하여 산화막(1)내에 매몰되어 지나가는 구리(5)를 형성한다.Subsequently, as shown in FIG. 2C, copper 5 is etched by CMP to form copper 5 embedded in the oxide film 1.
다음에 제2d도와 같이 구리막을 완전 밀봉(encapsulation)되도록 SiNx등과 같은 확산방지용 유전박막(6)과 절연층(7)을 형성함으로써 구리배선공정을 완료한다.Next, as shown in FIG. 2D, the copper wiring process is completed by forming the diffusion preventing dielectric thin film 6 and the insulating layer 7 such as SiNx to completely encapsulate the copper film.
상기한 바와 같은 상감법은 구리배선을 형성하는데 매우 유용한 기술로 여겨지고 있으나, 아직까지는 CMP의 웨이퍼 전면에 대한 식각 균일도가 높지 않다는 점과 불순물 입자(particle) 생성 문제, 손상(scratching) 등의 문제들로 인해 실제 공정 적용이 어렵다.As described above, the damascene method is considered to be a very useful technique for forming copper interconnects, but there are still problems such as high etching uniformity of the CMP wafer front surface, impurity particle generation problems, and scratching. This makes it difficult to apply the actual process.
또한, 제3도에 도시된 바와 같이 산화막이 글로벌(global) 단차를 갖는 경우에 CMP를 적용하여 구리배선을 하는 것은 불가능하므로 중간층의 단차에 대한 공정 마진이 적은 문제가 있다.In addition, as shown in FIG. 3, in the case where the oxide film has a global step, it is impossible to perform copper wiring by applying CMP, so there is a problem that there is little process margin for the step of the intermediate layer.
본 발명은 이와 같은 문제를 해결하기 위한 것으로, CMP에 의한 상감법의 단점을 배제하고 실제 공정에 적용할 수 있는 구리배선 형성을 위한 구리 박막 패터닝 방법을 제공하는데 그 목적이 있다.The present invention is to solve such a problem, and to provide a copper thin film patterning method for forming a copper wiring that can be applied to the actual process without the disadvantages of the damascene method by CMP.
상기 목적을 달성하기 위한 본 발명의 절연층을 선택적으로 식각하여 구리배선이 형성될 소정 영역에 소정 깊이의 트렌치를 형성하는 공정과, 상기 트렌치가 형성된 절연층 전면에 확산장벽층을 형성하는 공정, 상기 확산장벽층이 형성된 절연층 전면에 구리를 증착하는 공정, 상기 구리층을 상기 절연층 표면에 이르는 부분까지 산화시켜 구리산화층을 형성하는 공정, 상기 구리산화층을 선택적으로 제거하는 공정 및 상기 절연층 전면에 확산 방지용 절연층을 형성하는 공정을 포함하여 이루어진다.Selectively etching the insulating layer of the present invention for achieving the above object, forming a trench having a predetermined depth in a predetermined region where the copper wiring is to be formed, and forming a diffusion barrier layer on the entire surface of the insulating layer on which the trench is formed; Depositing copper on the entire surface of the insulating layer on which the diffusion barrier layer is formed, forming a copper oxide layer by oxidizing the copper layer to a portion reaching the surface of the insulating layer, selectively removing the copper oxide layer, and the insulating layer And forming a diffusion preventing insulating layer on the entire surface.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제4도에 본 발명에 의한 구리배선 방법을 공정 순서에 따라 도시하였다.4 shows the copper wiring method according to the present invention according to the process sequence.
먼저, 제4a도에 도시된 바와 같이 절연층으로서, 예컨데, 산화막(1)(또는 도핑된 산화막)에 소정의 포토레지스트(2)를 적용한 사진 식각 공적을 통해 제4b도와 같이 트렌치(3)를 형성한 후, 트렌치(3)가 형성된 산화막(1) 전면에 확산장벽층(4)을 형성하고, 그 전면에 구리(5)를 증착한다.First, as shown in FIG. 4A, as the insulating layer, the trench 3 is formed as shown in FIG. 4B through a photolithography process in which a predetermined photoresist 2 is applied to the oxide film 1 (or the doped oxide film). After the formation, the diffusion barrier layer 4 is formed on the entire surface of the oxide film 1 on which the trench 3 is formed, and copper 5 is deposited on the entire surface.
이어서 제4c도와 같이 O2또는 O2+N2분위기에서 약 250-600oC의 온도로 통상의 로(furnace)를 이용한 열처리를 실시하여 구리(5)를 산화시킨다.Subsequently, as illustrated in FIG. 4C, the copper 5 is oxidized by heat treatment using a conventional furnace at an temperature of about 250-600 ° C. in an O 2 or O 2 + N 2 atmosphere.
여기서, 산화의 다른 방법으로 약 1013-1015/cm2의 도우즈(dose)로 산소 이온주입을 실시한 후, 급속열처리(RTA ; Rapid Thermal Anneal)를 행할 수도 있다.Here, as another method of oxidation, oxygen ion implantation may be performed with a dose of about 10 13 -10 15 / cm 2 , followed by rapid thermal annealing (RTA).
상기 두 방법 모두 구리산화층(5-1) 두께가 구리의 증착 두께에 한정되어 제4c도에 도시된 바와 같이 산화막의 트렌치(3)내에 매립된 구리(5)는 산화가 일어 나지 않도록 한다.In both of the above methods, the thickness of the copper oxide layer 5-1 is limited to the deposition thickness of copper, so that copper 5 embedded in the trench 3 of the oxide film is not oxidized as shown in FIG. 4C.
특히 산소 이온 주입의 경우는 CO가스등을 소오스로 하되, 두께 방향으로의 주입 원소 농도의 균일도 유지를 위해 이온주입 에너지를 다르게 하여 2단계로 주입할 수도 있다.In particular, in the case of oxygen ion implantation, CO gas may be used as a source, and the ion implantation energy may be injected in two stages to maintain uniformity of the concentration of the implanted element in the thickness direction.
산화공정이 끝나면 제4d도에 도시된 바와 같이 구리산화층(5-1)을 제거한다. 구리산화층은 주로 Cu2O으로 불화물(fluoride) 계통의 종류에 의해 식각이 가능하며, 불화물에 대한 금속 구리는 식각선택비를 충분히 가지므로 원하는 트렌치 부분에만 금속 구리(5)를 남길 수 있다.After the oxidation process, the copper oxide layer 5-1 is removed as shown in FIG. 4d. The copper oxide layer is mainly Cu 2 O, which can be etched according to the type of fluoride system, and the metal copper to the fluoride has an etching selectivity, so the metal copper 5 can be left only in the desired trench portion.
여기서, 에천트(etchant)인 불화물로는 CF4를 사용하여 이방성 건식 식각방법으로 식각을 행하는 것이 바람직하다.Here, as an etchant fluoride, it is preferable to etch by an anisotropic dry etching method using CF 4 .
다음에 제4e도에 도시된 바와 같이 트렌치내에 매립된 형태의 구리배선이 형성된 산화막(1) 전면에 확산방지용 절연층(6)으로서, 예컨데 Si3N4등을 증착하여 구리배선의 밀봉(encapsulation)을 행한다.Next, as shown in FIG. 4E, as the diffusion preventing insulating layer 6 on the entire surface of the oxide film 1 in which the copper wirings embedded in the trench are formed, for example, Si 3 N 4 or the like is deposited to encapsulate the copper wirings. ).
본 발명은 금속 구리의 제거가 어려운 점에 착안하여 구리산화층과 금속 구리의 식각 선택성을 확보하여 구리산화층을 선택적으로 제거하고, 금속 구리층으로 된 배선을 형성하느 것으로, 상기와 같이 산화막에 형성된 트렌치내에만 구리층을 형성하고, 그 상부의 구리층 부분은 산화에 의해 구리산화층으로 변화시켜 구리에 대해 식각 선택성이 있는 에천트를 이용한 식각 방법에 의해 상기 구리산화층을 제거함으로써 산화막내에 매립된 구리배선을 형성한다.The present invention focuses on the difficulty of removing the metal copper, thereby securing the etching selectivity of the copper oxide layer and the metal copper to selectively remove the copper oxide layer, and forming a wiring formed of the metal copper layer, thereby forming a trench formed in the oxide film as described above. The copper layer embedded in the oxide film is formed only by forming a copper layer inside the copper layer, the upper part of which is converted into a copper oxide layer by oxidation, and by removing the copper oxide layer by an etching method using an etchant having an etching selectivity to copper. To form.
본 발명은 구리배선이 매립되어 형성되는 산화막에 글로벌 단차가 있는 경우에도 전체에서 균일하게 식각이 수행되므로 트렌치 내부에만 구리층을 남길 수 있어 구리배선 형성이 가능해 진다.In the present invention, even when there is a global step in the oxide film formed by embedding the copper wiring, since the etching is performed uniformly throughout, the copper layer may be left only in the trench, thereby forming the copper wiring.
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950012903A KR0161883B1 (en) | 1995-05-23 | 1995-05-23 | Method of fabricating metal wire of semiconductor device |
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| KR1019950012903A KR0161883B1 (en) | 1995-05-23 | 1995-05-23 | Method of fabricating metal wire of semiconductor device |
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| KR960043033A KR960043033A (en) | 1996-12-21 |
| KR0161883B1 true KR0161883B1 (en) | 1999-02-01 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100459947B1 (en) * | 1997-12-30 | 2005-02-03 | 주식회사 하이닉스반도체 | Method of forming a metal line of semiconductor device |
| KR100698987B1 (en) * | 2000-04-05 | 2007-03-26 | 가부시키가이샤 히타치세이사쿠쇼 | Fabrication method for semiconductor integrated circuit device |
| US8119485B2 (en) | 2009-02-10 | 2012-02-21 | Hynix Semiconductor, Inc. | Semiconductor device and fabrication method thereof |
-
1995
- 1995-05-23 KR KR1019950012903A patent/KR0161883B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100459947B1 (en) * | 1997-12-30 | 2005-02-03 | 주식회사 하이닉스반도체 | Method of forming a metal line of semiconductor device |
| KR100698987B1 (en) * | 2000-04-05 | 2007-03-26 | 가부시키가이샤 히타치세이사쿠쇼 | Fabrication method for semiconductor integrated circuit device |
| US8119485B2 (en) | 2009-02-10 | 2012-02-21 | Hynix Semiconductor, Inc. | Semiconductor device and fabrication method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960043033A (en) | 1996-12-21 |
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