KR100459947B1 - Method of forming a metal line of semiconductor device - Google Patents

Method of forming a metal line of semiconductor device Download PDF

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KR100459947B1
KR100459947B1 KR1019970079317A KR19970079317A KR100459947B1 KR 100459947 B1 KR100459947 B1 KR 100459947B1 KR 1019970079317 A KR1019970079317 A KR 1019970079317A KR 19970079317 A KR19970079317 A KR 19970079317A KR 100459947 B1 KR100459947 B1 KR 100459947B1
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copper
thin film
copper thin
trench
film
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KR19990059120A (en
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이성권
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주식회사 하이닉스반도체
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    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for forming a metal interconnection of a semiconductor device is provided to improve step coverage capable of being obtained by a CVD(chemical vapor deposition) process by depositing a copper thin film by a PVD(physical vapor deposition) process and by performing a heat treatment on the copper thin film. CONSTITUTION: A semiconductor substrate(11) having a trench is prepared. A barrier layer(13) is deposited along a step on the resultant structure including the trench. A copper thin film(14,14A) is deposited on the barrier layer along the step on the resultant structure. A heat treatment is performed on the copper thin film in an oxygen atmosphere to grow the copper thin film in a direction that the surface area of the copper thin film extends to make the copper atoms of the copper thin film react with oxygen atoms, thereby filling the trench. An insulation layer is deposited on the resultant structure including a copper oxide layer(14B) formed on the copper thin film. The insulation layer and the copper oxide layer are removed to form a metal interconnection by a planarization process.

Description

반도체 소자의 금속 배선 형성 방법{Method of forming a metal line of semiconductor device}Method of forming a metal line of semiconductor device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 구리(Cu) 박막을 금속 배선용으로 사용하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method of using a copper (Cu) thin film for metal wiring.

일반적으로, 반도체 소자의 전도층 재료로 많이 사용되고 있는 알루미늄 합금은 낮은 융점과 높은 비저항 등의 특성으로 인하여 초대규모 집적회로(Ultra Large Scale Integration)급 반도체 소자에서는 더 이상의 적용이 어렵게 되었다. 따라서, 대체 재료의 필요성이 대두되었고, 그러한 재료 중의 하나가 바로 높은 전기 전도도 특성을 갖는 구리 합금이다. 그러나 구리는 반도체 소자 제조 공정 중 열처리 과정에서 쉽게 산화되는 특성이 있으므로, 구리 박막 패턴 형성시 전면을 보호막 공정(encapsulation)으로 감싸주어야 하는 단점이 있다.In general, aluminum alloys, which are widely used as conductive layer materials for semiconductor devices, are difficult to be applied to ultra large scale integration class semiconductor devices due to their low melting point and high resistivity. Thus, there is a need for alternative materials, one of which is copper alloys with high electrical conductivity properties. However, since copper is easily oxidized during the heat treatment during the semiconductor device manufacturing process, the entire surface of the copper thin film pattern may be encapsulated.

또한 금속 배선으로 구리 박막을 이용하게 되는 차세대 반도체 소자는 매우 협소한 디자인 룰(design rule)을 갖기 때문에 구리 박막의 증착시 층덮힘(stepcoverage)이 양호한 화학기상증착법(CVD)으로 증착되어야 한다. 그러나 아직까지 구리 박막 증착 공정 기술 개발 현황은 물리기상증착법(PVD)을 이용한 구리 박막 증착은 용이하나 화학기상증착법을 이용한 구리 박막의 증착은 충분하게 개발되어 있지 않은 실정이다.In addition, since the next-generation semiconductor devices using copper thin films as metal wirings have very narrow design rules, they should be deposited by chemical vapor deposition (CVD) with good step coverage during the deposition of copper thin films. However, the current development of copper thin film deposition process technology is easy to deposit copper thin film using physical vapor deposition (PVD), but the deposition of copper thin film using chemical vapor deposition has not been sufficiently developed.

본 발명은 상기한 문제점을 해결하여 소자의 전기적 특성이 우수한 금속 배선층을 형성하는데 그 목적이 있다.An object of the present invention is to solve the above problems to form a metal wiring layer excellent in the electrical characteristics of the device.

상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속 배선 형성 방법은, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판 상부에 제 1 절연막을 증착하고, 상기 제 1 절연막에 금속 배선이 형성될 영역을 식각하여 트렌치를 형성하는 단계와, 상기 트렌치를 포함하는 전체 구조 상부에 장벽층 및 구리 박막을 순차로 증착하는 단계와, 산소 분위기의 열처리를 실시하여 산소에 노출된 상기 구리 박막의 표면에 구리 산화막을 형성시키되, 상기 트렌치의 내부에는 구리 박막이 매립된 형태로 되도록 하는 단계와, 상기 구리 산화막을 포함하는 전체 구조 상부에 제 2 절연막을 증착하고, 식각하여 상기 트렌치 내부에 배선이 형성되도록 하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In the method for forming a metal wiring of a semiconductor device according to the present invention for achieving the above object, a first insulating film is deposited on a substrate having a structure in which a number of elements for forming a semiconductor device is formed, and the metal wiring is formed on the first insulating film. Etching a region to be formed to form a trench, sequentially depositing a barrier layer and a copper thin film on the entire structure including the trench, and performing a heat treatment in an oxygen atmosphere to form a trench. Forming a copper oxide film on the surface, the copper thin film is buried in the inside of the trench, the second insulating film is deposited on top of the entire structure including the copper oxide film, and the wiring is etched inside the trench Characterized in that it comprises a step to be formed.

도 1(a) 내지 도 1(e)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순차적으로 도시한 단면도.1 (a) to 1 (e) are cross-sectional views sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

11 : 기판 12 : 제 1 절연막11 substrate 12 first insulating film

13 : 장벽층 14, 14A : 구리 박막13: barrier layer 14, 14A: copper thin film

14B : 구리 산화막 15 : 제 2 절연막14B: copper oxide film 15: second insulating film

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 1(a) 내지 도 1(e)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순차적으로 도시한 단면도이다.1 (a) to 1 (e) are cross-sectional views sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.

도 1(a)에 도시된 것과 같이, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(11) 상부에 제 1 절연막(12)을 증착하고, 금속 배선이 형성될 영역을 식각하여 트렌치(A)를 형성한다. 그리고 나서 트렌치(A)를 포함하는 전체 구조 상부에 장벽층(barrier material ; 13)을 증착한다.As illustrated in FIG. 1A, a first insulating layer 12 is deposited on a substrate 11 having a structure in which various elements for forming a semiconductor element are formed, and an area where a metal wiring is to be formed is etched to form a trench ( Form A). A barrier material 13 is then deposited over the entire structure, including trench A. FIG.

도 1(b)는 장벽층(13) 상부에 구리 박막(14)을 증착한 단면도 이다. 이 때 구리 박막(14)은 증착이 용이한 물리기상증착법을 이용하여 증착한다.FIG. 1B is a cross-sectional view of depositing a copper thin film 14 on the barrier layer 13. At this time, the copper thin film 14 is deposited using a physical vapor deposition method which is easy to deposit.

그런데, 구리(Cu)는 반도체 소자의 제조 공정 중 열처리 과정에서 쉽게 산화되는 특성이 있는데, 이는 구리(Cu) 원자가 보다 열역학적으로 안정한 Cu2O 또는 CuO의 형태로 반응하게 되기 때문이다. 즉, 4Cu + O2= 2Cu2O의 반응열은 -165 KJ/mol 이고, 2Cu + O2= 2Cu의 반응열은 -151 KJ/mol이므로 Cu2O 또는 CuO 형태의 반응물이 순수한 구리보다 열역학적으로 더 안정하다.By the way, copper (Cu) is easily oxidized during the heat treatment during the manufacturing process of the semiconductor device, because the copper (Cu) atoms react in the form of more thermodynamically stable Cu 2 O or CuO. That is, the reaction heat of 4Cu + O 2 = 2Cu 2 O is -165 KJ / mol, and the heat of reaction of 2Cu + O 2 = 2Cu is -151 KJ / mol, which means that the reactant in the form of Cu 2 O or CuO is thermodynamically more than pure copper. Stable.

구리의 이러한 성질을 이용하여 구리 박막(14)이 증착된 전체 구조를 450 ℃ ∼ 600 ℃의 산소(O2) 분위기에서 열처리 한다. 따라서, 도 1(c)에 도시된 것과 같이, 구리 박막(14)의 구리 원자들은 보다 많은 산소 원자와 반응하기 위해 표면적을 넓히는 방향으로 부분적 이동을 하게 되고, 산소 분위기에 노출된 구리 박막(14)은 산화되어 구리 산화막(14B)을 형성하게 된다. 이와 같은 과정의 결과로 장벽층(13) 상부에는 표면이 구리 산화막(14B)으로 둘러쌓인 구리 박막(14A)이 마치 수은을 떨어뜨린 모양과 같이 형성되고, 트렌치(A) 내부에는 구리 박막(14A)이 매립된 배선 구조가 완성 된다.Using this property of copper, the entire structure on which the copper thin film 14 is deposited is heat-treated in an oxygen (O 2 ) atmosphere of 450 ° C to 600 ° C. Accordingly, as shown in FIG. 1C, the copper atoms of the copper thin film 14 partially move in a direction of increasing the surface area in order to react with more oxygen atoms, and are exposed to the oxygen atmosphere. ) Is oxidized to form a copper oxide film 14B. As a result of this process, the copper thin film 14A having the surface surrounded by the copper oxide film 14B is formed on the top of the barrier layer 13 as if mercury is dropped, and the copper thin film 14A inside the trench A. ) Is filled with the wiring structure.

도 1(d)와 같이, 전체 구조 상부에 스핀 온 글래스(SOG)와 같은 물질을 사용하여 제 2 절연막(15)을 증착한 후, 에치 백(etch back) 공정을 진행하여, 도 1(e)와 같은 금속 배선을 형성한다. 에치 백 공정은 화학적 기계 연마 방법(CMP)을 이용하거나 플라즈마 식각 방법을 이용한다.As shown in FIG. 1 (d), the second insulating film 15 is deposited on the entire structure using a material such as spin on glass (SOG), and then an etch back process is performed. To form a metal wiring. The etch back process uses a chemical mechanical polishing method (CMP) or a plasma etching method.

상술한 바와 같이 본 발명에 의하면, 구리 금속을 반도체 소자에 적용하게 됨에 따라 소자의 신뢰성이 향상되고, 제조 공정시 구리 박막을 증착이 용이한 물리기상증착법으로 증착하고도 열처리를 통하여 화학기상증착법에서 얻을 수 있는 층덮힘 효과를 갖을 수 있게 된다.As described above, according to the present invention, as the copper metal is applied to the semiconductor device, the reliability of the device is improved, and in the chemical vapor deposition method, the copper thin film is deposited by physical vapor deposition which is easy to deposit during the manufacturing process. It can have a layering effect that can be obtained.

Claims (5)

(a) 트렌치가 형성된 반도체 기판을 제공하는 단계;(a) providing a trenched semiconductor substrate; (b) 상기 트렌치를 포함하는 전체 구조 상부면의 단차를 따라 장벽층을 증착하는 단계;(b) depositing a barrier layer along a step of the top surface of the entire structure including the trench; (c) 상기 장벽층을 포함하는 전체 구조 상부면의 단차를 따라 물리기상증착법으로 상기 장벽층의 상부에 구리 박막을 증착하는 단계;(c) depositing a thin copper film on top of the barrier layer by physical vapor deposition along a step of the top surface of the entire structure including the barrier layer; (d) 상기 구리 박막의 구리원자가 산소 원자와 반응하기 위해 표면적을 넓히는 방향으로 성장하여 상기 트렌치를 매립시키도록 산소 분위기에서 열처리 공정을 실시하는 단계;(d) performing a heat treatment process in an oxygen atmosphere such that the copper atoms of the copper thin film grow in a direction in which the surface area is increased to react with oxygen atoms to fill the trenches; (e) 상기 트렌치가 매립되도록 성장된 상기 구리 박막의 상부면에 형성된 구리 산화막을 포함하는 전체 구조 상부에 절연막을 증착하는 단계; 및(e) depositing an insulating film over the entire structure including a copper oxide film formed on an upper surface of the copper thin film grown to fill the trench; And (f) 평탄화 공정을 실시하여 상기 절연막과 상기 구리 산화막을 제거하여 금속 배선을 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법(f) forming a metal wiring by performing a planarization process to remove the insulating film and the copper oxide film to form a metal wiring. 제 1 항에 있어서,The method of claim 1, 상기 열처리 공정은 450℃ 내지 600℃의 온도 영역 및 O2분위기에서 실시하는 반도체 소자의 금속 배선 형성 방법.The heat treatment step is a metal wiring formation method of a semiconductor device carried out in a temperature range of 450 ℃ to 600 ℃ and O 2 atmosphere. 제 1 항에 있어서,The method of claim 1, 상기 구리 산화막은 Cu2O 및 CuO 중 적어도 어느 하나인 반도체 소자의 금속 배선 형성 방법.And said copper oxide film is at least one of Cu 2 O and CuO. 제 1 항에 있어서,The method of claim 1, 상기 절연막은 스핀 온 글래스막인 반도체 소자의 금속 배선 형성 방법.And the insulating film is a spin on glass film. 제 1 항에 있어서,The method of claim 1, 상기 평탄화 공정은 에치 백 공정으로 화학적기계연마 및 플라즈마를 이용한 식각 중 적어도 어느 하나로 실시되는 반도체 소자의 금속 배선 형성 방법.The planarization process is a method of forming a metal wiring of a semiconductor device is carried out by at least one of an etching using a chemical mechanical polishing and plasma as an etch back process.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0465824A (en) * 1990-07-06 1992-03-02 Fujitsu Ltd Manufacture of semiconductor device
JPH07183299A (en) * 1993-12-22 1995-07-21 Nec Corp Method for forming copper wirings
KR960002752A (en) * 1994-06-21 1996-01-26 사또 후미오 Semiconductor device and manufacturing method thereof
KR960043033A (en) * 1995-05-23 1996-12-21 문정환 Metal wiring formation method of semiconductor device
KR970051993A (en) * 1995-12-26 1997-07-29 김주용 Planarization method of SOG film of semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0465824A (en) * 1990-07-06 1992-03-02 Fujitsu Ltd Manufacture of semiconductor device
JPH07183299A (en) * 1993-12-22 1995-07-21 Nec Corp Method for forming copper wirings
KR960002752A (en) * 1994-06-21 1996-01-26 사또 후미오 Semiconductor device and manufacturing method thereof
KR960043033A (en) * 1995-05-23 1996-12-21 문정환 Metal wiring formation method of semiconductor device
KR0161883B1 (en) * 1995-05-23 1999-02-01 문정환 Method of fabricating metal wire of semiconductor device
KR970051993A (en) * 1995-12-26 1997-07-29 김주용 Planarization method of SOG film of semiconductor device

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