KR960043033A - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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Publication number
KR960043033A
KR960043033A KR1019950012903A KR19950012903A KR960043033A KR 960043033 A KR960043033 A KR 960043033A KR 1019950012903 A KR1019950012903 A KR 1019950012903A KR 19950012903 A KR19950012903 A KR 19950012903A KR 960043033 A KR960043033 A KR 960043033A
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KR
South Korea
Prior art keywords
layer
copper
insulating layer
forming
semiconductor device
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Application number
KR1019950012903A
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Korean (ko)
Other versions
KR0161883B1 (en
Inventor
이영종
김도형
Original Assignee
문정환
Lg 반도체 주식회사
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Application filed by 문정환, Lg 반도체 주식회사 filed Critical 문정환
Priority to KR1019950012903A priority Critical patent/KR0161883B1/en
Publication of KR960043033A publication Critical patent/KR960043033A/en
Application granted granted Critical
Publication of KR0161883B1 publication Critical patent/KR0161883B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치의 금속배선 형성방법에 관한 것으로, CMP에 의한 상감법의 단점을 배제하고 실제 공정에 적용할 수 있는 구리배선 형성을 위한 구리 박막 패터닝 방법에 관한 것이다.The present invention relates to a metal wiring forming method of a semiconductor device, and to a copper thin film patterning method for forming a copper wiring that can be applied to the actual process without the disadvantage of the damascene method by CMP.

본 발명은 절연층을 선택적으로 식각하여 구리 배선이 형성될 소정 영역에 소정 깊이의 트랜치를 형성하는 공정과, 상기트렌치가 형성된 절연층 전면에 확산장벽층을 형성하는 공정, 상기 확산장벽층이 형성된 절연층 전면에 구리를 증착하는 공정, 상기 구리층을 상기 절연층 표면에 이르는 부분까지 산화시켜 구리산화층을 형성하는 공정, 상기 구리산화층을 선택적으로 제거하는 공정, 및 상기 절연층 전면에 확산방지용 절연층을 형성하는 공정을 포함하여 이루어지는 반도체장치의 금속배선 형성방법을 제공한다.The present invention provides a method of selectively etching an insulating layer to form a trench having a predetermined depth in a predetermined region where a copper wiring is to be formed, and forming a diffusion barrier layer on an entire surface of the insulating layer on which the trench is formed, wherein the diffusion barrier layer is formed. Depositing copper on the entire surface of the insulating layer, oxidizing the copper layer to a portion reaching the surface of the insulating layer, forming a copper oxide layer, selectively removing the copper oxide layer, and diffusion preventing insulation on the entire insulating layer A metal wiring forming method of a semiconductor device comprising a step of forming a layer is provided.

Description

반도체장치의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명에 의한 구리 배선 형성방법을 도시한 공정순서도.4 is a process flowchart showing a method for forming a copper wiring according to the present invention.

Claims (8)

절연층을 선택적으로 식각하여 구리배선이 형성될 소정 영역에 소정 깊이의 트렌치를 형성하는 공정과, 상기 트렌치가 형성된 절연층 전면에 확산장벽층을 형성하는 공정, 상기 확산장벽층이 형성된 절연층 전면에 구리를 증착하는 공정, 상기 구리층을 상기 절연층 표면에 이르는 부분까지 산화시켜 구리산화층을 형성하는 공정, 상기 구리산화층을선택적으로 제거하는 공정, 및 상기 절연층 전면에 확산방지용 절연층을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.Selectively etching the insulating layer to form a trench having a predetermined depth in a predetermined region where the copper wiring is to be formed; forming a diffusion barrier layer on the entire surface of the insulating layer on which the trench is formed; Forming a copper oxide layer by oxidizing the copper layer to a portion reaching the surface of the insulating layer, selectively removing the copper oxide layer, and forming a diffusion preventing insulating layer on the entire surface of the insulating layer And forming a metal wiring in the semiconductor device. 제1항에 있어서, 상기 구리층의 산화는 상기 절연층의 표면까지 이루어지도록 함으로써 트렌치내에 매립된 구리층부분은 산화되지 않고 남아 구리배선이 되도록 하는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.The method of claim 1, wherein the copper layer is oxidized to the surface of the insulating layer so that a portion of the copper layer embedded in the trench remains in the copper wiring without being oxidized. 제1항에 있어서, 상기 구리층의 산화는 O2를 포함하는 분위기에서의 로를 이용한 열처리에 의해 행하는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.The method of claim 1, wherein the copper layer is oxidized by heat treatment using a furnace in an atmosphere containing O 2 . 제1항에 있어서, 상기 구리층의 산화는 구리층에 산소이온을 주입한 후 열처리하는 방법에 의해 행하는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.2. The method of claim 1, wherein the copper layer is oxidized by injecting oxygen ions into the copper layer and then thermally treating the copper layer. 제4항에 있어서, 상기 열처리 급속 열처리 방법으로 행하는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.5. The method of forming a metal wiring in a semiconductor device according to claim 4, wherein the heat treatment is performed by a rapid heat treatment method. 제4항에 있어서, 상기 이온주입시의 주입 에너지를 2단계로 주입하여 주입되는 이온의 농도를 두께 방향으로 균일하게 하는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.5. The method of claim 4, wherein the implantation energy at the time of ion implantation is implanted in two stages so that the concentration of implanted ions is uniform in the thickness direction. 제1항에 있어서, 상기 구리산화층은 불화물을 이용한 건식 식각방법에 의해 제거하는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.The method of claim 1, wherein the copper oxide layer is removed by a dry etching method using fluoride. 제1항에 있어서, 상기 절연층 산화막 또는 도핑된 산화막임을 특징으로 하는 반도체장치의 금속배선 형성방법.The method of claim 1, wherein the insulating layer oxide layer or the doped oxide layer is formed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950012903A 1995-05-23 1995-05-23 Method of fabricating metal wire of semiconductor device KR0161883B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950012903A KR0161883B1 (en) 1995-05-23 1995-05-23 Method of fabricating metal wire of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019950012903A KR0161883B1 (en) 1995-05-23 1995-05-23 Method of fabricating metal wire of semiconductor device

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KR960043033A true KR960043033A (en) 1996-12-21
KR0161883B1 KR0161883B1 (en) 1999-02-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459947B1 (en) * 1997-12-30 2005-02-03 주식회사 하이닉스반도체 Method of forming a metal line of semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291720A (en) * 2000-04-05 2001-10-19 Hitachi Ltd Semiconductor integrated circuit device and its manufacturing method
KR101095817B1 (en) 2009-02-10 2011-12-21 주식회사 하이닉스반도체 Semiconductor apparatus and fabrication method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459947B1 (en) * 1997-12-30 2005-02-03 주식회사 하이닉스반도체 Method of forming a metal line of semiconductor device

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