KR0161808B1 - Nand-type non-volatile semiconductor memory device & method for making the same - Google Patents
Nand-type non-volatile semiconductor memory device & method for making the same Download PDFInfo
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- KR0161808B1 KR0161808B1 KR1019950040126A KR19950040126A KR0161808B1 KR 0161808 B1 KR0161808 B1 KR 0161808B1 KR 1019950040126 A KR1019950040126 A KR 1019950040126A KR 19950040126 A KR19950040126 A KR 19950040126A KR 0161808 B1 KR0161808 B1 KR 0161808B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 27
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 12
- 239000007772 electrode material Substances 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
본 발명은 낸드형 플래쉬 메모리장치에 관한 것으로서, 특히 반도체기판상의 소자분리영역에 의해 한정된 액티브영역상에 스트링 선택라인 트랜지스터와 적어도 2개이상의 메모리셀 트랜지스터들 및 접지선택라인 트랜지스터를 비트라인과 접지라인사이에 직렬로 구성한 낸드형 불휘발성 반도체 메모리장치에 있어서, 상기 스트링 선택라인 트랜지스터 및 접지선택라인 트랜지스터의 액티브영역의 폭이 상기 메모리셀 트랜지스터의 액티브영역의 폭보다 넓게 형성된 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND flash memory device, and more particularly to a bit line and a ground line comprising a string select line transistor, at least two memory cell transistors, and a ground select line transistor on an active region defined by an isolation region on a semiconductor substrate. In the NAND type nonvolatile semiconductor memory device configured in series between, the widths of the active regions of the string select line transistor and the ground select line transistor are wider than the widths of the active regions of the memory cell transistor.
Description
제1도는 통상적인 낸드형 불휘발성 반도체 메모리장치의 단면도.1 is a cross-sectional view of a conventional NAND type nonvolatile semiconductor memory device.
제2도는 제1도의 등가회로도.2 is an equivalent circuit diagram of FIG.
제3도는 종래의 낸드형 불휘발성 반도체 메모리장치의 액티브영역의 레이아웃도.3 is a layout diagram of an active region of a conventional NAND nonvolatile semiconductor memory device.
제4도는 제3도의 A-A선 단면도.4 is a cross-sectional view taken along the line A-A of FIG.
제5도는 제3도의 B-B선 단면도.5 is a cross-sectional view taken along the line B-B in FIG.
제6도는 본 발명에 의한 낸드형 불휘발성 메모리장치의 액티브영역의 레이아웃도.6 is a layout diagram of an active region of a NAND nonvolatile memory device according to the present invention.
본 발명은 낸드형 불휘발성 반도체 메모리장치 및 그 제조방법에 과한 것으로서, 특히 0.4㎛ 이하의 디자인룰을 적용하는 고집적 낸드형 플래쉬(NAND-type FLASH) 메모리장치 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND type nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a highly integrated NAND-type FLASH memory device to which a design rule of 0.4 µm or less is applied.
낸드형 플래쉬 메모리장치는 일본 도시바가 제안한 것으로서, 비트라인과 접지사이에 복수의 트랜지스터를 직렬로 연결한 메모리셀구조를 말한다. 복수의 트랜지스터 중 비트라인에 인접한 트랜지스터는 스트링선택라인(SSL:String Select Line) 트랜지스터이고 접지에 인접한 트랜지스터는 접지선택라인(GSL:Ground Select Line) 트랜지스터로서 프로그램 제어를 위한 제어 트랜지스터들이다. SSL과 GSL사이에 있는 메모리셀 트랜지스터들은 플로팅 게이트와 콘트롤 게이트가 적층된 구조이고 플로팅 게이트와 가판 사이에 Fowler-Nordheim(이하 F-N이라함)터널에 의한 프로그램 및 소거를 위한 얇은 산화막이 존재한다.The NAND flash memory device is proposed by Toshiba Japan and refers to a memory cell structure in which a plurality of transistors are connected in series between a bit line and a ground. Among the plurality of transistors, a transistor adjacent to a bit line is a string select line (SSL) transistor and a transistor adjacent to ground is a control transistor for program control as a ground select line (GSL) transistor. The memory cell transistors between SSL and GSL have a structure in which a floating gate and a control gate are stacked, and there is a thin oxide layer for programming and erasing by a Fowler-Nordheim (hereinafter referred to as F-N) tunnel between the floating gate and the substrate.
이와같은 낸드형 플래쉬 메모리 셀구조에서는 제어 트랜지스터와 메모리셀 트랜지스터들이 동시에 제조되고 직렬로 연결된 셀들의 전류가 노아(NOR)형에 비해 작기 때문에 고집적화하기 위해서는 억세스 타임과 센싱감도에 따라 정밀한 디자인 룰을 적용해야 하고 액티브 영역형성 공정부터는 공정 마진을 고려해야만 한다.In the NAND type flash memory cell structure, since the control transistor and the memory cell transistors are manufactured at the same time and the current of the cells connected in series is smaller than that of the NOR type, precise design rules are applied according to the access time and the sensing sensitivity to achieve high integration. From the active area formation process, process margins must be considered.
종래의 기술에서는 액티브 영역위에 메모리셀 트랜지스터와 함께 형성되는 SSL/GSL 트랜지스터들은 터널 산화막을 성장시키기 전의 식각공정단계를 거치지 않게 되므로 후속공정에 의해 제어 트랜지스터들의 채널영역이 메모리셀 트랜지스터들의 채널영역보다 상대적으로 감소하게 된다.In the related art, the SSL / GSL transistors formed together with the memory cell transistors on the active region do not go through the etching process step before growing the tunnel oxide layer, so that the channel region of the control transistors is relatively smaller than the channel region of the memory cell transistors by a subsequent process. To decrease.
4Mb나 16Mb의 낸드형 플래쉬 메모리장치에서는 상술한 채널영역의 감소현상이 공정마진에 의해 별 문제가 없었으나 0.4㎛의 디자인 룰을 가지는 64메가이상의 고집적도에서는 공정마진이 없어지게 되므로 상대적으로 SSL/GSL 트랜지스터의 전기적 성능과 프로세스 윈도우 마진 측면에서 장애요인으로 작용할 소지가 많아지는 문제가 대두되고 있다.In the 4Mb or 16Mb NAND flash memory device, the above-mentioned reduction of the channel area is not a problem due to the process margin, but the process margin disappears at a high density of 64 mega or more with a 0.4 탆 design rule. The problem of increasing the potential of obstacles in terms of electrical performance and process window margins of GSL transistors is emerging.
따라서, 본 발명의 목적은 이와같은 종래 기술의 문제점을 해결하기 위하여 액티브 영역 형성시 액트브 영역의 형상변경으로 효율적이고 안정적인 프로세스 디자인을 확보할 수 있는 낸드형 불휘발성 반도체 메모리장치 및 그 제조방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a NAND type nonvolatile semiconductor memory device and a method of manufacturing the same, which can secure an efficient and stable process design by changing the shape of an active area when forming an active area. To provide.
상기 목적을 달성하기 위한 본 발명의 장치는 반도체 기판표면의 소자분리영역에 의해 한정된 액티브영역상에 스트링 선택라인 트랜지스터와 적어도 2개이상의 메모리셀 트랜지스터들 및 접지선택라인 트랜지스터를 비트라인과 접지라인사이에 직력로 구성한 낸드형 불휘발성 반도체 메모리장치에 있어서, 스트링 선택라인 트랜지스터 및 접지선택라인 트랜지스터의 액티브영역의 폭이 상기 메로리셀 트랜지스터의 액티브영역의 폭보다 넓게 형성된 것을 특징으로 한다.A device of the present invention for achieving the above object is to provide a string select line transistor, at least two memory cell transistors, and a ground select line transistor between a bit line and a ground line in an active region defined by an isolation region of a semiconductor substrate surface. In the NAND type nonvolatile semiconductor memory device having a linear force, the widths of the active regions of the string select line transistor and the ground select line transistor are formed to be wider than the widths of the active regions of the meleecell transistor.
여기서, 상기 스트링 선택라인 트랜지스터 및 접지선택라인 트랜지스터의 액티브영역의 폭이 상기 메모리셀 트랜지스터의 액티브영역의 폭보다 1%~100%이상 넓게 형성하고, 상기 스트링 선택라인 트랜지스터 및 접지 선택라인 트랜지스터가 형성되는 게이트 산화막의 두께가 상기 메모리셀 트랜지스터가 형성되는 게이트 산화막보다 두껍게 형성한 것을 특징으로 한다.The width of the active region of the string select line transistor and the ground select line transistor is formed to be 1% to 100% wider than the width of the active region of the memory cell transistor, and the string select line transistor and the ground select line transistor are formed. The thickness of the gate oxide film to be formed is thicker than the gate oxide film on which the memory cell transistor is formed.
본 발명의 제조방법은 반도체 기판표면의 소자분리영역에 의해 한정된 액티브영역을 가지며, 상기 액티브영역상에 스트링 선택라인 트랜지스터와 적어도 2개이상의 메모리셀 트랜지스터들 및 접지선택라인 트랜지스터를 비트라인과 접지라인사이에 직렬로 구성한 낸드형 불휘발성 반도체 메모리장치의 제조방법에 있어서, 반도체 기판의 표면근방에 상기 스트링 선택라인 트랜지스터 및 접지선택라인 트랜지스터가 형성될 영역의 폭이 상기 메모리셀 트랜지스터가 형성될 영역의 폭보다 넓게 되도록 액티브영역을 한정하기 위해 소자분리영역에 필드이온주입 및 필드산화막을 형성하는 제1공정; 액티브영역상에 성장된 희생산화막을 습식식각하는 제2공정; 결과물상에 제1게이트산화막을 성장시키는 제3공정; 통상의 사진식각공정을 통해 메모리셀 트랜지스터들이 형성되는 액티브영역만 오픈되도록 상기 제1게이트산화막을 습식식각하는 제4공정; 결과물상에 제2게이트산화막을 형성하고 제1전극물질을 적층하는 제5공정; 사진식각공정을 통해 제1전극물질을 패터닝하여 플로팅게이트를 형성하는 제6공정; 결과물상에 층간 절연막을 형성하는 제7공정; 결과물상에 제2전극물질을 적층하는 제8공정; 사진식각공정을 통해 상기 제2전극물질을 패터닝하여 콘트롤 게이트를 형성하는 제9공정; 형성된 게이트패턴을 이온주입 마스크로 사용하여 상기 액티브영역의 표면근방에 저농도의 불순물을 이온주입하는 제10공정; 게이트패턴의 측벽에 스페이서를 형성하고 스페이서에 셀프얼라인되도록 액티브영역의 표면근방에 고농도의 불순물을 이온주입하여 소스/드레인을 형성하는 제11공정; 및 절연물질을 적층하고 비트라인 콘택홀을 형성하고 메탈전극을 형성하는 제12공정을 구비하는 것을 특징으로 한다.The manufacturing method of the present invention has an active region defined by a device isolation region on the surface of a semiconductor substrate, and includes a string select line transistor, at least two memory cell transistors, and a ground select line transistor on the active region. A method of manufacturing a NAND type nonvolatile semiconductor memory device configured in series between a plurality of regions, wherein a width of a region where the string select line transistor and a ground select line transistor are to be formed near the surface of the semiconductor substrate is greater than that of the region where the memory cell transistor is to be formed. A first step of forming a field ion implantation and a field oxide film in the device isolation region to define the active region to be wider than the width; A second process of wet etching the sacrificial oxide film grown on the active region; A third step of growing a first gate oxide film on the resultant; A fourth process of wet etching the first gate oxide layer such that only an active region where memory cell transistors are formed is opened by a general photolithography process; A fifth step of forming a second gate oxide film on the resultant material and stacking a first electrode material; A sixth step of forming a floating gate by patterning the first electrode material through a photolithography process; A seventh step of forming an interlayer insulating film on the resultant product; An eighth step of laminating a second electrode material on the resultant product; A ninth process of forming a control gate by patterning the second electrode material through a photolithography process; A tenth step of ion implanting impurities of low concentration near the surface of the active region using the formed gate pattern as an ion implantation mask; Forming an spacer on sidewalls of the gate pattern and implanting a high concentration of impurities near the surface of the active region so as to self-align the spacers to form a source / drain; And a twelfth process of stacking insulating materials, forming bit line contact holes, and forming metal electrodes.
이하, 첨부한 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.
제1도는 통상적인 낸드형 플래쉬 메모리장치의 셀어레이의 단면도이다. 제2도는 제1도의 등가회로도이다.1 is a cross-sectional view of a cell array of a conventional NAND flash memory device. 2 is an equivalent circuit diagram of FIG.
낸드 플래쉬 메모리장치는 N형 반도체기판(10)에 P형웰(12)을 형성하고, 필드산화막(16)의 아래에는 필드이온 주입에 의해 채널 스톱층(18)이 형성된다. 필드산화막(16)에 의해 한정된 액티브영역에는 P형웰(12)의 표면 근방에 소스/드레인(14)이 불순물 주입에 의해 형성된다. 비트라인 프리차지 트랜지스터(BPT)와 SSL/GSL 트랜지스터의 액티브영역상에는 제1게이트산화막(20)이 형성되고 셀트랜지스터(CT)의 액티브영역상에는 제2게이트산화막(22)가 형성된다. 제1게이트산화막의 두께는 제2게이트산화막의 두께보다 두껍게 형성되고 제2게이트산화막은 F-N터널 산화막으로 제공된다. 24는 폴리실리콘과 같은 제1전극물질로 구성된 플로팅 게이트이고 26은 산화막/질화막/산화막으로 구성된 층간절연막이고, 28은 폴리실리콘과 같은 제2전극물질로 구성된 콘트롤게이트이다. 콘트롤 게이트는 워드라인(WL)과 동시에 형성된다. 플로팅 게이트(24), 층간절연막(26), 콘트롤게이트(28)의 적층구조의 측벽에는 스페이서(30)가 형성된다. 소스/드레인(14)는 적층구조에 셀프얼라인(Self-align)된 저농도의 불순물을 주입층과 스페이서에 셀프얼라인된 고농도의 불순물 주입층으로 구성되게 된다.In the NAND flash memory device, a P-type well 12 is formed on an N-type semiconductor substrate 10, and a channel stop layer 18 is formed under the field oxide layer 16 by field ion implantation. In the active region defined by the field oxide film 16, a source / drain 14 is formed near the surface of the P-type well 12 by implantation of impurities. The first gate oxide film 20 is formed on the active region of the bit line precharge transistor BPT and the SSL / GSL transistor, and the second gate oxide film 22 is formed on the active region of the cell transistor CT. The thickness of the first gate oxide film is formed thicker than that of the second gate oxide film, and the second gate oxide film is provided as an F-N tunnel oxide film. 24 is a floating gate made of a first electrode material such as polysilicon, 26 is an interlayer insulating film made of an oxide film / nitride film / oxide film, and 28 is a control gate made of a second electrode material made of polysilicon. The control gate is formed simultaneously with the word line WL. Spacers 30 are formed on sidewalls of the stacked structure of the floating gate 24, the interlayer insulating layer 26, and the control gate 28. The source / drain 14 is composed of an implantation layer having a low concentration of self-aligned impurities in a stacked structure and a highly implanted impurity implantation layer self-aligned with a spacer.
이와같이 구성된 결과물상에 BPSG(Silicon Glass)와 같은 평탄화층(32)가 증착되고 평탄화층(32)에는 비트라인콘택(34)이 형성한후 비트라인 콘택과 평탄화층(32) 상에 메탈전극(36)을 형성하여서 된 것이다.A planarization layer 32 such as silicon glass (BPSG) is deposited on the resultant structure formed as described above, and a bit line contact 34 is formed on the planarization layer 32, and then a metal electrode (or metal electrode) is formed on the bit line contact and the planarization layer 32. 36) was formed.
제3도를 참조하면, 종래의 낸드형 플래쉬 메모리장치에서는 액티브영역의 패턴이 제어트랜지폭이나 메모리 셀트랜지스터의 폭이 동일 사이즈로 형성되어 있다. 따라서, 제조공정상에 두꺼운 제1게이트산화막을 가지는 제어트랜지스터의 액티브영역의 폭(제4도의 A)이 제1게이트산화막을 제거하고 얇은 제2게이트산화막을 형성하는 메모리 셀트랜지스터의 액티브영역의 폭(제5도의 B)보다 좁아지게 된다. 이는 제1게이트산화막의 제거시에 습식식각공정에 의해 넓어지게 되기 때문이다.Referring to FIG. 3, in the conventional NAND flash memory device, the active region pattern has the same width as the control transistor width and the memory cell transistor. Therefore, the width of the active region of the control transistor having the thick first gate oxide film (A in FIG. 4) during the manufacturing process is the width of the active region of the memory cell transistor which removes the first gate oxide film and forms a thin second gate oxide film ( It becomes narrower than B) of FIG. This is because the wet etching process is widened when the first gate oxide film is removed.
따라서, 본 발명에서는 제6도에 도시한 바와 같이 제어트랜지스터의 액티브영역의 폭(C)을 메모리 셀트랜지스터의 액티브영역의 폭(B)보다 넓게 설정하여 패터닝한다는 것이다. 고집적화가 되어감에 따라서 공정마진이 점차적으로 없어지게 되므로 처음부터 공정상의 변동분에 대응한 마진을 충분히 고려하여 액티브영역을 차등적으로 구성한다는 것이다.Accordingly, in the present invention, as shown in FIG. 6, the width C of the active region of the control transistor is set to be wider than the width B of the active region of the memory cell transistor. As high integration increases, process margins gradually disappear, so that active regions are differentially configured in consideration of margins corresponding to process variations from the beginning.
이와같이 본 발명에서는 액티브영역의 폭을 미리 부터 다르게 설정함으로써 공정사의 오차를 최소화하고 이로써 전기적 특성상의 안정성을 유지할 수 있다.Thus, in the present invention, by setting the width of the active region differently in advance, it is possible to minimize the error of the process company and thereby to maintain the stability on the electrical characteristics.
Claims (4)
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| KR1019950040126A KR0161808B1 (en) | 1995-11-07 | 1995-11-07 | Nand-type non-volatile semiconductor memory device & method for making the same |
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