KR0159787B1 - Method for forming three-layer resist pattern - Google Patents
Method for forming three-layer resist pattern Download PDFInfo
- Publication number
- KR0159787B1 KR0159787B1 KR1019920013122A KR920013122A KR0159787B1 KR 0159787 B1 KR0159787 B1 KR 0159787B1 KR 1019920013122 A KR1019920013122 A KR 1019920013122A KR 920013122 A KR920013122 A KR 920013122A KR 0159787 B1 KR0159787 B1 KR 0159787B1
- Authority
- KR
- South Korea
- Prior art keywords
- resist
- layer
- layer resist
- pattern
- sog
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/095—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/11—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
Landscapes
- Engineering & Computer Science (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
본 발명은 고집적 반도체소자의 3층 레지스트 패턴형성방법에 관한 것으로, 하층레지스트패턴 형성시 웨이퍼 가장자리에 잔여레지스트가 남지 않도록 하기 위하여, 웨이퍼 상부면에 하층레지스트, SOG층 및 상층레지스트를 적층하되,하층레지스트 상부면에 SOG층을 웨이퍼 가장자리에서도 완전히 덮도록 도포하고, SOG층 상부면을 웨이퍼 가장자리에서도 완전히 덮도록 상층 레지스트를 도포하는 단계와, 상층레지스트 상부면에 패턴이 형성된 마스크를 올려놓고 광을 상층레지스트로 노광시킨는 단계와, 노광된 상층레지스트를 현상공정으로 제거하여 상층레지스트 패턴을 형성하과 노출된 SOG층을 제거하여 SOG층 패턴을 형성하는단계와, O2플라즈마 RIE 공정으로 상층레지스트 패턴과 노출된 하층레지스트를 제거하여 하층 레지스트 패턴을 형성하는 단계로 이루어지는 기술이다.The present invention relates to a method for forming a three-layer resist pattern of a highly integrated semiconductor device, in order to prevent residual resist from remaining on the wafer edge when forming a lower resist pattern, a lower layer resist, an SOG layer, and an upper layer resist are laminated on the upper surface of the wafer. Applying an SOG layer on the top surface of the resist so as to completely cover the wafer edge, and applying an upper layer resist so as to completely cover the SOG layer on the wafer edge, and placing a patterned mask on the top surface of the upper layer resist Exposing the resist with the resist, removing the exposed upper resist by a developing process to form an upper resist pattern, and removing the exposed SOG layer to form an SOG layer pattern; and exposing the upper resist pattern and the exposed by O 2 plasma RIE process. Removing the lower layer resist to form a lower layer resist pattern A technique comprising step.
Description
제1도는 웨이퍼의 상부면에 칩이 형성될 부분을 도시한 평면도.1 is a plan view showing a portion where a chip is to be formed on an upper surface of a wafer;
제2a도 내지 제2e도는 종래기술로 3층 레지스트 패턴의 형성 단계를 제1도의 A-A'를 F다라 도시한 단면도.2A to 2E are cross-sectional views showing A-A 'in FIG. 1 as the step of forming a three-layer resist pattern in the prior art.
제3a도 및 제 3b도는 본 발명의 제1실시예에 의해 3층 레지스트 패턴의 형성단계를 제1도의 A-A'를 다라 도시한 단면도.3A and 3B are cross-sectional views illustrating the step of forming a three-layer resist pattern according to the first embodiment of the present invention, taken along the line A-A 'of FIG.
제4a도 및 제4b도는 본 발명의 제2실시예에 의해 3층 레지스트 패턴의 형성단계를 제1도의 A-A'를 따라 도시한 단면도.4A and 4B are cross-sectional views taken along the line AA ′ of FIG. 1 showing the step of forming a three-layer resist pattern according to the second embodiment of the present invention.
* 도면의 주요부분에 대한 부호설명* Explanation of symbols on the main parts of the drawings
1 : 웨이퍼 2 : 하층레지스트1 wafer 2 lower layer resist
2A : 하층레지스트 패턴 3 : SOG층2A: lower layer resist pattern 3: SOG layer
3A : SOG층 패턴 4 : 상층레지스트3A: SOG layer pattern 4: upper layer resist
4A : 상층레지스트패턴 5 : 마스크4A: upper layer resist pattern 5: mask
6 : 잔여레지스트6: residual resist
본 발명은 고집적 반도체 소자의 3층 레지스트 패턴 공정밥법에 관한 것으로, 특히 3층 레지스트 패턴 공정밥법에 관한 것으로, 특히 3층 레지스트 패턴 공정진행중에 발생하는 오염물질을 제거하는 공정방법에 관한 것이다.The present invention relates to a three-layer resist pattern process method of a highly integrated semiconductor device, and more particularly to a three-layer resist pattern process method, and more particularly to a process method for removing contaminants generated during the process of the three-layer resist pattern process.
3층 레지스트(Tri-level Resist) 패턴공정은 먼저 패턴을 형성하고자하는 물질층 상부에 하층레지스트/SOG층/상층레지스트를 순차적으로 적층한 다음, 상층레지스트, SOG층, 하층레지스트를 각각 제거하는 공정순서로 이루어진다.Tri-level resist pattern process is a process of first laminating the lower layer resist / SOG layer / upper layer layer on top of the material layer to form the pattern, and then removing the upper layer layer, the SOG layer, and the lower layer layer, respectively. In order.
웨이퍼 상부에 3층 레지스트패턴을 형성하는 단계를 제2a도 내지 제2e도에 되시된 종래기술을 설명하기로 한다.Forming a three-layer resist pattern on the wafer will be described with the prior art as shown in FIGS. 2A through 2E.
제1도는 웨이퍼(1)에 칩(20)이 형성될 부분을 도시한 것이다.FIG. 1 shows a portion where the chip 20 is to be formed on the wafer 1.
제2a도 내지 제2e도는 종래기술에 의해 감광막패턴의 형성단계를 제1도의 A-A'단면을 따라 도시한 것이다.2A through 2E illustrate a step of forming the photosensitive film pattern according to the related art along the cross-sectional view taken along line AA ′ of FIG. 1.
제2a도는 웨이퍼(1) 상부에 3층 레지스트를 도포하되, SOG층(3)을 하층레지스트(2)의 가장자리(10)는 노출되도록 하층레지스트(2)의 일정부분까지 도포하고, 상층레지스트(4)는 하부의 SOG층(3) 상부면 뿐만 아니라 하층레지스트(2)의 노출된 가장자리까지 완전히 도포한 다음, 패턴이 형성된 마스크(5)를 올려놓고 노광시키는 단계를 도시한 단면도이다.FIG. 2A shows a three-layer resist on top of the wafer 1, applying a SOG layer 3 to a portion of the lower layer resist 2 so that the edge 10 of the lower layer resist 2 is exposed, and the upper layer resist ( 4 is a cross-sectional view showing the step of completely applying not only the upper surface of the lower SOG layer 3 but also the exposed edge of the lower layer resist 2, and then placing and exposing the mask 5 on which the pattern is formed.
제2b는 상츨레지스트(4)의 노광된 상층레지스트를 현상공정으로 제거하여 상층레지스트 패턴(4A)을 형성한 상태의 단면도이다.2B is a cross-sectional view of the state in which the exposed upper layer resist of the upper resist 4 is removed by a developing step to form the upper resist pattern 4A.
제2c도는 노출된 SOG층(3)을 CF4플라즈마로 에칭하여 SOG층 패턴(3A)을 형성한 상태의 단면도이다.2C is a cross-sectional view of the SOG layer pattern 3A formed by etching the exposed SOG layer 3 with CF 4 plasma.
제2d도는 O2플라즈마 RIE(Reative Ion Etching)공정으로 노출된 상층레지스트 패턴(4A)과 하층레지스트(2)를 동시에 식각하여 하층레지스트 패턴(2A)을 형성한 상태의 단면도로서, 노출되는 SOG층 패턴(3A)은 O2플라즈마 RIE공정의 마스크로 작용하게 됨을 알수 있다. 또한 웨이퍼(1)의 가장자리에 하층레지스트(2)와 상층레지스트(4)가 겹쳐진 부분이 두꺼우므로 O2플라즈마 RIE공정에서 완전히 제거되지 않아 잔여레지스트(6)가 남아있음을 도시한다.FIG. 2D is a cross-sectional view of the lower layer resist pattern 2A formed by simultaneously etching the upper layer resist pattern 4A and the lower layer resist 2 exposed by an O 2 plasma RIE (Rative Ion Etching) process, and the exposed SOG layer. It can be seen that the pattern 3A serves as a mask for the O 2 plasma RIE process. In addition, since the overlapped portion of the lower layer resist 2 and the upper layer resist 4 at the edge of the wafer 1 is not completely removed in the O 2 plasma RIE process, it shows that the remaining resist 6 remains.
제2e도는 남아있는 SOG층 패턴(3A)을 제거한 상태의 단면도로서, SOG층 패턴(3A)을 제거하기 위해 BOE 용액에 담그는 공정에서 잔여레지스트(6)가 떨어지게 되어 웨이퍼(1)를 오염시키게 된다.Figure 2e is a cross-sectional view of the remaining SOG layer pattern 3A is removed, the residual resist 6 falls in the process of immersing in the BOE solution to remove the SOG layer pattern 3A to contaminate the wafer (1). .
상기 잔여레지스트는 두께가 얇고 하층레지스트를 식각할 때 이온충격(Ion Bmbardment)을 받았기 때문에 기판과 흡착력이 약하게 되어 BOE 용액에 담그면 쉽게 떨어지게 된다.Since the residual resist was thin and was subjected to ion bombardment when the lower layer resist was etched, the substrate and the adsorption force were weakened, so that the remaining resist easily fell when immersed in the BOE solution.
따라서, 본 발명은 상기의 3층 레지스트 패턴 형성방법에서 잔여레지스트가 남는 것을 방지하기 위하여 SOG층을 하층레지스트의 상부면을 완전히 도포하거나, 상층레지스트를 SOG층의 가장자리 내측으로 도포하는 3층 레지스트 패턴 공정방법을 제공하는데 그목적이 있다.Accordingly, the present invention provides a three-layer resist pattern in which the SOG layer is completely coated on the upper surface of the lower layer resist or the upper layer resist is applied inside the edge of the SOG layer in order to prevent the remaining resist from remaining in the three-layer resist pattern forming method. The purpose is to provide a process method.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하고 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제3a도 및 제3b도는 본 발명의 제1실시예에 의해 3층 레지스트 패턴의 형성 단계를 제1도의 A-A'단면을 따라 도시한 것이다.3A and 3B illustrate a step of forming a three-layer resist pattern according to the first embodiment of the present invention along the A-A 'cross section of FIG.
제3a도는 제2a도와 같이 웨이퍼(1) 상부면에 하층레지스트(2), SOG층(3) 및 상층레지스트(4)를 적층한다음, 패턴이 형성된 마스크(5)를 올려놓고 광을 노광시킨 상태의 단면도로서, SOG층(3)이 하층레지스트(2)을 완전히 덮도록하되 웨이퍼(1)의 가장자리(10)는 노출되도록한 상태를 도시한다.FIG. 3A shows the lower layer resist 2, the SOG layer 3, and the upper layer resist 4 stacked on the upper surface of the wafer 1 as shown in FIG. 2A, and then the mask 5 having the pattern formed thereon is exposed to light. As a cross-sectional view of the state, the SOG layer 3 is completely covered with the lower layer resist 2, but the edge 10 of the wafer 1 is exposed.
제3b도는 노광된 상층 레지스트(4)를 현상공정으로 제거하여 상층레지스트 패턴(도시안됨)을 형성한후, 노출된 SOG층(3)을 CF4플라즈마로 에칭하여 SOG층 패턴(3A)을 형성한 다음, O2플라즈마 같은 공정으로 상츨레지스트 패턴과 노출된 하층레지스트(2)를 제거하여 하층레지스트 패턴(2A)을 형성한 상태의 단면도로소, 웨이퍼 가장자리에는 잔여레지스트가 형성되지 않음을 도시한다.FIG. 3B shows the exposed upper resist pattern 4 by a developing process to form an upper resist pattern (not shown), and then the exposed SOG layer 3 is etched with CF 4 plasma to form the SOG layer pattern 3A. Next, a cross sectional view of the lower layer resist pattern 2A formed by removing the upper resist pattern and the exposed lower layer resist 2 by a process such as an O 2 plasma shows that no residual resist is formed at the wafer edge. .
제4a도 및 제4b도는 본 발명의 제2실시예에 의해 3층 레지스트 패턴의 형성단계를 제1도의 A-A'단면을 따라 도시한 것이다.4A and 4B illustrate a step of forming a three-layer resist pattern according to the second embodiment of the present invention along the cross-section A-A 'of FIG.
제4a는 제 2a도와 같이 웨이퍼(1) 상부면에 하층레지스트(2), SOG층(3) 및 상층레지스트(4)를 적층한 다음, 패턴이 형성된 마스크(5)를 올려놓고 광을 노광시킨 상태의 단면도로서, 하층레지스트(2)가 웨이퍼(1)의 가장자리(10)가 노출되도록 도포하고, SOG층(3)을 하층레지스트(2)의 가장자리 일부가 노출되도록 도포하고, 상층레지스트(4)는 SOG층(3)의 가장자리 일부가 노출되도록 도포한 것을 도시한다.4A is a layer 2, SOG layer 3 and the upper layer resist 4 is laminated on the upper surface of the wafer 1 as shown in FIG. 2A, and then the mask 5 on which the pattern is formed is placed and the light is exposed. As a cross-sectional view of the state, the lower layer resist 2 is applied so that the edge 10 of the wafer 1 is exposed, and the SOG layer 3 is applied so that a part of the edge of the lower layer resist 2 is exposed, and the upper layer resist 4 is exposed. ) Shows the coating so that a part of the edge of the SOG layer 3 is exposed.
재4b도는 제3b도와 동일한 방법으로 상츨레지스트 패턴(도시안됨)을 형성하고, 그하부에 SOG층 패턴(3A)을 형성한 다음, 상층래지스트 패턴과 노출되는 하층레지스트(2)를 제거하여 하층레지스트 패턴(2A)을 형성한 상태의 단면도로서, 웨이퍼(1) 가장자리에는 잔여레지스트가 형성되지 않음을 도시한다.In FIG. 4B, an upper resist pattern (not shown) is formed in the same manner as in FIG. 3B, an SOG layer pattern 3A is formed thereunder, and then the lower resist is exposed by removing the upper resist pattern and the lower resist 2 It is sectional drawing of the state which formed the resist pattern 2A, and shows that no residual resist is formed in the edge of the wafer 1. As shown in FIG.
상기한 본 발명은 하층레지스트 식각공정에서 잔류레지스트가 남지 않기 때문에 BOE용액에서 SOG층 패턴을제거할 때 잔류레지스트에 의해 웨이퍼가 오염될 염려가 없는 것이다.In the present invention described above, there is no fear of contamination of the wafer by the residual resist when removing the SOG layer pattern from the BOE solution because no residual resist remains in the lower layer resist etching process.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920013122A KR0159787B1 (en) | 1992-07-23 | 1992-07-23 | Method for forming three-layer resist pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920013122A KR0159787B1 (en) | 1992-07-23 | 1992-07-23 | Method for forming three-layer resist pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940002663A KR940002663A (en) | 1994-02-17 |
| KR0159787B1 true KR0159787B1 (en) | 1999-02-18 |
Family
ID=19336813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920013122A KR0159787B1 (en) | 1992-07-23 | 1992-07-23 | Method for forming three-layer resist pattern |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0159787B1 (en) |
-
1992
- 1992-07-23 KR KR1019920013122A patent/KR0159787B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940002663A (en) | 1994-02-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR900005565A (en) | Improved pattern formation method | |
| KR0159787B1 (en) | Method for forming three-layer resist pattern | |
| KR0156316B1 (en) | Patterning method of semiconductor device | |
| JPH02321A (en) | Method of forming aperture | |
| US4612274A (en) | Electron beam/optical hybrid lithographic resist process in acoustic wave devices | |
| JPH06105686B2 (en) | Method for manufacturing semiconductor device | |
| JPS58166725A (en) | Forming method for opening section of laminated coating layer | |
| KR100499399B1 (en) | Manufacturing Method of Stacked Via Contact | |
| JPH01149435A (en) | Manufacture of semiconductor device | |
| KR100265588B1 (en) | Manufacture of semiconductor device | |
| KR950010853B1 (en) | Reverse contact hole patterning method of semiconductor device | |
| KR0183045B1 (en) | Patterning method of photoresist | |
| KR100235936B1 (en) | Method for manufacturing resist pattern | |
| KR940009769A (en) | Method of forming photoresist fine pattern of semiconductor device | |
| KR960006564B1 (en) | Method of forming micropattern of semiconductor devices | |
| KR20000038673A (en) | Method for preventing contamination of semiconductor wafer | |
| KR100289664B1 (en) | Manufacturing Method of Exposure Mask | |
| KR980005543A (en) | METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR | |
| JPS6042833A (en) | Formation of fine pattern | |
| KR940016494A (en) | How to Form Metal Via Contact Holes | |
| KR970008495A (en) | A mask for a lead-on chip wafer, a manufacturing method for forming an adhesive on a wafer using the same, and a wafer structure using the same | |
| JPH01216525A (en) | Pattern forming method for semiconductor device | |
| JP2000353748A (en) | Manufacture of semiconductor device | |
| JPS6216536B2 (en) | ||
| JPH05251336A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100726 Year of fee payment: 13 |
|
| LAPS | Lapse due to unpaid annual fee |