KR0155768B1 - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
KR0155768B1
KR0155768B1 KR1019940020295A KR19940020295A KR0155768B1 KR 0155768 B1 KR0155768 B1 KR 0155768B1 KR 1019940020295 A KR1019940020295 A KR 1019940020295A KR 19940020295 A KR19940020295 A KR 19940020295A KR 0155768 B1 KR0155768 B1 KR 0155768B1
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South Korea
Prior art keywords
heat treatment
capacitor
plasma
film
tantalum pentoxide
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KR1019940020295A
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Korean (ko)
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KR960009171A (en
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권기원
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김광호
삼성전자주식회사
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Publication of KR960009171A publication Critical patent/KR960009171A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors

Abstract

오산화탄탈륨 유전체막을 구비하는 커패시터의 제조방법이 개시되어 있다. 커패시터의 하부전극 상에 유전체막으로서 오산화탄탈륨막을 형성한 다음, 플라즈마-O2열처리와 추가 열처리를 연속으로 실시한다. 이어서, 상기 오산화탄탈륨막 상에 커패시터의 상부전극을 형성한다. 종래방법에 의한 커패시터에 비해 동등한 전기적 특성을 가지면서 생산성을 월등하게 향상시킬 수 있다.A method of manufacturing a capacitor having a tantalum pentoxide diode film is disclosed. A tantalum pentoxide film is formed as a dielectric film on the lower electrode of the capacitor, and then plasma-O 2 heat treatment and further heat treatment are successively performed. Subsequently, an upper electrode of the capacitor is formed on the tantalum pentoxide film. Compared with the capacitor by the conventional method, while having the same electrical characteristics, productivity can be improved significantly.

Description

오산화탄탈륨 유전체막을 구비하는 커패시터 제조방법Capacitor manufacturing method comprising tantalum pentoxide pentoxide film

제1도는 종래방법에 의해 제조된 커패시터에 있어서, 등가산화막 두께의 플라즈마 전력 의존성을 나타내는 그래프.1 is a graph showing plasma power dependence of equivalent oxide film thickness in a capacitor manufactured by a conventional method.

제2도는 종래방법에 의해 제조된 커패시터에 있어서, 누설전류의 플라즈마 전력 의존성을 나타내는 그래프.2 is a graph showing plasma power dependency of leakage current in a capacitor manufactured by a conventional method.

제3a도 내지 제3d도는 본 발명에 의한 커패시터 제조방법을 설명하기 위한 단면도들.3a to 3d are cross-sectional views for explaining a capacitor manufacturing method according to the present invention.

제4도는 본 발명에 의해 제조된 커패시터에 있어서, 등가산화막 두께의 플라즈마 전력 의존성을 나타내는 그래프.4 is a graph showing plasma power dependence of equivalent oxide film thickness in a capacitor manufactured by the present invention.

제5도는 본 발명에 의해 제조된 커패시터에 있어서, 누설전류의 플라즈마 절력 의존성을 나타내는 그래프.5 is a graph showing the plasma force dependency of the leakage current in the capacitor manufactured by the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 반도체기판 12 : 하부전극10 semiconductor substrate 12 lower electrode

14 : Ta2O5유전체막 18 : 상부전극14: Ta 2 O 5 dielectric film 18: upper electrode

본 발명은 반도체장치의 커패시터 제조방법에 관한 것으로, 특히 오산화탄탈륨(Ta2O5)유전체막을 구비하는 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor manufacturing method of a semiconductor device, and more particularly, to a capacitor manufacturing method including a tantalum pentoxide (Ta 2 O 5) dielectric film.

DRAM(Dynamic Random Access Memory) 장치의 집적도가 증가함에 따라, 제한된 셀 면적내에서 커패시턴스를 증가시키기 위한 많은 방법들이 제안되고 있는데, 보통 다음의 세가지로 나뉘어질 수 있다. 즉, ① 유전체막을 박막화하는 방법, ②커패시터의 유효면적을 증가시키는 방법, 및 ③유전상수가 큰 물질을 사용하는 방법이 그것이다.As the density of dynamic random access memory (DRAM) devices increases, many methods for increasing capacitance within a limited cell area have been proposed, which can be generally divided into three types. That is, (1) a method of thinning a dielectric film, (2) increasing the effective area of a capacitor, and (3) using a material having a large dielectric constant.

이 중, 첫번째 방법은 유전체막의 두께를 100Å 이하로 박막화하는 경우 파울러 노드하임(Fowler-Nordheim) 전류에 의해 신뢰성이 저하되므로 대용량 메모리소자에 적용하기가 어렵다는 단점이 있다.Among these, the first method has a disadvantage in that it is difficult to apply to a large-capacity memory device when the thickness of the dielectric film is reduced to 100 Å or less because reliability is degraded by Fowler-Nordheim current.

두번째 방법은, 3차원 구조의 커패시터를 제조하기 위하여 공정이 복잡해지고 공정단가가 증가하게 되는 단점이 있다.The second method has a disadvantage in that the process becomes complicated and the process cost increases to manufacture a three-dimensional capacitor.

따라서, 최근에는 세번째 방법, 즉 고유전상수를 갖는 물질, 예컨데 오산화탄탈륨(Ta2O5),SrTiO3,BaSrTiO3,PZT,PLZT 등의 산화물을 유전체막으로 사용하여 플래너(planner)형의 커패시터를 제조하려는 시도가 활발하게 진행되고 있다. 특히, 상기한 산화물 중에서 유전상수와 재료 자체의 열역학적 안정성 측면등에서 오산화탄탈륨이 현재 가장 유망한 재료로서 사용되고 있다.Therefore, recently, a third method, that is, specific materials, for example tantalum pentoxide (Ta 2 O 5), SrTiO 3, BaSrTiO 3, PZT, capacitor-type planar with the oxide such as PLZT a dielectric film (planner) having a dielectric constant Attempts to manufacture are actively underway. In particular, tantalum pentoxide is currently used as the most promising material in view of the dielectric constant and thermodynamic stability of the material itself.

상기 오산화탄탈륨을 형성하기 위한 방법으로 초기에 연구되었던 스퍼터링(sputtering) 방법은, 고집적 소자의 복잡한 구조에서 단차도포성(step coverage)가 불량하기 때문에 수득된 막의 특성이 우수함에도 불구하고 현재는 거의 연구되고 있지 않다. 한편, 화학기상증착(Chemical Vapor Deposition; 이하 CVD라 한다) 방법에 의해 성장된 막은, 증착 직후의 막의 누설전류가 큼에도 불구하고 복잡한 구조에서의 단차 도포성이 우수하기 때문에 지금까지 많은 연구가 진행되고 있다.The sputtering method, which was initially studied as a method for forming the tantalum pentoxide, is almost studied despite the excellent properties of the obtained film due to poor step coverage in the complex structure of the highly integrated device. It is not becoming. On the other hand, the films grown by the chemical vapor deposition (CVD) method has a lot of research so far despite the high leakage current of the film immediately after the deposition is excellent in step coverage in a complex structure It is becoming.

상기한 CVD 오산화탄탈륨막의 높은 누설전류를 감소시키기 위하여 쉰리키(H.Shinriki)등은 막의 증착 직후에 자외선이 조사되는 오존분위기에서 막을 열처리한 다음 연속으로 고온의 산소분위기에서 열처리하는 소위, 2단계 열처리(2-step anneal)법을 개발하였다(참조문헌: IEEE Trans. on Electron Devices Vol.38, No.3, pp.455-463,1991). 또한, 스즈키(Suzuki)등은 플라즈마-O2 열처리법을 제안하였다(참조문헌: Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials, 1993,pp.862-864). 그러나, 상기한 방법들은 다음과 같은 문제점들을 갖고 있다.In order to reduce the high leakage current of the CVD tantalum pentoxide film, H. Shinriki et al. Heat treatment the film in an ozone atmosphere irradiated with UV light immediately after the deposition of the film, followed by continuous heat treatment in a high temperature oxygen atmosphere. A 2-step anneal method has been developed (see, IEEE Trans.on Electron Devices Vol. 38, No. 3, pp.455-463,1991). Suzuki et al. Also proposed a plasma-O2 heat treatment method (Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials, 1993, pp. 862-864). However, the above methods have the following problems.

먼저, 2단계 열처리법의 경우는, 자외선 하에서 오존처리를 진행함에 있어서 웨이퍼당 15분간의 열처리 시간이 소요되는데, 이는 25매의 웨이퍼와 공정을 모니터하기 위해 추가되는 2∼3매의 웨이퍼를 포함할 경우 총 소요시간이 6시간 이상이 되기 때문에 양산을 고려할 때는 경제성이 재검토되어야 한다.First, in the two-stage heat treatment method, an ozone treatment under ultraviolet light takes 15 minutes of heat treatment time per wafer, which includes 25 wafers and 2-3 wafers added to monitor the process. In this case, the total travel time is 6 hours or more, so the economic feasibility should be reviewed when considering mass production.

플라즈마-O2열처리법의 경우는, 10nm 내외의 매우 얇은 오산화탄탈륨막이 플라즈마에 직접 노출될 경우 크게 손상될 수 있다.In the case of the plasma-O 2 heat treatment method, a very thin tantalum pentoxide film of about 10 nm can be greatly damaged when directly exposed to the plasma.

제1도는 상술한 여러가지 종래방법들에 의해 각각 제조된 커패시터에 있어서 등가산화막 두께의 플라즈마 전력(power) 의존성을 도시한 그래프이다. 여기서, ●는 폴리실리콘으로 이루어진 커패시터의 하부전극 상에 오산화탄탈륨막을 약 9nm정도의 두께로 침적한 다음, 자외선 오존분위기에서 열처리한 경우이며, ○는 자외선 오존분위기와 고온의 산소분위기에서 2단계 열처리한 경우, □는 플라즈마-O2열처리한 경우를 각각 나타낸다.FIG. 1 is a graph showing plasma power dependence of equivalent oxide film thickness in capacitors manufactured by the various conventional methods described above. Where ● is a case where a tantalum pentoxide pentoxide film is deposited to a thickness of about 9 nm on a lower electrode of a polysilicon capacitor and heat-treated in an ultraviolet ozone atmosphere, and ○ is a two-stage heat treatment in an ultraviolet ozone atmosphere and a high temperature oxygen atmosphere. In each case, □ indicates a case where the plasma-O 2 heat treatment was performed.

제1도를 참조하면, 상기 오산화탄탈륨막을 400℃, 플라즈마-O2분위기에서 3분 정도 열처리한 경우(□), 플라즈마 전력이 증가함에 따라 막의 등가산화막 두께가 급격히 증가하였다. 이러한 등가산화막 두께의 증가는, 막의 하부, 즉 폴리실리콘 하부전극과 오산화탄탈륨막의 계면에서 폴리실리콘의 산화에 의한 계면산화막이 증가했기 때문인 것으로 밝혀졌다. 이와 같이 계면산화막이 증가하는 이유는, 플라즈마-O2열처리 중에 산소가 얇은 오산화탄탈륨막을 확산하였기 때문이다.Referring to FIG. 1, when the tantalum pentoxide film was heat-treated at 400 ° C. for 3 minutes in a plasma-O 2 atmosphere (□), the equivalent oxide film thickness of the film rapidly increased as plasma power was increased. This increase in the equivalent oxide film thickness was found to be due to an increase in the interfacial oxide film due to oxidation of polysilicon at the bottom of the film, that is, at the interface between the polysilicon lower electrode and the tantalum pentoxide film. The reason why the interfacial oxide film is increased in this manner is because oxygen diffused the thin tantalum pentoxide film during the plasma-O 2 heat treatment.

제2도는 자외선 오존분위기와 고온 산소분위기의 2단계 열처리법과 플라즈마-O2열처리법에 의해 각각 제조된 커패시터에 있어서, 누설전류의 플라즈마 전력 의존성을 나타낸 그래프이다. 여기서, □와 ■는 각각, 2단계 열처리법에 의한 커패시터에 양의 바이어스(positive bias)와 음의 바이어스(negative bias)를 인가한 경우이며, ○와 ●는 각각, 플라즈마-O2열처리법에 의한 커패시터에 양의 바이어스와 음의 바이어스를 인가한 경우이다.FIG. 2 is a graph showing the plasma power dependence of leakage current in a capacitor manufactured by a two-step heat treatment method and a plasma-O 2 heat treatment method of an ultraviolet ozone atmosphere and a high temperature oxygen atmosphere. Where □ and ■ are the cases where positive bias and negative bias are applied to the capacitor by the two-step heat treatment method, and ○ and ● are respectively applied to the plasma-O 2 heat treatment method. This is the case where positive bias and negative bias are applied to the capacitor.

제2도를 참조하면, 자외선 오존분위기와 고온의 산소분위기에서 2단계 열처리를 실시한 경우(□,■)보다 플라즈마-O2열처리를 실시한 경우(○,●) 커패시터의 누설전류가 많았으며, 플라즈마 전력을 증가시켜도 누설전류가 줄어들지 않았다. 참고로, 오산화탄탈륨막을 유전체막으로 사용하는 커패시터는 양의 바이어스를 가했을 때 동작전압에서 누설전류가 크게 나타난다.Referring to FIG. 2, when the plasma-O 2 heat treatment (○, ●) was performed in the UV ozone atmosphere and the high temperature oxygen atmosphere (□, ■), the leakage current of the capacitor was higher. Increasing the power did not reduce the leakage current. For reference, a capacitor using a tantalum pentoxide film as a dielectric film shows a large leakage current at an operating voltage when a positive bias is applied.

따라서, 본 발명의 목적은 상술한 종래방법의 문제점들을 해결할 수 있는 TaO 유전체막을 구비하는 커패시터의 제조방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor having a TaO dielectric film that can solve the problems of the conventional method described above.

상기 목적을 달성하기 위하여 본 발명은, 반도체기판 상에 하부전극을 형성하는 단계, 상기 하부전극 상에 유전체막으로서 오산화탄탈륨막을 형성하는 단계, 상기 오산화탄탈륨막이 형성된 결과물에 플라즈마-O2열처리와 추가 열처리를 연속적으로 실시하는 단계 및 상기 오산화탄탈륨막 상에 상부전극을 형성하는 단계를 구비하는 것을 특징으로 하는 커패시터의 제조방법을 제공한다.In order to achieve the above object, the present invention, forming a lower electrode on the semiconductor substrate, forming a tantalum pentoxide film as a dielectric film on the lower electrode, plasma-O 2 heat treatment and addition to the resultant formed tantalum pentoxide film And continuously forming a heat treatment and forming an upper electrode on the tantalum pentoxide film.

본 발명의 바람직한 실시예에 의하면, 상기 플라즈마-O2열처리법에서 플라즈마 전력을 300watt 이하로 사용한다. 상기 플라즈마-O2열처리는 30초∼10분간 진행하는 것이 바람직하다.According to a preferred embodiment of the present invention, the plasma power is used at 300 watt or less in the plasma-O 2 heat treatment method. Preferably, the plasma-O 2 heat treatment is performed for 30 seconds to 10 minutes.

상기 추가 열처리 방법으로, 산소 또는 질소 분위기에서 400∼800℃ 정도의 온도에서 로(furnace) 열처리 방법을 사용하는 것이 바람직하며, 급열 처리(Rapid Thermal Anneal) 방법을 사용할 수도 있다. 상기 급열 처리방법을 사용학 경우 산소 또는 질소 분위기에서 실시할 수 있다.As the additional heat treatment method, it is preferable to use a furnace heat treatment method at a temperature of about 400 to 800 ° C. in an oxygen or nitrogen atmosphere, and a rapid thermal annealing method may be used. In the case of using the rapid treatment method may be carried out in an oxygen or nitrogen atmosphere.

본 발명에 의하면, 생산성이 우수한 플라즈마-O2열처리를 실시한 후 플라즈마에 의한 손상(damage)을 제거하기 위해 고온의 추가 열처리를 실시함으로써 종래방법에 의한 커패시터와 동등한 전기적 특성을 유지하면서 생산성을 향상시킬 수 있다.According to the present invention, after performing the plasma-O 2 heat treatment having excellent productivity, a high temperature additional heat treatment is performed to remove plasma damage, thereby improving productivity while maintaining electrical characteristics equivalent to those of the capacitor according to the conventional method. Can be.

이하, 첨부한 도면을 참조하여 본 발명을 더욱 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

제3a도 내지 제3d도는 본 발명에 의한 커패시터 제조방법을 설명하기 위한 단면도들이다.3A to 3D are cross-sectional views illustrating a method of manufacturing a capacitor according to the present invention.

제3a도는 하부전극(12) 및 유전체막(14)을 형성하는 단계를 도시한다. 웨이퍼(10) 상에 도전물질, 예컨데 불순물이 도우프된 폴리실리콘을 침적하고, 이를 리소그라피 공정으로 패터닝함으로써 커패시터의 하부전극(12)을 형성한다. 이어서, 저압화확기상증착(Low Pressure Chamical Vapor Deposition; LPCVD) 방법에 의해 Ta(OC2H5)5와 O2등의 원료를 이용하여 오산화탄탈륨(Ta2O5)을 50∼300Å 정도의 두께로 상기 하부전극(12) 상에 침적함으로써 커패시터의 유전체막(14)을 형성한다. 본 발명의 실시예에서는 오산탄탈룸막(14)을 84Å두께로 형성하였다.3A shows the steps of forming the lower electrode 12 and the dielectric film 14. The lower electrode 12 of the capacitor is formed by depositing polysilicon doped with a conductive material such as impurities on the wafer 10 and patterning the same by lithography. Subsequently, the thickness of tantalum pentoxide (Ta 2 O 5 ) is about 50 to 300 kPa using raw materials such as Ta (OC 2 H 5 ) 5 and O 2 by a low pressure chemical vapor deposition (LPCVD) method. The dielectric film 14 of the capacitor is formed by depositing on the lower electrode 12. In the embodiment of the present invention, the tantalum tantalum film 14 was formed to a thickness of 84 mm 3.

제3b도는 플라즈마-O2열처리를 실시하는 단계를 도시한다. 상기 오산화탄탈류 유전체막(14)이 형성된 웨이퍼에 산소 플라즈마 분위기(16)에서 400℃, 3분간 열처리를 실시한다. 이때, 플라즈마 전력은 150, 300 및 450watt로 변화시켰다.3b shows the step of performing a plasma-O 2 heat treatment. The wafer on which the tantalum pentoxide dielectric film 14 is formed is subjected to heat treatment at 400 ° C. for 3 minutes in an oxygen plasma atmosphere 16. At this time, the plasma power was changed to 150, 300 and 450 watts.

제3c도는 고온 열처리를 실시하는 단계를 도시한다. 상술한 바와 같이 산소 플라즈마 분위기에서 열처리를 실시한 다음, 계속해서, 여러장의 웨이퍼(W)들을 동시에 처리할 수 있는 튜브 로(tube furnace;T)에서 산소분위기 하에서 400∼800℃의 온도에서 30분간 추가 열처리를 실시한다. 상기한 고온 산소분의기의 추가 열처리는 이전단계의 플라즈마-O2열처리에 의한 플라즈마 손상을 제거하기 위한 목적으로 실시된다.3C shows a step of performing a high temperature heat treatment. As described above, heat treatment is performed in an oxygen plasma atmosphere, and then, in a tube furnace (T) capable of simultaneously processing a plurality of wafers (W), an additional 30 minutes at a temperature of 400 to 800 ° C. under an oxygen atmosphere is performed. Heat treatment is performed. The additional heat treatment of the hot oxygen powder separator is carried out for the purpose of removing plasma damage by the plasma-O 2 heat treatment of the previous step.

제3d도는 상부전극(18)을 형성하는 단계를 도시한다. 상기 오산화탄탈륨 유전체막(14) 상에 도전물질, 예컨데 질화티타늄(TiN)을 900Å 정도의 두께로 침적하고, 이를 리소그라피 공정으로 패터닝함으로써 커패시터의 상부전극(18)을 형성한다.3d illustrates the step of forming the upper electrode 18. A conductive material, such as titanium nitride (TiN), is deposited on the tantalum pentoxide pentoxide layer 14 to a thickness of about 900 kV and patterned by a lithography process to form the upper electrode 18 of the capacitor.

이하, 상술한 본 발명의 제조방법에 의해 수득된 커패시터의 전기적 특성을 실험결과를 참조하여 살펴보기로 한다.Hereinafter, the electrical characteristics of the capacitor obtained by the above-described manufacturing method of the present invention will be described with reference to the experimental results.

제4도는 본 발명에 의해 제조된 커패시터에 있어서, 등가산화막 두께의 플라즈마 전력 의존성을 나타내는 그래프다. 여기서, ○는 본 발명의 플라즈마-O2열처리와 고온 산소분위기 추가 열처리에 의해 제조된 커패시터의 특성을 나타내고, ●는 종래의 자외선 오존분위기에서 열처리한 커패시터의 특성을 나타내고, □는 종래의 자외선 오존분위기와 고온의 산소분위기에서 2단계 열처리한 커패시터의 특성을 각각 나타낸다.4 is a graph showing the plasma power dependency of the equivalent oxide film thickness in the capacitor manufactured by the present invention. Here, ○ represents the characteristics of the capacitor prepared by the plasma-O 2 heat treatment and the high temperature oxygen atmosphere additional heat treatment of the present invention, ● represents the characteristics of the capacitor heat-treated in the conventional ultraviolet ozone atmosphere, □ is the conventional ultraviolet ozone The characteristics of the capacitor subjected to the two-stage heat treatment in the atmosphere and high temperature oxygen atmosphere are shown respectively.

제4도를 참조하면, 본 발명에 의한 커패시터(○)가 지금까지 전기적 특성이 가장 우수한 것으로 알려진 자외선 오존분위기와 고온 산소분위기의 2단계 열처리법에 의한 커패시터(□)와 동일한 등가산화막 두께를 얻었음을 볼 수 있다. 또한, 플라즈마 전력이 150∼300watt 사이에서 변화하더라도 등가산화막의 두께에 변화가 없이 안정된 특성을 갖고 있음을 알 수 있다. 이는 본 발명에 의한 커패시터 제조방법이 주변의 공정변수에 둔감한 안정된 공정이라는 것을 반증한다.Referring to FIG. 4, the capacitor (○) according to the present invention obtained the same equivalent oxide film thickness as that of the capacitor (□) by the two-stage heat treatment method of the ultraviolet ozone atmosphere and the high temperature oxygen atmosphere, which are known to have the best electrical properties. Can be seen. In addition, it can be seen that even if the plasma power varies between 150 and 300 watts, the equivalent oxide film has stable characteristics without change. This proves that the capacitor manufacturing method according to the present invention is a stable process insensitive to surrounding process variables.

제5도는 본 발명에 의해 제조된 커패시터에 있어서, 누설전류 밀도의 플라즈마 전력 의존성을 나타내는 그래프이다. 여기서, ○와 ●는 각각, 본 발명에 의한 커패시터에 양의 바이어스와 음의 바이어스를 인가한 경우를 나타내고, □와 ■는 각각, 종래의 자외선 오존분위기와 고온의 산소분위기에서 2단계 열처리한 커패시터에 양의 바이어스와 음의 바이어스를 인가한 경우를 나타낸다.5 is a graph showing the plasma power dependency of the leakage current density in the capacitor manufactured by the present invention. Here, ○ and ● represent the cases where positive and negative biases are applied to the capacitor according to the present invention, respectively, and □ and ■ are the capacitors subjected to the two-step heat treatment in the conventional ultraviolet ozone atmosphere and the high temperature oxygen atmosphere, respectively. This is a case where positive bias and negative bias are applied.

제5도를 참조하며, 본 발명에 의한 커패시터(○,●)가 종래의 2단계 열처리( □,■)에 의한 커패시터와 동등한 수준의 누설전류를 가짐을 알 수 있다.Referring to Figure 5, it can be seen that the capacitor (○, ●) according to the present invention has a leakage current of the same level as the capacitor by the conventional two-step heat treatment (□, ■).

상기 제4도 및 제5도에 나타난 실험결과에서 볼 수 있듯이, 본 발명의 플라즈마 -O2열처리와 고온 산소분위기 추가 열처리를 연속으로 실시한 커패시터는, 종래의 자외선 오존분위기와 고온 산소분위기에서 2단계 열처리한 커패시터와 동등한 10-6A/cm2의 누설전류 특성을 가진다. 이는, 제2도에서 보이는 것처럼, 종래의 플라즈마-O2열처리에 의한 커패시터의 누설전류 10-4A/cm2`보다 작아 커패시터의 전기적 특성이 우수하다. 또한, 자외선 오존분위기에서의 열처리가 6시간 이상 소요되는 반면, 플라즈마-O2열처리는 1시간 30분이 채 걸리지 않는 공정이므로 생산성이 월등하게 우수하다. 즉, 본 발명은 전기적인 특성을 유지하면서 생산성을 향상시킬 수 있는 공정이다.As can be seen from the experimental results shown in FIGS. 4 and 5, the capacitor subjected to the continuous plasma -O 2 heat treatment and the additional high temperature oxygen atmosphere heat treatment of the present invention has two stages in a conventional ultraviolet ozone atmosphere and a high temperature oxygen atmosphere. It has a leakage current characteristic of 10 -6 A / cm 2 equivalent to that of the heat-treated capacitor. This, as shown in Figure 2, is less than the leakage current 10 -4 A / cm 2 'of the capacitor by the conventional plasma-O 2 heat treatment is excellent in the electrical characteristics of the capacitor. In addition, the heat treatment in the ultraviolet ozone atmosphere takes 6 hours or more, whereas the plasma-O 2 heat treatment is a process that takes less than 1 hour and 30 minutes, so the productivity is excellent. That is, the present invention is a process that can improve productivity while maintaining electrical characteristics.

또한 상기 제4도에 도시된 바와 같이, 종래의 자외선 오존분위기와 고온 산소분위기에서 2단계 열처리법의 경우는 자외선 오존분위기의 열처리후 고온의 산소분위기에서 열처리하는 과정에서 등가산화막의 두께가 10Å 이상 민감하게 변화되고, 이에 따라 등가산화막의 두께를 정확하게 조절하기가 매우 힘들다. 반면에, 본 발명에 의하면, 상기 제1도와 제4도의 데이터를 비교해볼 때, 플라즈마 전력 300watt까지 플라즈마 -O2열처리 공정의 등가산화막 두께에 대하여 플라즈마-O2열처리후의 고온 추가 열처리 공정에서 등가산화막 두께가 2Å 이내로 변화하기 때문에, 등가산화막의 두께가 공정 변수에 둔감하여 신뢰성있는 공정을 확보할 수 있다.In addition, as shown in FIG. 4, in the case of the two-step heat treatment method in the conventional ultraviolet ozone atmosphere and the high temperature oxygen atmosphere, the equivalent oxide film has a thickness of 10 kPa or more in the process of heat treatment in the high temperature oxygen atmosphere after the ultraviolet ozone atmosphere. Sensitively changed, it is very difficult to accurately control the thickness of the equivalent oxide film. On the other hand, in accordance with this invention, the equivalent oxide film in said first help fourth degree when compared to the data, the plasma power to the plasma 300watt -O 2 -O 2 plasma after adding a high temperature heat treatment with respect to the equivalent oxide film thickness of the heat treatment process the heat-treating step Since the thickness changes within 2 kW, the thickness of the equivalent oxide film is insensitive to process variables, thereby ensuring a reliable process.

본 발명의 바람직한 다른 실시예에 의하면, 플라즈마-O2열처리후의 고온의 추가 열처리를 질소분위기에서 실시할 수 있다.According to another preferred embodiment of the present invention, the high temperature additional heat treatment after the plasma-O 2 heat treatment can be performed in a nitrogen atmosphere.

본 발명의 바람직한 다른 실시예에 의하면, 상기 고온의 추가 열처리를 급열처리 (Rapid Thermal Anneal)방법으로 실시할 수 있다.According to another preferred embodiment of the present invention, the high temperature additional heat treatment may be performed by a rapid thermal annealing method.

이상 상술한 바와 같이 본 발명에 의하면, 생산성이 우수한 플라즈마-O2열처리를 실시한 후 플라즈마에 의한 손상(damage)을 제거하기 위해 고온의 추가 열처리를 실시함으로써 종래방법에 의한 커패시터와 동등한 전기적 특성을 유지하면서 생산성을 향상시킬 수 있다.As described above, according to the present invention, after the plasma-O 2 heat treatment with high productivity is performed, the additional heat treatment at high temperature is performed to remove the damage caused by the plasma, thereby maintaining the electrical characteristics equivalent to those of the capacitor according to the conventional method. While improving productivity.

본 발명이 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당분야에서 통상의 지식을 가진 자에 의하여 가능함은 맹백하다.The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

Claims (5)

반도체기판 상에 하부전극을 형성하는 단계, 상기 하부전극 상에 유전체막으로서 오산화탄탈륨막을 형성하는 단계, 상기 오산화탄탈륨막이 형성된 결과물에 플라즈마-O2열처리와 추가 열처리를 연속적으로 실시하는 단계 및 상기 오산화탄탈륨막 상에 상부전극을 형성하는 단계를 구비하는 것을 특징으로 하는 커패시터의 제조방법.Forming a lower electrode on a semiconductor substrate, forming a tantalum pentoxide film as a dielectric film on the lower electrode, continuously performing plasma-O 2 heat treatment and further heat treatment on the resultant product on which the tantalum pentoxide film is formed, and the pentoxide And forming an upper electrode on the tantalum film. 제 1항에 있어서, 상기 플라즈마-O2열처리에서 플라즈마 전력을 300watt 이하로 사용하는 것을 특징으로 하는 커패시터의 제조방법.The method of claim 1, wherein the plasma power is used at 300 watt or less in the plasma-O 2 heat treatment. 제 1항에 있어서, 상기 플라즈마-O2열처리는 30초∼10분간 진행하는 것을 특징으로 하는 커패시터의 제조방법.The method of claim 1, wherein the plasma-O 2 heat treatment is performed for 30 seconds to 10 minutes. 제 1항에 있어서, 상기 추가 열처리로서, 산소 또는 질소분위기에서 400∼800℃ 정도의 온도에서 로(furnace) 열처리하는 방법을 사용하는 것을 특징으로 하는 커패시터의 제조방법.The method of manufacturing a capacitor according to claim 1, wherein as the additional heat treatment, a furnace heat treatment is performed at a temperature of about 400 to 800 ° C. in an oxygen or nitrogen atmosphere. 제 1항에 있어서, 상기 추가 열처리로서, 산소 또는 질소분위기에서 급열처리(Rapid Rhermal Anneal) 방법을 사용하는 것을 특징으로 하는 커패시터의 제조방법.The method of manufacturing a capacitor according to claim 1, wherein, as said additional heat treatment, Rapid Rhermal Anneal method is used in an oxygen or nitrogen atmosphere.
KR1019940020295A 1994-08-17 1994-08-17 Manufacture of semiconductor device KR0155768B1 (en)

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